--- /dev/null
+# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
+
+ LOGICAL_SYNTHESIS = Yosys
+ PHYSICAL_SYNTHESIS = Coriolis
+ DESIGN_KIT = sxlib
+
+# YOSYS_FLATTEN = Yes
+ CHIP = chip
+ CORE = memory
+ MARGIN = 2
+ BOOMOPT = # -A
+ BOOGOPT =
+ LOONOPT =
+ NSL2VHOPT = -vasy # -split -p
+ USE_CLOCKTREE = Yes
+ USE_DEBUG = No
+ USE_KITE = No
+# RM_CHIP = Yes
+
+ NETLISTS = $(shell cat nets.txt)
+# PATTERNS = memory_r
+
+
+ include ./mk/design-flow.mk
+
+
+blif: memory.blif
+vst: memory.vst
+
+lvx: lvx-chip_cts_r
+druc: druc-chip_cts_r
+dreal: dreal-chip_cts_r
+flatph: flatph-chip_cts_r
+view: cgt-chip_cts_r
+
+layout: chip_cts_r.ap
+gds: chip_cts_r.gds
+gds_flat: chip_cts_r_flat.gds
+cif: chip_cts_r.cif
+
+
+view: cgt-chip_cts_r
+sim: asimut-memory_cts_r
--- /dev/null
+#!/usr/bin/env python
+
+from helpers import l, u, n
+
+
+chip = { 'pads.ioPadGauge' : 'pxlib',
+
+ # | Instance | Pad | To Core | From Core | Enable |
+ 'pads.instances' :[
+ # "a" input.
+ [ 'p_a0' , 'a(0)', 'a(0)' ],
+ [ 'p_a1' , 'a(1)', 'a(1)' ],
+ [ 'p_a2' , 'a(2)', 'a(2)' ],
+ [ 'p_a3' , 'a(3)', 'a(3)' ],
+ # "b" input.
+ [ 'p_b0' , 'b(0)', 'b(0)' ],
+ [ 'p_b1' , 'b(1)', 'b(1)' ],
+ [ 'p_b2' , 'b(2)', 'b(2)' ],
+ [ 'p_b3' , 'b(3)', 'b(3)' ],
+ # "f" output.
+ [ 'p_f0' , 'f(0)', 'f(0)' ], # , 'f_oe' ],
+ [ 'p_f1' , 'f(1)', 'f(1)' ], # , 'f_oe' ],
+ [ 'p_f2' , 'f(2)', 'f(2)' ], # , 'f_oe' ],
+ [ 'p_f3' , 'f(3)', 'f(3)' ], # , 'f_oe' ],
+ ],
+ 'pads.south' :
+ [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0' ],
+ 'pads.east' :
+ [ 'p_a2', 'p_a3' , 'p_b3' , 'p_b2' ],
+ 'pads.north' :
+ [ 'p_b1', 'p_vddeck_0', 'p_b0' , 'p_vsseck_0', 'rst' ],
+ 'pads.west' :
+ [ 'p_f3', 'p_f2' , 'p_clk_0', 'p_f1' , 'p_f0' ],
+ 'core.size' : ( l( 2500), l( 2500) ),
+ 'chip.size' : ( l(4200), l(4200) ),
+ 'pads.useCoreSize' : True,
+ 'chip.clockTree' : True,
+ }
+
--- /dev/null
+
+from Hurricane import DebugSession
+
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) )
--- /dev/null
+# -*- Mode:Python -*-
+
+import os
+import Cfg
+import CRL
+import Viewer
+#import node180.scn6m_deep_09
+import symbolic.cmos
+from helpers import l, u, n
+
+
+Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile )
+
+
+Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
+
+Cfg.getParamBool ( 'misc.catchCore' ).setBool ( False )
+Cfg.getParamBool ( 'misc.info' ).setBool ( False )
+Cfg.getParamBool ( 'misc.paranoid' ).setBool ( False )
+Cfg.getParamBool ( 'misc.bug' ).setBool ( False )
+Cfg.getParamBool ( 'misc.logMode' ).setBool ( True )
+Cfg.getParamBool ( 'misc.verboseLevel1' ).setBool ( True )
+Cfg.getParamBool ( 'misc.verboseLevel2' ).setBool ( True )
+#Cfg.getParamInt ( 'misc.minTraceLevel' ).setInt ( 159 )
+#Cfg.getParamInt ( 'misc.maxTraceLevel' ).setInt ( 160 )
+Cfg.getParamEnumerate ( 'etesian.effort' ).setInt ( 2 )
+Cfg.getParamPercentage( 'etesian.spaceMargin' ).setPercentage( 20.0 )
+Cfg.getParamPercentage( 'etesian.aspectRatio' ).setPercentage( 100.0 )
+Cfg.getParamBool ( 'etesian.uniformDensity' ).setBool ( True )
+Cfg.getParamInt ( 'anabatic.edgeLenght' ).setInt ( 24 )
+Cfg.getParamInt ( 'anabatic.edgeWidth' ).setInt ( 8 )
+Cfg.getParamString ( 'anabatic.topRoutingLayer' ).setString ( 'METAL4')
+Cfg.getParamInt ( 'katana.eventsLimit' ).setInt ( 1000000 )
+Cfg.getParamInt ( 'katana.hTracksReservedLocal' ).setInt ( 7 )
+Cfg.getParamInt ( 'katana.vTracksReservedLocal' ).setInt ( 6 )
+#Cfg.getParamInt ( 'clockTree.minimumSide' ).setInt ( l(1000) )
+
+Cfg.Configuration.popDefaultPriority()
+
+#cellsTop = os.path.abspath( os.getcwd()+'/../cells' )
+if os.environ.has_key('CELLS_TOP'):
+ cellsTop = os.environ['CELLS_TOP']
+else:
+ cellsTop = '../../../cells'
+
+af = CRL.AllianceFramework.get()
+env = af.getEnvironment()
+env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
+env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend )
+#env.setCLOCK( '^clk$|m_clock' )
+env.setCLOCK( 'clk|ck|cki' )
+env.setPOWER( 'vdd' )
+env.setGROUND( 'vss' )
+
+Cfg.Configuration.popDefaultPriority()
+
+print 'Successfully read user configuration'
+
--- /dev/null
+from nmigen import Elaboratable, Cat, Module, Signal, Instance, Memory
+from nmigen.cli import rtlil
+
+
+class ADD(Elaboratable):
+ def __init__(self, width):
+ self.a = Signal(width)
+ self.b = Signal(width)
+ self.f = Signal(width)
+ self.mem = Memory(width=64, depth=64, init=range(64))
+
+ def elaborate(self, platform):
+ m = Module()
+ result = Signal.like(self.f)
+ m.d.sync += result.eq(self.a + self.b)
+
+ # 64k SRAM instance
+ a = Signal(16)
+ q = Signal(64) # output
+ d = Signal(64) # input
+ we = Signal(1)
+ # Memory
+ m.submodules.rdport = rdport = self.mem.read_port()
+ m.submodules.wrport = wrport = self.mem.write_port()
+ m.d.comb += [
+ rdport.addr.eq(a),
+ q.eq(rdport.data),
+ wrport.addr.eq(a),
+ wrport.data.eq(d),
+ wrport.en.eq(we),
+ ]
+
+ # connect up some arbitrary signals, to get the memory to be
+ # at least mostly instantiated.
+ m.d.comb += a.eq(Cat(self.a, self.b, self.a, self.b)) # 16-bit
+ m.d.comb += we.eq(self.a[0] ^ self.b[0])
+ # in/out is 4 bit, mem is 64. just... wrap/add
+ for i in range(0,64,4):
+ m.d.comb += d[i:i+4].eq(result)
+ for i in range(0,64,4):
+ result = result + q[i:i+4]
+ m.d.comb += self.f.eq(result)
+
+ return m
+
+
+def create_ilang(dut, ports, test_name):
+ vl = rtlil.convert(dut, name=test_name, ports=ports)
+ with open("%s.il" % test_name, "w") as f:
+ f.write(vl)
+
+if __name__ == "__main__":
+ alu = ADD(width=4)
+ create_ilang(alu, [alu.a, alu.b, alu.f], "memory")
--- /dev/null
+../mksym.sh
\ No newline at end of file
projects / soclayout.git / commitdiff