--- /dev/null
+
+ LOGICAL_SYNTHESIS = Yosys
+ PHYSICAL_SYNTHESIS = Coriolis
+# DESIGN_KIT = FlexLib018
+ DESIGN_KIT = cmos45
+ YOSYS_FLATTEN = No
+# YOSYS_SET_TOP = Yes
+ CHIP = chip
+ CORE = ls180
+ USE_CLOCKTREE = Yes
+ USE_DEBUG = No
+ RM_CHIP = Yes
+ VST_FLAGS = --vst-no-lowercase
+
+ #NETLISTS = $(shell cat netlists.lst)
+ NETLISTS = ls180
+# YOSYS_FLATTEN = $(shell cat flatten.lst)
+
+ include ./mk/design-flow.mk
+
+chip_r.vst: ls180.vst
+ -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
+
+chip_r.ap: chip_r.vst
+
+pinmux:
+ (cd coriolis2 && python ../../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
+ ln -f -s ../../../pinmux/src/parse.py coriolis2/pinparse.py
+ ln -f -s coriolis2/ls180 ls180
+
+# comment out for now
+blif: ls180.blif
+vst: ls180.vst
+
+lvx: lvx-chip_r
+druc: druc-chip_r
+dreal: dreal-chip_r
+flatph: flatph-chip_r
+view: cgt-chip_r
+
+layout: chip_r.ap
+gds: chip_r.gds
+gds_flat: chip_r_flat.gds
+cif: chip_r.cif
+
+
+view: cgt-chip_r
+sim: asimut-ls180_r
--- /dev/null
+(* blackbox = 1 *)
+module SPBlock_512W64B8W(input [8:0] a,
+ input [63:0] d,
+ output [63:0] q,
+ input [7:0] we,
+ input clk);
+endmodule // SPBlock_512W64B8W
--- /dev/null
+
+-- Phony VHDL interface for SRAM block.
+
+entity SPBlock_512W64B8W is
+ port ( clk : in bit
+ ; we : in bit_vector( 7 downto 0)
+ ; a : in bit_vector( 8 downto 0)
+ ; d : in bit_vector(63 downto 0)
+ ; q : out bit_vector(63 downto 0)
+ ; vdd : in bit
+ ; vss : in bit
+ );
+end SPBlock_512W64B8W;
+
+architecture behavioral of SPBlock_512W64B8W is
+
+begin
+
+end behavioral;
--- /dev/null
+#!/usr/bin/env python
+
+from helpers import l, u, n
+import os
+import json
+
+def _byteify(data, ignore_dicts = False):
+ # if this is a unicode string, return its string representation
+ if isinstance(data, unicode):
+ return data.encode('utf-8')
+ # if this is a list of values, return list of byteified values
+ if isinstance(data, list):
+ return [ _byteify(item, ignore_dicts=True) for item in data ]
+ # if this is a dictionary, return dictionary of byteified keys and values
+ # but only if we haven't already byteified it
+ if isinstance(data, dict) and not ignore_dicts:
+ return dict((_byteify(key, ignore_dicts=True),
+ _byteify(value, ignore_dicts=True))
+ for key, value in data.iteritems())
+ # if it's anything else, return it in its original form
+ return data
+
+# load JSON-formatted pad info from pinmux
+pth = os.path.abspath(__file__)
+pth = os.path.split(pth)[0]
+print "path", pth
+with open("%s/ls180/litex_pinpads.json" % pth) as f:
+ txt = f.read()
+chip = json.loads(txt, object_hook=_byteify)
+chip = _byteify(chip, ignore_dicts=True)
+print chip
+
+chip.update({ 'pads.ioPadGauge' : 'pxlib',
+ # core option (big, time-consuming)
+ #'core.size' : ( l(28000), l(28000) ),
+ #'chip.size' : ( l(30200), l(30200) ),
+ # no-core option (test_issuer but no actual core)
+ 'core.size' : ( l(13000), l(13000) ),
+ 'chip.size' : ( l(14400), l(14400) ),
+ 'pads.useCoreSize': True,
+ 'chip.clockTree' : True,
+ })
--- /dev/null
+from Hurricane import DebugSession
+
+#DebugSession.addToTrace( katana.getCell().getNet( 'cu_issue_i' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'cu_wr_rel_o(2)' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'xer_so_ok' ) )
+
--- /dev/null
+0 in
+1 in
+2 in
--- /dev/null
+e8 inout
+e9 inout
+e10 inout
+e11 inout
+e12 inout
+e13 inout
+e14 inout
+e15 inout
--- /dev/null
+s0 inout
+s1 inout
+s2 inout
+s3 inout
+s4 inout
+s5 inout
+s6 inout
+s7 inout
--- /dev/null
+gpios 1
+vss 2
+eint 1
+sdr 1
+mtwi 1
+uart 1
+mspi 2
+sys 1
+vdd 2
+gpioe 1
+pwm 1
+jtag 1
+sd 1
--- /dev/null
+tms in
+tdi in
+tdo out
+tck out
--- /dev/null
+{
+ "chip.clocks": {
+ "JTAG": "p_jtag_tck",
+ "MSPI": "p_spimaster_clk",
+ "MTWI": "p_i2c_scl",
+ "SD": "p_sdcard_clk",
+ "SDR": "p_sdram_clock"
+ },
+ "chip.domains": {
+ "EINT": [
+ "p_eint_0",
+ "p_eint_1",
+ "p_eint_2"
+ ],
+ "GPIO": [
+ "p_gpio_8",
+ "p_gpio_9",
+ "p_gpio_10",
+ "p_gpio_11",
+ "p_gpio_12",
+ "p_gpio_13",
+ "p_gpio_14",
+ "p_gpio_15",
+ "p_gpio_0",
+ "p_gpio_1",
+ "p_gpio_2",
+ "p_gpio_3",
+ "p_gpio_4",
+ "p_gpio_5",
+ "p_gpio_6",
+ "p_gpio_7"
+ ],
+ "JTAG": [
+ "p_jtag_tms",
+ "p_jtag_tdi",
+ "p_jtag_tdo",
+ "p_jtag_tck"
+ ],
+ "MSPI": [
+ "p_spisdcard_clk",
+ "p_spisdcard_cs_n",
+ "p_spisdcard_mosi",
+ "p_spisdcard_miso",
+ "p_spimaster_clk",
+ "p_spimaster_cs_n",
+ "p_spimaster_mosi",
+ "p_spimaster_miso"
+ ],
+ "MTWI": [
+ "p_i2c_sda",
+ "p_i2c_scl"
+ ],
+ "PWM": [
+ "p_pwm0",
+ "p_pwm1"
+ ],
+ "SD": [
+ "p_sdcard_cmd",
+ "p_sdcard_clk",
+ "p_sdcard_data0",
+ "p_sdcard_data1",
+ "p_sdcard_data2",
+ "p_sdcard_data3"
+ ],
+ "SDR": [
+ "p_sdram_dm_0",
+ "p_sdram_dq_0",
+ "p_sdram_dq_1",
+ "p_sdram_dq_2",
+ "p_sdram_dq_3",
+ "p_sdram_dq_4",
+ "p_sdram_dq_5",
+ "p_sdram_dq_6",
+ "p_sdram_dq_7",
+ "p_sdram_a_0",
+ "p_sdram_a_1",
+ "p_sdram_a_2",
+ "p_sdram_a_3",
+ "p_sdram_a_4",
+ "p_sdram_a_5",
+ "p_sdram_a_6",
+ "p_sdram_a_7",
+ "p_sdram_a_8",
+ "p_sdram_a_9",
+ "p_sdram_ba_0",
+ "p_sdram_ba_1",
+ "p_sdram_clock",
+ "p_sdram_cke",
+ "p_sdram_ras_n",
+ "p_sdram_cas_n",
+ "p_sdram_we_n",
+ "p_sdram_cs_n",
+ "p_sdram_a_10",
+ "p_sdram_a_11",
+ "p_sdram_a_12",
+ "p_sdram_dm_1",
+ "p_sdram_dq_8",
+ "p_sdram_dq_9",
+ "p_sdram_dq_10",
+ "p_sdram_dq_11",
+ "p_sdram_dq_12",
+ "p_sdram_dq_13",
+ "p_sdram_dq_14",
+ "p_sdram_dq_15"
+ ],
+ "UART": [
+ "p_uart_tx",
+ "p_uart_rx"
+ ]
+ },
+ "chip.n_extpower": 3,
+ "chip.n_intpower": 5,
+ "pads.east": [
+ "p_sdram_a_10",
+ "iopower_1",
+ "ioground_1",
+ "p_sdram_a_11",
+ "p_sdram_a_12",
+ "p_sdram_dm_1",
+ "p_sdram_dq_8",
+ "p_sdram_dq_9",
+ "p_sdram_dq_10",
+ "p_sdram_dq_11",
+ "p_sdram_dq_12",
+ "p_sdram_dq_13",
+ "p_sdram_dq_14",
+ "p_sdram_dq_15",
+ "power_1",
+ "ground_1",
+ "p_gpio_8",
+ "p_gpio_9",
+ "p_gpio_10",
+ "p_gpio_11",
+ "p_gpio_12",
+ "p_gpio_13",
+ "p_gpio_14",
+ "p_gpio_15",
+ "nc_0",
+ "p_jtag_tms",
+ "p_jtag_tdi",
+ "p_jtag_tdo",
+ "p_jtag_tck",
+ "nc_1",
+ "nc_2",
+ "nc_3"
+ ],
+ "pads.instances": [
+ [
+ "iopower_0",
+ "iovdd"
+ ],
+ [
+ "ioground_0",
+ "iovss"
+ ],
+ [
+ "p_sdram_dm_0",
+ "sdram_dm(0)",
+ "sdram_dm(0)",
+ "+"
+ ],
+ [
+ "p_sdram_dq_0",
+ "sdram_dq_0",
+ "sdram_dq_o(0)",
+ "sdram_dq_i(0)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_1",
+ "sdram_dq_1",
+ "sdram_dq_o(1)",
+ "sdram_dq_i(1)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_2",
+ "sdram_dq_2",
+ "sdram_dq_o(2)",
+ "sdram_dq_i(2)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_3",
+ "sdram_dq_3",
+ "sdram_dq_o(3)",
+ "sdram_dq_i(3)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_4",
+ "sdram_dq_4",
+ "sdram_dq_o(4)",
+ "sdram_dq_i(4)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_5",
+ "sdram_dq_5",
+ "sdram_dq_o(5)",
+ "sdram_dq_i(5)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_6",
+ "sdram_dq_6",
+ "sdram_dq_o(6)",
+ "sdram_dq_i(6)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_7",
+ "sdram_dq_7",
+ "sdram_dq_o(7)",
+ "sdram_dq_i(7)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_a_0",
+ "sdram_a(0)",
+ "sdram_a(0)",
+ "+"
+ ],
+ [
+ "p_sdram_a_1",
+ "sdram_a(1)",
+ "sdram_a(1)",
+ "+"
+ ],
+ [
+ "p_sdram_a_2",
+ "sdram_a(2)",
+ "sdram_a(2)",
+ "+"
+ ],
+ [
+ "p_sdram_a_3",
+ "sdram_a(3)",
+ "sdram_a(3)",
+ "+"
+ ],
+ [
+ "p_sdram_a_4",
+ "sdram_a(4)",
+ "sdram_a(4)",
+ "+"
+ ],
+ [
+ "p_sdram_a_5",
+ "sdram_a(5)",
+ "sdram_a(5)",
+ "+"
+ ],
+ [
+ "p_sdram_a_6",
+ "sdram_a(6)",
+ "sdram_a(6)",
+ "+"
+ ],
+ [
+ "p_sdram_a_7",
+ "sdram_a(7)",
+ "sdram_a(7)",
+ "+"
+ ],
+ [
+ "p_sdram_a_8",
+ "sdram_a(8)",
+ "sdram_a(8)",
+ "+"
+ ],
+ [
+ "p_sdram_a_9",
+ "sdram_a(9)",
+ "sdram_a(9)",
+ "+"
+ ],
+ [
+ "p_sdram_ba_0",
+ "sdram_ba(0)",
+ "sdram_ba(0)",
+ "+"
+ ],
+ [
+ "p_sdram_ba_1",
+ "sdram_ba(1)",
+ "sdram_ba(1)",
+ "+"
+ ],
+ [
+ "p_sdram_clock",
+ "sdram_clock",
+ "sdram_clock",
+ "+"
+ ],
+ [
+ "p_sdram_cke",
+ "sdram_cke",
+ "sdram_cke",
+ "+"
+ ],
+ [
+ "p_sdram_ras_n",
+ "sdram_ras_n",
+ "sdram_ras_n",
+ "+"
+ ],
+ [
+ "p_sdram_cas_n",
+ "sdram_cas_n",
+ "sdram_cas_n",
+ "+"
+ ],
+ [
+ "p_sdram_we_n",
+ "sdram_we_n",
+ "sdram_we_n",
+ "+"
+ ],
+ [
+ "p_sdram_cs_n",
+ "sdram_cs_n",
+ "sdram_cs_n",
+ "+"
+ ],
+ [
+ "power_0",
+ "vdd"
+ ],
+ [
+ "ground_0",
+ "vss"
+ ],
+ [
+ "iopower_1",
+ "iovdd"
+ ],
+ [
+ "ioground_1",
+ "iovdd"
+ ],
+ [
+ "p_sdram_a_10",
+ "sdram_a(10)",
+ "sdram_a(10)",
+ "+"
+ ],
+ [
+ "p_sdram_a_11",
+ "sdram_a(11)",
+ "sdram_a(11)",
+ "+"
+ ],
+ [
+ "p_sdram_a_12",
+ "sdram_a(12)",
+ "sdram_a(12)",
+ "+"
+ ],
+ [
+ "p_sdram_dm_1",
+ "sdram_dm(1)",
+ "sdram_dm(1)",
+ "*"
+ ],
+ [
+ "p_sdram_dq_8",
+ "sdram_dq_8",
+ "sdram_dq_o(8)",
+ "sdram_dq_i(8)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_9",
+ "sdram_dq_9",
+ "sdram_dq_o(9)",
+ "sdram_dq_i(9)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_10",
+ "sdram_dq_10",
+ "sdram_dq_o(10)",
+ "sdram_dq_i(10)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_11",
+ "sdram_dq_11",
+ "sdram_dq_o(11)",
+ "sdram_dq_i(11)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_12",
+ "sdram_dq_12",
+ "sdram_dq_o(12)",
+ "sdram_dq_i(12)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_13",
+ "sdram_dq_13",
+ "sdram_dq_o(13)",
+ "sdram_dq_i(13)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_14",
+ "sdram_dq_14",
+ "sdram_dq_o(14)",
+ "sdram_dq_i(14)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "p_sdram_dq_15",
+ "sdram_dq_15",
+ "sdram_dq_o(15)",
+ "sdram_dq_i(15)",
+ "sdram_dq_oe",
+ "*"
+ ],
+ [
+ "power_1",
+ "vdd"
+ ],
+ [
+ "ground_1",
+ "vss"
+ ],
+ [
+ "p_gpio_8",
+ "gpio_8",
+ "gpio_o(8)",
+ "gpio_i(8)",
+ "gpio_oe(8)",
+ "*"
+ ],
+ [
+ "p_gpio_9",
+ "gpio_9",
+ "gpio_o(9)",
+ "gpio_i(9)",
+ "gpio_oe(9)",
+ "*"
+ ],
+ [
+ "p_gpio_10",
+ "gpio_10",
+ "gpio_o(10)",
+ "gpio_i(10)",
+ "gpio_oe(10)",
+ "*"
+ ],
+ [
+ "p_gpio_11",
+ "gpio_11",
+ "gpio_o(11)",
+ "gpio_i(11)",
+ "gpio_oe(11)",
+ "*"
+ ],
+ [
+ "p_gpio_12",
+ "gpio_12",
+ "gpio_o(12)",
+ "gpio_i(12)",
+ "gpio_oe(12)",
+ "*"
+ ],
+ [
+ "p_gpio_13",
+ "gpio_13",
+ "gpio_o(13)",
+ "gpio_i(13)",
+ "gpio_oe(13)",
+ "*"
+ ],
+ [
+ "p_gpio_14",
+ "gpio_14",
+ "gpio_o(14)",
+ "gpio_i(14)",
+ "gpio_oe(14)",
+ "*"
+ ],
+ [
+ "p_gpio_15",
+ "gpio_15",
+ "gpio_o(15)",
+ "gpio_i(15)",
+ "gpio_oe(15)",
+ "*"
+ ],
+ [
+ "p_jtag_tms",
+ "jtag_tms",
+ "jtag_tms",
+ "-"
+ ],
+ [
+ "p_jtag_tdi",
+ "jtag_tdi",
+ "jtag_tdi",
+ "-"
+ ],
+ [
+ "p_jtag_tdo",
+ "jtag_tdo",
+ "jtag_tdo",
+ "+"
+ ],
+ [
+ "p_jtag_tck",
+ "jtag_tck",
+ "jtag_tck",
+ "+"
+ ],
+ [
+ "power_2",
+ "vdd"
+ ],
+ [
+ "ground_2",
+ "vss"
+ ],
+ [
+ "p_i2c_sda",
+ "i2c_sda",
+ "i2c_sda_o",
+ "i2c_sda_i",
+ "i2c_sda_oe",
+ "*"
+ ],
+ [
+ "p_i2c_scl",
+ "i2c_scl",
+ "i2c_scl",
+ "+"
+ ],
+ [
+ "p_spisdcard_clk",
+ "spisdcard_clk",
+ "spisdcard_clk",
+ "+"
+ ],
+ [
+ "p_spisdcard_cs_n",
+ "spisdcard_cs_n",
+ "spisdcard_cs_n",
+ "+"
+ ],
+ [
+ "p_spisdcard_mosi",
+ "spisdcard_mosi",
+ "spisdcard_mosi",
+ "+"
+ ],
+ [
+ "p_spisdcard_miso",
+ "spisdcard_miso",
+ "spisdcard_miso",
+ "-"
+ ],
+ [
+ "p_uart_tx",
+ "uart_tx",
+ "uart_tx",
+ "+"
+ ],
+ [
+ "p_uart_rx",
+ "uart_rx",
+ "uart_rx",
+ "-"
+ ],
+ [
+ "p_gpio_0",
+ "gpio_0",
+ "gpio_o(0)",
+ "gpio_i(0)",
+ "gpio_oe(0)",
+ "*"
+ ],
+ [
+ "p_gpio_1",
+ "gpio_1",
+ "gpio_o(1)",
+ "gpio_i(1)",
+ "gpio_oe(1)",
+ "*"
+ ],
+ [
+ "p_gpio_2",
+ "gpio_2",
+ "gpio_o(2)",
+ "gpio_i(2)",
+ "gpio_oe(2)",
+ "*"
+ ],
+ [
+ "p_gpio_3",
+ "gpio_3",
+ "gpio_o(3)",
+ "gpio_i(3)",
+ "gpio_oe(3)",
+ "*"
+ ],
+ [
+ "p_gpio_4",
+ "gpio_4",
+ "gpio_o(4)",
+ "gpio_i(4)",
+ "gpio_oe(4)",
+ "*"
+ ],
+ [
+ "p_gpio_5",
+ "gpio_5",
+ "gpio_o(5)",
+ "gpio_i(5)",
+ "gpio_oe(5)",
+ "*"
+ ],
+ [
+ "p_gpio_6",
+ "gpio_6",
+ "gpio_o(6)",
+ "gpio_i(6)",
+ "gpio_oe(6)",
+ "*"
+ ],
+ [
+ "p_gpio_7",
+ "gpio_7",
+ "gpio_o(7)",
+ "gpio_i(7)",
+ "gpio_oe(7)",
+ "*"
+ ],
+ [
+ "p_sys_clk",
+ "sys_clk",
+ "sys_clk",
+ "-"
+ ],
+ [
+ "sys_rst",
+ "sys_rst",
+ "sys_rst",
+ "-"
+ ],
+ [
+ "p_sys_pll_18_o",
+ "sys_pll_18_o",
+ "sys_pll_18_o",
+ "+"
+ ],
+ [
+ "p_sys_clksel_0",
+ "sys_clksel_i(0)",
+ "sys_clksel_i(0)",
+ "-"
+ ],
+ [
+ "p_sys_clksel_1",
+ "sys_clksel_i(1)",
+ "sys_clksel_i(1)",
+ "-"
+ ],
+ [
+ "p_sys_pll_lck_o",
+ "sys_pll_lck_o",
+ "sys_pll_lck_o",
+ "+"
+ ],
+ [
+ "power_3",
+ "vdd"
+ ],
+ [
+ "ground_3",
+ "vss"
+ ],
+ [
+ "iopower_2",
+ "iovdd"
+ ],
+ [
+ "ioground_2",
+ "iovss"
+ ],
+ [
+ "p_pwm0",
+ "pwm(0)",
+ "pwm(0)",
+ "+"
+ ],
+ [
+ "p_pwm1",
+ "pwm(1)",
+ "pwm(1)",
+ "+"
+ ],
+ [
+ "p_eint_0",
+ "eint(0)",
+ "eint(0)",
+ "-"
+ ],
+ [
+ "p_eint_1",
+ "eint(1)",
+ "eint(1)",
+ "-"
+ ],
+ [
+ "p_eint_2",
+ "eint(2)",
+ "eint(2)",
+ "-"
+ ],
+ [
+ "p_spimaster_clk",
+ "spimaster_clk",
+ "spimaster_clk",
+ "+"
+ ],
+ [
+ "p_spimaster_cs_n",
+ "spimaster_cs_n",
+ "spimaster_cs_n",
+ "+"
+ ],
+ [
+ "p_spimaster_mosi",
+ "spimaster_mosi",
+ "spimaster_mosi",
+ "+"
+ ],
+ [
+ "p_spimaster_miso",
+ "spimaster_miso",
+ "spimaster_miso",
+ "-"
+ ],
+ [
+ "p_sdcard_cmd",
+ "sdcard_cmd",
+ "sdcard_cmd_o",
+ "sdcard_cmd_i",
+ "sdcard_cmd_oe",
+ "*"
+ ],
+ [
+ "p_sdcard_clk",
+ "sdcard_clk",
+ "sdcard_clk",
+ "+"
+ ],
+ [
+ "p_sdcard_data0",
+ "sdcard_data0",
+ "sdcard_data_o(0)",
+ "sdcard_data_i(0)",
+ "sdcard_data_oe",
+ "*"
+ ],
+ [
+ "p_sdcard_data1",
+ "sdcard_data1",
+ "sdcard_data_o(1)",
+ "sdcard_data_i(1)",
+ "sdcard_data_oe",
+ "*"
+ ],
+ [
+ "p_sdcard_data2",
+ "sdcard_data2",
+ "sdcard_data_o(2)",
+ "sdcard_data_i(2)",
+ "sdcard_data_oe",
+ "*"
+ ],
+ [
+ "p_sdcard_data3",
+ "sdcard_data3",
+ "sdcard_data_o(3)",
+ "sdcard_data_i(3)",
+ "sdcard_data_oe",
+ "*"
+ ],
+ [
+ "power_4",
+ "vdd"
+ ],
+ [
+ "ground_4",
+ "vss"
+ ],
+ [
+ "nc_0",
+ "nc(0)",
+ "nc(0)",
+ "-"
+ ],
+ [
+ "nc_1",
+ "nc(1)",
+ "nc(1)",
+ "-"
+ ],
+ [
+ "nc_2",
+ "nc(2)",
+ "nc(2)",
+ "-"
+ ],
+ [
+ "nc_3",
+ "nc(3)",
+ "nc(3)",
+ "-"
+ ],
+ [
+ "nc_4",
+ "nc(4)",
+ "nc(4)",
+ "-"
+ ],
+ [
+ "nc_5",
+ "nc(5)",
+ "nc(5)",
+ "-"
+ ],
+ [
+ "nc_6",
+ "nc(6)",
+ "nc(6)",
+ "-"
+ ],
+ [
+ "nc_7",
+ "nc(7)",
+ "nc(7)",
+ "-"
+ ],
+ [
+ "nc_8",
+ "nc(8)",
+ "nc(8)",
+ "-"
+ ],
+ [
+ "nc_9",
+ "nc(9)",
+ "nc(9)",
+ "-"
+ ],
+ [
+ "nc_10",
+ "nc(10)",
+ "nc(10)",
+ "-"
+ ],
+ [
+ "nc_11",
+ "nc(11)",
+ "nc(11)",
+ "-"
+ ],
+ [
+ "nc_12",
+ "nc(12)",
+ "nc(12)",
+ "-"
+ ],
+ [
+ "nc_13",
+ "nc(13)",
+ "nc(13)",
+ "-"
+ ],
+ [
+ "nc_14",
+ "nc(14)",
+ "nc(14)",
+ "-"
+ ],
+ [
+ "nc_15",
+ "nc(15)",
+ "nc(15)",
+ "-"
+ ],
+ [
+ "nc_16",
+ "nc(16)",
+ "nc(16)",
+ "-"
+ ],
+ [
+ "nc_17",
+ "nc(17)",
+ "nc(17)",
+ "-"
+ ],
+ [
+ "nc_18",
+ "nc(18)",
+ "nc(18)",
+ "-"
+ ],
+ [
+ "nc_19",
+ "nc(19)",
+ "nc(19)",
+ "-"
+ ],
+ [
+ "nc_20",
+ "nc(20)",
+ "nc(20)",
+ "-"
+ ],
+ [
+ "nc_21",
+ "nc(21)",
+ "nc(21)",
+ "-"
+ ],
+ [
+ "nc_22",
+ "nc(22)",
+ "nc(22)",
+ "-"
+ ],
+ [
+ "nc_23",
+ "nc(23)",
+ "nc(23)",
+ "-"
+ ]
+ ],
+ "pads.north": [
+ "p_sdram_dm_0",
+ "iopower_0",
+ "ioground_0",
+ "p_sdram_dq_0",
+ "p_sdram_dq_1",
+ "p_sdram_dq_2",
+ "p_sdram_dq_3",
+ "p_sdram_dq_4",
+ "p_sdram_dq_5",
+ "p_sdram_dq_6",
+ "p_sdram_dq_7",
+ "p_sdram_a_0",
+ "p_sdram_a_1",
+ "p_sdram_a_2",
+ "p_sdram_a_3",
+ "p_sdram_a_4",
+ "p_sdram_a_5",
+ "p_sdram_a_6",
+ "p_sdram_a_7",
+ "p_sdram_a_8",
+ "p_sdram_a_9",
+ "p_sdram_ba_0",
+ "p_sdram_ba_1",
+ "p_sdram_clock",
+ "p_sdram_cke",
+ "p_sdram_ras_n",
+ "p_sdram_cas_n",
+ "p_sdram_we_n",
+ "p_sdram_cs_n",
+ "power_0",
+ "ground_0",
+ "nc_17"
+ ],
+ "pads.south": [
+ "p_i2c_sda",
+ "power_2",
+ "ground_2",
+ "p_i2c_scl",
+ "nc_18",
+ "nc_19",
+ "nc_20",
+ "nc_21",
+ "p_spisdcard_clk",
+ "p_spisdcard_cs_n",
+ "p_spisdcard_mosi",
+ "p_spisdcard_miso",
+ "nc_22",
+ "p_uart_tx",
+ "p_uart_rx",
+ "p_gpio_0",
+ "p_gpio_1",
+ "p_gpio_2",
+ "p_gpio_3",
+ "p_gpio_4",
+ "p_gpio_5",
+ "p_gpio_6",
+ "p_gpio_7",
+ "p_sys_clk",
+ "sys_rst",
+ "nc_23",
+ "p_sys_pll_18_o",
+ "p_sys_clksel_0",
+ "p_sys_clksel_1",
+ "power_3",
+ "ground_3",
+ "p_sys_pll_lck_o"
+ ],
+ "pads.west": [
+ "p_pwm0",
+ "iopower_2",
+ "ioground_2",
+ "p_pwm1",
+ "p_eint_0",
+ "p_eint_1",
+ "p_eint_2",
+ "p_spimaster_clk",
+ "p_spimaster_cs_n",
+ "p_spimaster_mosi",
+ "p_spimaster_miso",
+ "p_sdcard_cmd",
+ "p_sdcard_clk",
+ "p_sdcard_data0",
+ "p_sdcard_data1",
+ "p_sdcard_data2",
+ "p_sdcard_data3",
+ "nc_4",
+ "nc_5",
+ "nc_6",
+ "nc_7",
+ "nc_8",
+ "nc_9",
+ "nc_10",
+ "nc_11",
+ "nc_12",
+ "nc_13",
+ "nc_14",
+ "nc_15",
+ "power_4",
+ "ground_4",
+ "nc_16"
+ ],
+ "pins.map": {
+ "eint_0": "p_eint_0",
+ "eint_1": "p_eint_1",
+ "eint_2": "p_eint_2",
+ "gpioe_e10": "p_gpio_10",
+ "gpioe_e11": "p_gpio_11",
+ "gpioe_e12": "p_gpio_12",
+ "gpioe_e13": "p_gpio_13",
+ "gpioe_e14": "p_gpio_14",
+ "gpioe_e15": "p_gpio_15",
+ "gpioe_e8": "p_gpio_8",
+ "gpioe_e9": "p_gpio_9",
+ "gpios_s0": "p_gpio_0",
+ "gpios_s1": "p_gpio_1",
+ "gpios_s2": "p_gpio_2",
+ "gpios_s3": "p_gpio_3",
+ "gpios_s4": "p_gpio_4",
+ "gpios_s5": "p_gpio_5",
+ "gpios_s6": "p_gpio_6",
+ "gpios_s7": "p_gpio_7",
+ "jtag_tck": "p_jtag_tck",
+ "jtag_tdi": "p_jtag_tdi",
+ "jtag_tdo": "p_jtag_tdo",
+ "jtag_tms": "p_jtag_tms",
+ "mspi0_ck": "p_spisdcard_clk",
+ "mspi0_miso": "p_spisdcard_miso",
+ "mspi0_mosi": "p_spisdcard_mosi",
+ "mspi0_nss": "p_spisdcard_cs_n",
+ "mspi1_ck": "p_spimaster_clk",
+ "mspi1_miso": "p_spimaster_miso",
+ "mspi1_mosi": "p_spimaster_mosi",
+ "mspi1_nss": "p_spimaster_cs_n",
+ "mtwi_scl": "p_i2c_scl",
+ "mtwi_sda": "p_i2c_sda",
+ "nc_0": "nc_0",
+ "nc_1": "nc_1",
+ "nc_10": "nc_10",
+ "nc_11": "nc_11",
+ "nc_12": "nc_12",
+ "nc_13": "nc_13",
+ "nc_14": "nc_14",
+ "nc_15": "nc_15",
+ "nc_16": "nc_16",
+ "nc_17": "nc_17",
+ "nc_18": "nc_18",
+ "nc_19": "nc_19",
+ "nc_2": "nc_2",
+ "nc_20": "nc_20",
+ "nc_21": "nc_21",
+ "nc_22": "nc_22",
+ "nc_23": "nc_23",
+ "nc_3": "nc_3",
+ "nc_4": "nc_4",
+ "nc_5": "nc_5",
+ "nc_6": "nc_6",
+ "nc_7": "nc_7",
+ "nc_8": "nc_8",
+ "nc_9": "nc_9",
+ "pwm0_out": "p_pwm0",
+ "pwm1_out": "p_pwm1",
+ "sd0_clk": "p_sdcard_clk",
+ "sd0_cmd": "p_sdcard_cmd",
+ "sd0_d0": "p_sdcard_data0",
+ "sd0_d1": "p_sdcard_data1",
+ "sd0_d2": "p_sdcard_data2",
+ "sd0_d3": "p_sdcard_data3",
+ "sdr_ad0": "p_sdram_a_0",
+ "sdr_ad1": "p_sdram_a_1",
+ "sdr_ad10": "p_sdram_a_10",
+ "sdr_ad11": "p_sdram_a_11",
+ "sdr_ad12": "p_sdram_a_12",
+ "sdr_ad2": "p_sdram_a_2",
+ "sdr_ad3": "p_sdram_a_3",
+ "sdr_ad4": "p_sdram_a_4",
+ "sdr_ad5": "p_sdram_a_5",
+ "sdr_ad6": "p_sdram_a_6",
+ "sdr_ad7": "p_sdram_a_7",
+ "sdr_ad8": "p_sdram_a_8",
+ "sdr_ad9": "p_sdram_a_9",
+ "sdr_ba0": "p_sdram_ba_0",
+ "sdr_ba1": "p_sdram_ba_1",
+ "sdr_casn": "p_sdram_cas_n",
+ "sdr_cke": "p_sdram_cke",
+ "sdr_clk": "p_sdram_clock",
+ "sdr_csn0": "p_sdram_cs_n",
+ "sdr_d0": "p_sdram_dq_0",
+ "sdr_d1": "p_sdram_dq_1",
+ "sdr_d10": "p_sdram_dq_10",
+ "sdr_d11": "p_sdram_dq_11",
+ "sdr_d12": "p_sdram_dq_12",
+ "sdr_d13": "p_sdram_dq_13",
+ "sdr_d14": "p_sdram_dq_14",
+ "sdr_d15": "p_sdram_dq_15",
+ "sdr_d2": "p_sdram_dq_2",
+ "sdr_d3": "p_sdram_dq_3",
+ "sdr_d4": "p_sdram_dq_4",
+ "sdr_d5": "p_sdram_dq_5",
+ "sdr_d6": "p_sdram_dq_6",
+ "sdr_d7": "p_sdram_dq_7",
+ "sdr_d8": "p_sdram_dq_8",
+ "sdr_d9": "p_sdram_dq_9",
+ "sdr_dqm0": "p_sdram_dm_0",
+ "sdr_dqm1": "p_sdram_dm_1",
+ "sdr_rasn": "p_sdram_ras_n",
+ "sdr_wen": "p_sdram_we_n",
+ "sys_clk": "p_sys_clk",
+ "sys_csel0": "p_sys_clksel_0",
+ "sys_csel1": "p_sys_clksel_1",
+ "sys_pllock": "p_sys_pll_lck_o",
+ "sys_pllout": "p_sys_pll_18_o",
+ "uart0_rx": "p_uart_rx",
+ "uart0_tx": "p_uart_tx",
+ "vdde_0": "ioground_0",
+ "vdde_1": "ioground_1",
+ "vdde_2": "ioground_2",
+ "vddi_0": "ground_0",
+ "vddi_1": "ground_1",
+ "vddi_2": "ground_2",
+ "vddi_3": "ground_3",
+ "vddi_4": "ground_4",
+ "vsse_0": "iopower_0",
+ "vsse_1": "iopower_1",
+ "vsse_2": "iopower_2",
+ "vssi_0": "power_0",
+ "vssi_1": "power_1",
+ "vssi_2": "power_2",
+ "vssi_3": "power_3",
+ "vssi_4": "power_4"
+ },
+ "pins.specs": {
+ "EINT:": [
+ "0-",
+ "1-",
+ "2-"
+ ],
+ "GPIO:": [
+ "E8*",
+ "E9*",
+ "E10*",
+ "E11*",
+ "E12*",
+ "E13*",
+ "E14*",
+ "E15*",
+ "S0*",
+ "S1*",
+ "S2*",
+ "S3*",
+ "S4*",
+ "S5*",
+ "S6*",
+ "S7*"
+ ],
+ "JTAG:": [
+ "TMS-",
+ "TDI-",
+ "TDO+",
+ "TCK+"
+ ],
+ "MSPI:0": [
+ "CK+",
+ "NSS+",
+ "MOSI+",
+ "MISO-"
+ ],
+ "MSPI:1": [
+ "CK+",
+ "NSS+",
+ "MOSI+",
+ "MISO-"
+ ],
+ "MTWI:": [
+ "SDA*",
+ "SCL+"
+ ],
+ "PWM:": [
+ "0+",
+ "1+"
+ ],
+ "SD:0": [
+ "CMD*",
+ "CLK+",
+ "D0*",
+ "D1*",
+ "D2*",
+ "D3*"
+ ],
+ "SDR:": [
+ "DQM0+",
+ "D0*",
+ "D1*",
+ "D2*",
+ "D3*",
+ "D4*",
+ "D5*",
+ "D6*",
+ "D7*",
+ "AD0+",
+ "AD1+",
+ "AD2+",
+ "AD3+",
+ "AD4+",
+ "AD5+",
+ "AD6+",
+ "AD7+",
+ "AD8+",
+ "AD9+",
+ "BA0+",
+ "BA1+",
+ "CLK+",
+ "CKE+",
+ "RASn+",
+ "CASn+",
+ "WEn+",
+ "CSn0+",
+ "AD10+",
+ "AD11+",
+ "AD12+",
+ "DQM1*",
+ "D8*",
+ "D9*",
+ "D10*",
+ "D11*",
+ "D12*",
+ "D13*",
+ "D14*",
+ "D15*"
+ ],
+ "SYS:": [
+ "CLK-",
+ "RST-",
+ "PLLCLK-",
+ "PLLOUT+",
+ "CSEL0-",
+ "CSEL1-",
+ "PLLOCK+"
+ ],
+ "UART:0": [
+ "TX+",
+ "RX-"
+ ],
+ "VDD:E": [
+ "0-",
+ "1-",
+ "2-"
+ ],
+ "VDD:I": [
+ "0-",
+ "1-",
+ "2-",
+ "3-",
+ "4-"
+ ],
+ "VSS:E": [
+ "0-",
+ "1-",
+ "2-"
+ ],
+ "VSS:I": [
+ "0-",
+ "1-",
+ "2-",
+ "3-",
+ "4-"
+ ]
+ }
+}
--- /dev/null
+coriolis2/ls180
\ No newline at end of file
--- /dev/null
+# Pinouts (PinMux)
+auto-generated by [[pinouts.py]]
+
+[[!toc ]]
+
+
+## Bank N (32 pins, width 2)
+
+| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
+| --- | ----------- | ----------- | ----------- | ----------- |
+| 0 | N VSSE_0 | |
+| 1 | N VDDE_0 | |
+| 2 | N SDR_DQM0 | |
+| 3 | N SDR_D0 | |
+| 4 | N SDR_D1 | |
+| 5 | N SDR_D2 | |
+| 6 | N SDR_D3 | |
+| 7 | N SDR_D4 | |
+| 8 | N SDR_D5 | |
+| 9 | N SDR_D6 | |
+| 10 | N SDR_D7 | |
+| 11 | N SDR_AD0 | |
+| 12 | N SDR_AD1 | |
+| 13 | N SDR_AD2 | |
+| 14 | N SDR_AD3 | |
+| 15 | N SDR_AD4 | |
+| 16 | N SDR_AD5 | |
+| 17 | N SDR_AD6 | |
+| 18 | N SDR_AD7 | |
+| 19 | N SDR_AD8 | |
+| 20 | N SDR_AD9 | |
+| 21 | N SDR_BA0 | |
+| 22 | N SDR_BA1 | |
+| 23 | N SDR_CLK | |
+| 24 | N SDR_CKE | |
+| 25 | N SDR_RASn | |
+| 26 | N SDR_CASn | |
+| 27 | N SDR_WEn | |
+| 28 | N SDR_CSn0 | |
+| 30 | N VSSI_0 | |
+| 31 | N VDDI_0 | |
+
+## Bank E (32 pins, width 2)
+
+| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
+| --- | ----------- | ----------- | ----------- | ----------- |
+| 32 | E VSSE_1 | |
+| 33 | E VDDE_1 | |
+| 34 | E SDR_AD10 | |
+| 35 | E SDR_AD11 | |
+| 36 | E SDR_AD12 | |
+| 37 | E SDR_DQM1 | |
+| 38 | E SDR_D8 | |
+| 39 | E SDR_D9 | |
+| 40 | E SDR_D10 | |
+| 41 | E SDR_D11 | |
+| 42 | E SDR_D12 | |
+| 43 | E SDR_D13 | |
+| 44 | E SDR_D14 | |
+| 45 | E SDR_D15 | |
+| 46 | E VSSI_1 | |
+| 47 | E VDDI_1 | |
+| 48 | E GPIOE_E8 | |
+| 49 | E GPIOE_E9 | |
+| 50 | E GPIOE_E10 | |
+| 51 | E GPIOE_E11 | |
+| 52 | E GPIOE_E12 | |
+| 53 | E GPIOE_E13 | |
+| 54 | E GPIOE_E14 | |
+| 55 | E GPIOE_E15 | |
+| 57 | E JTAG_TMS | |
+| 58 | E JTAG_TDI | |
+| 59 | E JTAG_TDO | |
+| 60 | E JTAG_TCK | |
+
+## Bank S (32 pins, width 2)
+
+| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
+| --- | ----------- | ----------- | ----------- | ----------- |
+| 64 | S VSSI_2 | |
+| 65 | S VDDI_2 | |
+| 66 | S MTWI_SDA | |
+| 67 | S MTWI_SCL | |
+| 72 | S MSPI0_CK | |
+| 73 | S MSPI0_NSS | |
+| 74 | S MSPI0_MOSI | |
+| 75 | S MSPI0_MISO | |
+| 77 | S UART0_TX | |
+| 78 | S UART0_RX | |
+| 79 | S GPIOS_S0 | |
+| 80 | S GPIOS_S1 | |
+| 81 | S GPIOS_S2 | |
+| 82 | S GPIOS_S3 | |
+| 83 | S GPIOS_S4 | |
+| 84 | S GPIOS_S5 | |
+| 85 | S GPIOS_S6 | |
+| 86 | S GPIOS_S7 | |
+| 87 | S SYS_CLK | |
+| 88 | S SYS_RST | |
+| 89 | S SYS_PLLCLK | |
+| 90 | S SYS_PLLOUT | |
+| 91 | S SYS_CSEL0 | |
+| 92 | S SYS_CSEL1 | |
+| 93 | S SYS_PLLOCK | |
+| 94 | S VSSI_3 | |
+| 95 | S VDDI_3 | |
+
+## Bank W (32 pins, width 2)
+
+| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
+| --- | ----------- | ----------- | ----------- | ----------- |
+| 96 | W VSSE_2 | |
+| 97 | W VDDE_2 | |
+| 98 | W PWM_0 | |
+| 99 | W PWM_1 | |
+| 100 | W EINT_0 | |
+| 101 | W EINT_1 | |
+| 102 | W EINT_2 | |
+| 103 | W MSPI1_CK | |
+| 104 | W MSPI1_NSS | |
+| 105 | W MSPI1_MOSI | |
+| 106 | W MSPI1_MISO | |
+| 107 | W SD0_CMD | |
+| 108 | W SD0_CLK | |
+| 109 | W SD0_D0 | |
+| 110 | W SD0_D1 | |
+| 111 | W SD0_D2 | |
+| 112 | W SD0_D3 | |
+| 126 | W VSSI_4 | |
+| 127 | W VDDI_4 | |
+
+# Pinouts (Fixed function)
+
+# Functions (PinMux)
+
+auto-generated by [[pinouts.py]]
+
+## EINT
+
+External Interrupt
+
+* EINT_0 : W4/0
+* EINT_1 : W5/0
+* EINT_2 : W6/0
+
+## GPIO
+
+GPIO
+
+* GPIOE_E10 : E18/0
+* GPIOE_E11 : E19/0
+* GPIOE_E12 : E20/0
+* GPIOE_E13 : E21/0
+* GPIOE_E14 : E22/0
+* GPIOE_E15 : E23/0
+* GPIOE_E8 : E16/0
+* GPIOE_E9 : E17/0
+* GPIOS_S0 : S15/0
+* GPIOS_S1 : S16/0
+* GPIOS_S2 : S17/0
+* GPIOS_S3 : S18/0
+* GPIOS_S4 : S19/0
+* GPIOS_S5 : S20/0
+* GPIOS_S6 : S21/0
+* GPIOS_S7 : S22/0
+
+## JTAG
+
+JTAG
+
+* JTAG_TCK : E28/0
+* JTAG_TDI : E26/0
+* JTAG_TDO : E27/0
+* JTAG_TMS : E25/0
+
+## MSPI0
+
+SPI Master 1 (general)
+
+* MSPI0_CK : S8/0
+* MSPI0_MISO : S11/0
+* MSPI0_MOSI : S10/0
+* MSPI0_NSS : S9/0
+
+## MSPI1
+
+SPI Master 2 (SDCard)
+
+* MSPI1_CK : W7/0
+* MSPI1_MISO : W10/0
+* MSPI1_MOSI : W9/0
+* MSPI1_NSS : W8/0
+
+## MTWI
+
+I2C Master 1
+
+* MTWI_SCL : S3/0
+* MTWI_SDA : S2/0
+
+## PWM
+
+PWM
+
+* PWM_0 : W2/0
+* PWM_1 : W3/0
+
+## SD0
+
+SD/MMC 1
+
+* SD0_CLK : W12/0
+* SD0_CMD : W11/0
+* SD0_D0 : W13/0
+* SD0_D1 : W14/0
+* SD0_D2 : W15/0
+* SD0_D3 : W16/0
+
+## SDR
+
+SDRAM
+
+* SDR_AD0 : N11/0
+* SDR_AD1 : N12/0
+* SDR_AD10 : E2/0
+* SDR_AD11 : E3/0
+* SDR_AD12 : E4/0
+* SDR_AD2 : N13/0
+* SDR_AD3 : N14/0
+* SDR_AD4 : N15/0
+* SDR_AD5 : N16/0
+* SDR_AD6 : N17/0
+* SDR_AD7 : N18/0
+* SDR_AD8 : N19/0
+* SDR_AD9 : N20/0
+* SDR_BA0 : N21/0
+* SDR_BA1 : N22/0
+* SDR_CASn : N26/0
+* SDR_CKE : N24/0
+* SDR_CLK : N23/0
+* SDR_CSn0 : N28/0
+* SDR_D0 : N3/0
+* SDR_D1 : N4/0
+* SDR_D10 : E8/0
+* SDR_D11 : E9/0
+* SDR_D12 : E10/0
+* SDR_D13 : E11/0
+* SDR_D14 : E12/0
+* SDR_D15 : E13/0
+* SDR_D2 : N5/0
+* SDR_D3 : N6/0
+* SDR_D4 : N7/0
+* SDR_D5 : N8/0
+* SDR_D6 : N9/0
+* SDR_D7 : N10/0
+* SDR_D8 : E6/0
+* SDR_D9 : E7/0
+* SDR_DQM0 : N2/0
+* SDR_DQM1 : E5/0
+* SDR_RASn : N25/0
+* SDR_WEn : N27/0
+
+## SYS
+
+System Control
+
+* SYS_CLK : S23/0
+* SYS_CSEL0 : S27/0
+* SYS_CSEL1 : S28/0
+* SYS_PLLCLK : S25/0
+* SYS_PLLOCK : S29/0
+* SYS_PLLOUT : S26/0
+* SYS_RST : S24/0
+
+## UART0
+
+UART (TX/RX) 1
+
+* UART0_RX : S14/0
+* UART0_TX : S13/0
+
+## VDD
+
+Power
+
+* VDDE_0 : N1/0
+* VDDE_1 : E1/0
+* VDDE_2 : W1/0
+* VDDI_0 : N31/0
+* VDDI_1 : E15/0
+* VDDI_2 : S1/0
+* VDDI_3 : S31/0
+* VDDI_4 : W31/0
+
+## VSS
+
+GND
+
+* VSSE_0 : N0/0
+* VSSE_1 : E0/0
+* VSSE_2 : W0/0
+* VSSI_0 : N30/0
+* VSSI_1 : E14/0
+* VSSI_2 : S0/0
+* VSSI_3 : S30/0
+* VSSI_4 : W30/0
+
+# Pinmap for Libre-SOC 180nm
+
+## SD0
+
+user-facing: internal (on Card), multiplexed with JTAG
+and UART2, for debug purposes
+
+* SD0_CMD 107 W11/0
+* SD0_CLK 108 W12/0
+* SD0_D0 109 W13/0
+* SD0_D1 110 W14/0
+* SD0_D2 111 W15/0
+* SD0_D3 112 W16/0
+
+## UART0
+
+
+
+* UART0_TX 77 S13/0
+* UART0_RX 78 S14/0
+
+## GPIOS
+
+* GPIOS_S0 79 S15/0
+* GPIOS_S1 80 S16/0
+* GPIOS_S2 81 S17/0
+* GPIOS_S3 82 S18/0
+* GPIOS_S4 83 S19/0
+* GPIOS_S5 84 S20/0
+* GPIOS_S6 85 S21/0
+* GPIOS_S7 86 S22/0
+
+## GPIOE
+
+* GPIOE_E8 48 E16/0
+* GPIOE_E9 49 E17/0
+* GPIOE_E10 50 E18/0
+* GPIOE_E11 51 E19/0
+* GPIOE_E12 52 E20/0
+* GPIOE_E13 53 E21/0
+* GPIOE_E14 54 E22/0
+* GPIOE_E15 55 E23/0
+
+## JTAG
+
+* JTAG_TMS 57 E25/0
+* JTAG_TDI 58 E26/0
+* JTAG_TDO 59 E27/0
+* JTAG_TCK 60 E28/0
+
+## PWM
+
+* PWM_0 98 W2/0
+* PWM_1 99 W3/0
+
+## EINT
+
+* EINT_0 100 W4/0
+* EINT_1 101 W5/0
+* EINT_2 102 W6/0
+
+## VDD
+
+* VDDE_0 1 N1/0
+* VDDI_0 31 N31/0
+* VDDE_1 33 E1/0
+
+## VSS
+
+* VSSE_0 0 N0/0
+* VSSI_0 30 N30/0
+* VSSE_1 32 E0/0
+
+## SYS
+
+
+
+* SYS_CLK 87 S23/0
+* SYS_RST 88 S24/0
+* SYS_PLLCLK 89 S25/0
+* SYS_PLLOUT 90 S26/0
+* SYS_CSEL0 91 S27/0
+* SYS_CSEL1 92 S28/0
+* SYS_PLLOCK 93 S29/0
+
+## MTWI
+
+I2C.
+
+
+* MTWI_SDA 66 S2/0
+* MTWI_SCL 67 S3/0
+
+## MSPI0
+
+* MSPI0_CK 72 S8/0
+* MSPI0_NSS 73 S9/0
+* MSPI0_MOSI 74 S10/0
+* MSPI0_MISO 75 S11/0
+
+## MSPI1
+
+
+
+* MSPI1_CK 103 W7/0
+* MSPI1_NSS 104 W8/0
+* MSPI1_MOSI 105 W9/0
+* MSPI1_MISO 106 W10/0
+
+## SDR
+
+
+
+* SDR_DQM0 2 N2/0
+* SDR_D0 3 N3/0
+* SDR_D1 4 N4/0
+* SDR_D2 5 N5/0
+* SDR_D3 6 N6/0
+* SDR_D4 7 N7/0
+* SDR_D5 8 N8/0
+* SDR_D6 9 N9/0
+* SDR_D7 10 N10/0
+* SDR_AD0 11 N11/0
+* SDR_AD1 12 N12/0
+* SDR_AD2 13 N13/0
+* SDR_AD3 14 N14/0
+* SDR_AD4 15 N15/0
+* SDR_AD5 16 N16/0
+* SDR_AD6 17 N17/0
+* SDR_AD7 18 N18/0
+* SDR_AD8 19 N19/0
+* SDR_AD9 20 N20/0
+* SDR_BA0 21 N21/0
+* SDR_BA1 22 N22/0
+* SDR_CLK 23 N23/0
+* SDR_CKE 24 N24/0
+* SDR_RASn 25 N25/0
+* SDR_CASn 26 N26/0
+* SDR_WEn 27 N27/0
+* SDR_CSn0 28 N28/0
+* SDR_AD10 34 E2/0
+* SDR_AD11 35 E3/0
+* SDR_AD12 36 E4/0
+* SDR_DQM1 37 E5/0
+* SDR_D8 38 E6/0
+* SDR_D9 39 E7/0
+* SDR_D10 40 E8/0
+* SDR_D11 41 E9/0
+* SDR_D12 42 E10/0
+* SDR_D13 43 E11/0
+* SDR_D14 44 E12/0
+* SDR_D15 45 E13/0
+
+## Unused Pinouts (spare as GPIO) for 'Libre-SOC 180nm'
+
+| Pin | Mux0 | Mux1 | Mux2 | Mux3 |
+| --- | ----------- | ----------- | ----------- | ----------- |
+| 46 | E VSSI_1 | | | |
+| 47 | E VDDI_1 | | | |
+| 64 | S VSSI_2 | | | |
+| 65 | S VDDI_2 | | | |
+| 94 | S VSSI_3 | | | |
+| 95 | S VDDI_3 | | | |
+| 96 | W VSSE_2 | | | |
+| 97 | W VDDE_2 | | | |
+| 126 | W VSSI_4 | | | |
+| 127 | W VDDI_4 | | | |
+
+# Reference Datasheets
+
+datasheets and pinout links
+
+* <http://datasheets.chipdb.org/AMD/8018x/80186/amd-80186.pdf>
+* <http://hands.com/~lkcl/eoma/shenzen/frida/FRD144A2701.pdf>
+* <http://pinouts.ru/Memory/sdcard_pinout.shtml>
+* p8 <http://www.onfi.org/~/media/onfi/specs/onfi_2_0_gold.pdf?la=en>
+* <https://www.heyrick.co.uk/blog/files/datasheets/dm9000aep.pdf>
+* <http://cache.freescale.com/files/microcontrollers/doc/app_note/AN4393.pdf>
+* <https://www.nxp.com/docs/en/data-sheet/MCF54418.pdf>
+* ULPI OTG PHY, ST <http://www.st.com/en/interfaces-and-transceivers/stulpi01a.html>
+* ULPI OTG PHY, TI TUSB1210 <http://ti.com/product/TUSB1210/>
+
+# Pin Bank starting points and lengths
+
+* E 32 32 2
+* N 0 32 2
+* S 64 32 2
+* W 96 32 2
--- /dev/null
+# auto-generated by Libre-SOC pinmux program: do not edit
+# python src/pinmux_generator.py -v -s {spec} -o {output}
+pindict = {
+ 'mspi1': [ 'ck+', 'nss+', 'mosi+', 'miso-', ],
+ 'mspi0': [ 'ck+', 'nss+', 'mosi+', 'miso-', ],
+ 'vss': [ '0-', '1-', '2-', '3-',
+ '4-', ],
+ 'vdd': [ '0-', '1-', '2-', '3-',
+ '4-', ],
+ 'pwm': [ '0+', '1+', ],
+ 'jtag': [ 'tms-', 'tdi-', 'tdo+', 'tck+', ],
+ 'vdd': [ '0-', '1-', '2-', ],
+ 'sys': [ 'clk-', 'rst-', 'pllclk-', 'pllout+',
+ 'csel0-', 'csel1-', 'pllock+', ],
+ 'uart0': [ 'tx+', 'rx-', ],
+ 'vss': [ '0-', '1-', '2-', ],
+ 'sdr': [ 'dqm0+', 'd0*', 'd1*', 'd2*',
+ 'd3*', 'd4*', 'd5*', 'd6*',
+ 'd7*', 'ad0+', 'ad1+', 'ad2+',
+ 'ad3+', 'ad4+', 'ad5+', 'ad6+',
+ 'ad7+', 'ad8+', 'ad9+', 'ba0+',
+ 'ba1+', 'clk+', 'cke+', 'rasn+',
+ 'casn+', 'wen+', 'csn0+', 'ad10+',
+ 'ad11+', 'ad12+', 'dqm1*', 'd8*',
+ 'd9*', 'd10*', 'd11*', 'd12*',
+ 'd13*', 'd14*', 'd15*', ],
+ 'gpio': [ 'e8*', 'e9*', 'e10*', 'e11*',
+ 'e12*', 'e13*', 'e14*', 'e15*',
+ 's0*', 's1*', 's2*', 's3*',
+ 's4*', 's5*', 's6*', 's7*', ],
+ 'mtwi': [ 'sda*', 'scl+', ],
+ 'sd0': [ 'cmd*', 'clk+', 'd0*', 'd1*',
+ 'd2*', 'd3*', ],
+ 'eint': [ '0-', '1-', '2-', ],
+}
+
+litexdict = {
+ 'mspi1': [ 'spimaster_clk+', 'spimaster_cs_n+', 'spimaster_mosi+', 'spimaster_miso-', ],
+ 'mspi0': [ 'spisdcard_clk+', 'spisdcard_cs_n+', 'spisdcard_mosi+', 'spisdcard_miso-', ],
+ 'vss': [ '0-', '1-', '2-', '3-',
+ '4-', ],
+ 'vdd': [ '0-', '1-', '2-', '3-',
+ '4-', ],
+ 'pwm': [ 'pwm0+', 'pwm1+', ],
+ 'jtag': [ 'jtag_tms-', 'jtag_tdi-', 'jtag_tdo+', 'jtag_tck+', ],
+ 'vdd': [ '0-', '1-', '2-', ],
+ 'sys': [ 'sys_clk-', 'rst-', 'pllclk-', 'sys_pll_18_o+',
+ 'sys_clksel_0-', 'sys_clksel_1-', 'sys_pll_lck_o+', ],
+ 'uart0': [ 'uart_tx+', 'uart_rx-', ],
+ 'vss': [ '0-', '1-', '2-', ],
+ 'sdr': [ 'sdram_dm_0+', 'sdram_dq_0*', 'sdram_dq_1*', 'sdram_dq_2*',
+ 'sdram_dq_3*', 'sdram_dq_4*', 'sdram_dq_5*', 'sdram_dq_6*',
+ 'sdram_dq_7*', 'sdram_a_0+', 'sdram_a_1+', 'sdram_a_2+',
+ 'sdram_a_3+', 'sdram_a_4+', 'sdram_a_5+', 'sdram_a_6+',
+ 'sdram_a_7+', 'sdram_a_8+', 'sdram_a_9+', 'sdram_ba_0+',
+ 'sdram_ba_1+', 'sdram_clock+', 'sdram_cke+', 'sdram_ras_n+',
+ 'sdram_cas_n+', 'sdram_we_n+', 'sdram_cs_n+', 'sdram_a_10+',
+ 'sdram_a_11+', 'sdram_a_12+', 'sdram_dm_1*', 'sdram_dq_8*',
+ 'sdram_dq_9*', 'sdram_dq_10*', 'sdram_dq_11*', 'sdram_dq_12*',
+ 'sdram_dq_13*', 'sdram_dq_14*', 'sdram_dq_15*', ],
+ 'gpio': [ 'e8*', 'e9*', 'e10*', 'e11*',
+ 'e12*', 'e13*', 'e14*', 'e15*',
+ 's0*', 's1*', 's2*', 's3*',
+ 's4*', 's5*', 's6*', 's7*', ],
+ 'mtwi': [ 'i2c_sda*', 'i2c_scl+', ],
+ 'sd0': [ 'sdcard_cmd*', 'sdcard_clk+', 'sdcard_data0*', 'sdcard_data1*',
+ 'sdcard_data2*', 'sdcard_data3*', ],
+ 'eint': [ '0-', '1-', '2-', ],
+}
+
--- /dev/null
+ck out
+nss out
+mosi out
+miso in
--- /dev/null
+sda inout
+scl out
--- /dev/null
+0 N 2 vsse_0
+1 N 2 vdde_0
+2 N 2 sdr_dqm0
+3 N 2 sdr_d0
+4 N 2 sdr_d1
+5 N 2 sdr_d2
+6 N 2 sdr_d3
+7 N 2 sdr_d4
+8 N 2 sdr_d5
+9 N 2 sdr_d6
+10 N 2 sdr_d7
+11 N 2 sdr_ad0
+12 N 2 sdr_ad1
+13 N 2 sdr_ad2
+14 N 2 sdr_ad3
+15 N 2 sdr_ad4
+16 N 2 sdr_ad5
+17 N 2 sdr_ad6
+18 N 2 sdr_ad7
+19 N 2 sdr_ad8
+20 N 2 sdr_ad9
+21 N 2 sdr_ba0
+22 N 2 sdr_ba1
+23 N 2 sdr_clk
+24 N 2 sdr_cke
+25 N 2 sdr_rasn
+26 N 2 sdr_casn
+27 N 2 sdr_wen
+28 N 2 sdr_csn0
+30 N 2 vssi_0
+31 N 2 vddi_0
+32 E 2 vsse_1
+33 E 2 vdde_1
+34 E 2 sdr_ad10
+35 E 2 sdr_ad11
+36 E 2 sdr_ad12
+37 E 2 sdr_dqm1
+38 E 2 sdr_d8
+39 E 2 sdr_d9
+40 E 2 sdr_d10
+41 E 2 sdr_d11
+42 E 2 sdr_d12
+43 E 2 sdr_d13
+44 E 2 sdr_d14
+45 E 2 sdr_d15
+46 E 2 vssi_1
+47 E 2 vddi_1
+48 E 2 gpioe_e8
+49 E 2 gpioe_e9
+50 E 2 gpioe_e10
+51 E 2 gpioe_e11
+52 E 2 gpioe_e12
+53 E 2 gpioe_e13
+54 E 2 gpioe_e14
+55 E 2 gpioe_e15
+57 E 2 jtag_tms
+58 E 2 jtag_tdi
+59 E 2 jtag_tdo
+60 E 2 jtag_tck
+64 S 2 vssi_2
+65 S 2 vddi_2
+66 S 2 mtwi_sda
+67 S 2 mtwi_scl
+72 S 2 mspi0_ck
+73 S 2 mspi0_nss
+74 S 2 mspi0_mosi
+75 S 2 mspi0_miso
+77 S 2 uart0_tx
+78 S 2 uart0_rx
+79 S 2 gpios_s0
+80 S 2 gpios_s1
+81 S 2 gpios_s2
+82 S 2 gpios_s3
+83 S 2 gpios_s4
+84 S 2 gpios_s5
+85 S 2 gpios_s6
+86 S 2 gpios_s7
+87 S 2 sys_clk
+88 S 2 sys_rst
+89 S 2 sys_pllclk
+90 S 2 sys_pllout
+91 S 2 sys_csel0
+92 S 2 sys_csel1
+93 S 2 sys_pllock
+94 S 2 vssi_3
+95 S 2 vddi_3
+96 W 2 vsse_2
+97 W 2 vdde_2
+98 W 2 pwm_0
+99 W 2 pwm_1
+100 W 2 eint_0
+101 W 2 eint_1
+102 W 2 eint_2
+103 W 2 mspi1_ck
+104 W 2 mspi1_nss
+105 W 2 mspi1_mosi
+106 W 2 mspi1_miso
+107 W 2 sd0_cmd
+108 W 2 sd0_clk
+109 W 2 sd0_d0
+110 W 2 sd0_d1
+111 W 2 sd0_d2
+112 W 2 sd0_d3
+126 W 2 vssi_4
+127 W 2 vddi_4
--- /dev/null
+E 32 32 2
+N 0 32 2
+S 64 32 2
+W 96 32 2
--- /dev/null
+0 out
+1 out
--- /dev/null
+cmd inout
+clk out
+d0 inout bus
+d1 inout bus
+d2 inout bus
+d3 inout bus
--- /dev/null
+dqm0 out
+d0 inout bus
+d1 inout bus
+d2 inout bus
+d3 inout bus
+d4 inout bus
+d5 inout bus
+d6 inout bus
+d7 inout bus
+ad0 out
+ad1 out
+ad2 out
+ad3 out
+ad4 out
+ad5 out
+ad6 out
+ad7 out
+ad8 out
+ad9 out
+ba0 out
+ba1 out
+clk out
+cke out
+rasn out
+casn out
+wen out
+csn0 out
+ad10 out
+ad11 out
+ad12 out
+dqm1 inout
+d8 inout bus
+d9 inout bus
+d10 inout bus
+d11 inout bus
+d12 inout bus
+d13 inout bus
+d14 inout bus
+d15 inout bus
--- /dev/null
+clk in
+rst in
+pllclk in
+pllout out
+csel0 in
+csel1 in
+pllock out
--- /dev/null
+tx out
+rx in
--- /dev/null
+0 in
+1 in
+2 in
--- /dev/null
+0 in
+1 in
+2 in
--- /dev/null
+../pinmux/src/parse.py
\ No newline at end of file
--- /dev/null
+# -*- Mode:Python -*-
+
+import Cfg
+import CRL
+import Viewer
+from helpers.overlay import CfgCache
+import symbolic.cmos45 # do not remove
+import os
+
+if os.environ.has_key('CELLS_TOP'):
+ cellsTop = os.environ['CELLS_TOP']
+else:
+ cellsTop = '../../../alliance-check-toolkit/cells'
+
+with CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg:
+ cfg.misc.catchCore = False
+ cfg.misc.info = False
+ cfg.misc.paranoid = False
+ cfg.misc.bug = False
+ cfg.misc.logMode = True
+ cfg.misc.verboseLevel1 = True
+ cfg.misc.verboseLevel2 = True
+ cfg.anabatic.edgeLenght = 24
+ cfg.anabatic.edgeWidth = 8
+ cfg.anabatic.topRoutingLayer = 'METAL5'
+ cfg.etesian.graphics = 3
+
+ #cfg.katana.searchHalo = 30
+ #cfg.katana.eventsLimit = 1000000
+ #cfg.katana.hTracksReservedLocal = 7
+
+ # Run 2 (make-cgt-2.log)
+ #cfg.etesian.effort = 2
+ #cfg.etesian.uniformDensity = True
+ #cfg.etesian.spaceMargin = 0.05
+ #cfg.etesian.aspectRatio = 1.0
+ #cfg.katana.vTracksReservedLocal = 4
+ #cfg.katana.hTracksReservedLocal = 4
+
+ # Run 3 (make-cgt-3.log)
+ #cfg.etesian.effort = 2
+ #cfg.etesian.uniformDensity = False
+ #cfg.etesian.spaceMargin = 0.05
+ #cfg.etesian.aspectRatio = 1.0
+ #cfg.katana.vTracksReservedLocal = 5
+ #cfg.katana.hTracksReservedLocal = 5
+
+ # Run 4 (make-cgt-4.log)
+ #cfg.etesian.effort = 2
+ #cfg.etesian.uniformDensity = True
+ #cfg.etesian.spaceMargin = 0.05
+ #cfg.etesian.aspectRatio = 1.0
+
+ # Run 5 (make-cgt-5.log)
+ cfg.etesian.effort = 2
+ cfg.etesian.uniformDensity = True
+ cfg.etesian.spaceMargin = 0.05
+ cfg.etesian.aspectRatio = 1.0
+ cfg.katana.useGlobalEstimate = False
+ cfg.katana.vTracksReservedLocal = 7
+ cfg.katana.hTracksReservedLocal = 6
+ cfg.katana.bloatOverloadAdd = 4
+ cfg.conductor.stopLevel = 0
+ cfg.conductor.maxPlaceIterations = 2
+ cfg.conductor.useFixedAbHeight = False
+
+ af = CRL.AllianceFramework.get()
+ env = af.getEnvironment()
+ env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
+ env.addSYSTEM_LIBRARY(library=cellsTop+'/niolib',
+ mode=CRL.Environment.Prepend )
+ env.addSYSTEM_LIBRARY(library=cellsTop+'/nsxlib',
+ mode=CRL.Environment.Prepend )
+ env.addSYSTEM_LIBRARY(library='.',
+ mode=CRL.Environment.Prepend )
+ env.setPOWER ('vdd')
+ env.setGROUND('vss')
+ af.getCell( 'SPBlock_512W64B8W', CRL.Catalog.State.Logical )
+
+Viewer.Graphics.setStyle('Alliance.Classic [black]')
+
+print( ' o Successfully run "<>/coriolis2/settings.py".' )
+print( ' - CELLS_TOP = "{}"'.format(cellsTop) )
--- /dev/null
+coriolis2/ls180
\ No newline at end of file
--- /dev/null
+non_generated/full_core_ls180.il
\ No newline at end of file
--- /dev/null
+../non_generated
\ No newline at end of file
projects / soclayout.git / commitdiff