wire $0\builder_sync_rhs_array_muxed5[0:0]
attribute \src "ls180.v:7184.1-7200.4"
wire $0\builder_sync_rhs_array_muxed6[0:0]
- attribute \src "ls180.v:149.11-149.24"
+ attribute \src "ls180.v:140.11-140.24"
wire width 3 $0\eint_1[2:0]
attribute \src "ls180.v:7431.1-10055.4"
wire $0\main_cmd_consumed[0:0]
wire $0\main_libresocsim_interface2_converted_interface_stb[0:0]
attribute \src "ls180.v:2910.1-2956.4"
wire $0\main_libresocsim_interface2_converted_interface_we[0:0]
- attribute \src "ls180.v:150.12-150.74"
+ attribute \src "ls180.v:133.12-133.74"
wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
- attribute \src "ls180.v:154.5-154.69"
+ attribute \src "ls180.v:159.5-159.69"
wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
- attribute \src "ls180.v:134.5-134.72"
+ attribute \src "ls180.v:137.5-137.72"
wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
- attribute \src "ls180.v:138.12-138.78"
+ attribute \src "ls180.v:147.12-147.78"
wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
- attribute \src "ls180.v:161.5-161.74"
- wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
attribute \src "ls180.v:132.5-132.74"
+ wire $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
+ attribute \src "ls180.v:145.5-145.74"
wire $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
attribute \src "ls180.v:2850.1-2896.4"
wire $0\main_libresocsim_libresoc_dbus_ack[0:0]
wire \builder_sync_rhs_array_muxed6
attribute \src "ls180.v:1898.6-1898.18"
wire \builder_wait
- attribute \src "ls180.v:28.20-28.24"
- wire width 3 output 24 \eint
- attribute \src "ls180.v:149.11-149.17"
+ attribute \src "ls180.v:19.20-19.24"
+ wire width 3 output 15 \eint
+ attribute \src "ls180.v:140.11-140.17"
wire width 3 \eint_1
- attribute \src "ls180.v:29.21-29.27"
- wire width 16 output 25 \gpio_i
- attribute \src "ls180.v:30.21-30.27"
- wire width 16 output 26 \gpio_o
- attribute \src "ls180.v:31.21-31.28"
- wire width 16 output 27 \gpio_oe
- attribute \src "ls180.v:34.14-34.21"
- wire output 30 \i2c_scl
- attribute \src "ls180.v:35.14-35.23"
- wire output 31 \i2c_sda_i
- attribute \src "ls180.v:36.14-36.23"
- wire output 32 \i2c_sda_o
- attribute \src "ls180.v:37.14-37.24"
- wire output 33 \i2c_sda_oe
+ attribute \src "ls180.v:9.21-9.27"
+ wire width 16 output 5 \gpio_i
+ attribute \src "ls180.v:10.21-10.27"
+ wire width 16 output 6 \gpio_o
+ attribute \src "ls180.v:11.21-11.28"
+ wire width 16 output 7 \gpio_oe
+ attribute \src "ls180.v:39.14-39.21"
+ wire output 35 \i2c_scl
+ attribute \src "ls180.v:40.14-40.23"
+ wire output 36 \i2c_sda_i
+ attribute \src "ls180.v:41.14-41.23"
+ wire output 37 \i2c_sda_o
+ attribute \src "ls180.v:42.14-42.24"
+ wire output 38 \i2c_sda_oe
attribute \src "ls180.v:49.13-49.21"
wire input 45 \jtag_tck
attribute \src "ls180.v:50.13-50.21"
wire width 64 \main_libresocsim_libresoc2
attribute \src "ls180.v:127.12-127.45"
wire width 3 \main_libresocsim_libresoc_clk_sel
- attribute \src "ls180.v:150.12-150.66"
+ attribute \src "ls180.v:133.12-133.66"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i
- attribute \src "ls180.v:151.13-151.67"
+ attribute \src "ls180.v:134.13-134.67"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o
- attribute \src "ls180.v:152.13-152.68"
+ attribute \src "ls180.v:135.13-135.68"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe
- attribute \src "ls180.v:153.6-153.61"
+ attribute \src "ls180.v:158.6-158.61"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl
- attribute \src "ls180.v:154.5-154.62"
+ attribute \src "ls180.v:159.5-159.62"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i
- attribute \src "ls180.v:155.6-155.63"
+ attribute \src "ls180.v:160.6-160.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o
- attribute \src "ls180.v:156.6-156.64"
+ attribute \src "ls180.v:161.6-161.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe
- attribute \src "ls180.v:133.6-133.64"
+ attribute \src "ls180.v:136.6-136.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk
- attribute \src "ls180.v:134.5-134.65"
+ attribute \src "ls180.v:137.5-137.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i
- attribute \src "ls180.v:135.6-135.66"
+ attribute \src "ls180.v:138.6-138.66"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o
- attribute \src "ls180.v:136.6-136.67"
+ attribute \src "ls180.v:139.6-139.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe
- attribute \src "ls180.v:137.13-137.68"
+ attribute \src "ls180.v:146.13-146.68"
wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a
- attribute \src "ls180.v:146.12-146.68"
+ attribute \src "ls180.v:155.12-155.68"
wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba
- attribute \src "ls180.v:143.6-143.65"
+ attribute \src "ls180.v:152.6-152.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n
- attribute \src "ls180.v:145.6-145.63"
+ attribute \src "ls180.v:154.6-154.63"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke
- attribute \src "ls180.v:144.6-144.64"
+ attribute \src "ls180.v:153.6-153.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n
- attribute \src "ls180.v:147.12-147.68"
+ attribute \src "ls180.v:156.12-156.68"
wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm
- attribute \src "ls180.v:138.12-138.70"
+ attribute \src "ls180.v:147.12-147.70"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i
- attribute \src "ls180.v:139.13-139.71"
+ attribute \src "ls180.v:148.13-148.71"
wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o
- attribute \src "ls180.v:140.6-140.65"
+ attribute \src "ls180.v:149.6-149.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe
- attribute \src "ls180.v:142.6-142.65"
+ attribute \src "ls180.v:151.6-151.65"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n
- attribute \src "ls180.v:141.6-141.64"
+ attribute \src "ls180.v:150.6-150.64"
wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n
- attribute \src "ls180.v:158.6-158.67"
+ attribute \src "ls180.v:129.6-129.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk
- attribute \src "ls180.v:160.6-160.68"
+ attribute \src "ls180.v:131.6-131.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n
- attribute \src "ls180.v:161.5-161.67"
+ attribute \src "ls180.v:132.5-132.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso
- attribute \src "ls180.v:159.6-159.68"
+ attribute \src "ls180.v:130.6-130.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi
- attribute \src "ls180.v:129.6-129.67"
+ attribute \src "ls180.v:142.6-142.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk
- attribute \src "ls180.v:131.6-131.68"
+ attribute \src "ls180.v:144.6-144.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n
- attribute \src "ls180.v:132.5-132.67"
+ attribute \src "ls180.v:145.5-145.67"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso
- attribute \src "ls180.v:130.6-130.68"
+ attribute \src "ls180.v:143.6-143.68"
wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi
attribute \src "ls180.v:72.5-72.39"
wire \main_libresocsim_libresoc_dbus_ack
wire width 36 input 48 \nc
attribute \src "ls180.v:251.6-251.13"
wire \por_clk
- attribute \src "ls180.v:38.19-38.22"
- wire width 2 output 34 \pwm
- attribute \src "ls180.v:157.12-157.17"
+ attribute \src "ls180.v:22.19-22.22"
+ wire width 2 output 18 \pwm
+ attribute \src "ls180.v:141.12-141.17"
wire width 2 \pwm_1
- attribute \src "ls180.v:9.13-9.23"
- wire output 5 \sdcard_clk
- attribute \src "ls180.v:10.14-10.26"
- wire output 6 \sdcard_cmd_i
- attribute \src "ls180.v:11.13-11.25"
- wire output 7 \sdcard_cmd_o
- attribute \src "ls180.v:12.13-12.26"
- wire output 8 \sdcard_cmd_oe
- attribute \src "ls180.v:13.19-13.32"
- wire width 4 input 9 \sdcard_data_i
- attribute \src "ls180.v:14.19-14.32"
- wire width 4 output 10 \sdcard_data_o
- attribute \src "ls180.v:15.13-15.27"
- wire output 11 \sdcard_data_oe
- attribute \src "ls180.v:16.20-16.27"
- wire width 13 output 12 \sdram_a
- attribute \src "ls180.v:25.19-25.27"
- wire width 2 output 21 \sdram_ba
- attribute \src "ls180.v:22.13-22.24"
- wire output 18 \sdram_cas_n
- attribute \src "ls180.v:24.13-24.22"
- wire output 20 \sdram_cke
- attribute \src "ls180.v:27.13-27.24"
- wire output 23 \sdram_clock
- attribute \src "ls180.v:148.6-148.19"
+ attribute \src "ls180.v:12.13-12.23"
+ wire output 8 \sdcard_clk
+ attribute \src "ls180.v:13.14-13.26"
+ wire output 9 \sdcard_cmd_i
+ attribute \src "ls180.v:14.13-14.25"
+ wire output 10 \sdcard_cmd_o
+ attribute \src "ls180.v:15.13-15.26"
+ wire output 11 \sdcard_cmd_oe
+ attribute \src "ls180.v:16.19-16.32"
+ wire width 4 input 12 \sdcard_data_i
+ attribute \src "ls180.v:17.19-17.32"
+ wire width 4 output 13 \sdcard_data_o
+ attribute \src "ls180.v:18.13-18.27"
+ wire output 14 \sdcard_data_oe
+ attribute \src "ls180.v:27.20-27.27"
+ wire width 13 output 23 \sdram_a
+ attribute \src "ls180.v:36.19-36.27"
+ wire width 2 output 32 \sdram_ba
+ attribute \src "ls180.v:33.13-33.24"
+ wire output 29 \sdram_cas_n
+ attribute \src "ls180.v:35.13-35.22"
+ wire output 31 \sdram_cke
+ attribute \src "ls180.v:38.13-38.24"
+ wire output 34 \sdram_clock
+ attribute \src "ls180.v:157.6-157.19"
wire \sdram_clock_1
- attribute \src "ls180.v:23.13-23.23"
- wire output 19 \sdram_cs_n
- attribute \src "ls180.v:26.19-26.27"
- wire width 2 output 22 \sdram_dm
- attribute \src "ls180.v:17.21-17.31"
- wire width 16 output 13 \sdram_dq_i
- attribute \src "ls180.v:18.20-18.30"
- wire width 16 output 14 \sdram_dq_o
- attribute \src "ls180.v:19.13-19.24"
- wire output 15 \sdram_dq_oe
- attribute \src "ls180.v:21.13-21.24"
- wire output 17 \sdram_ras_n
- attribute \src "ls180.v:20.13-20.23"
- wire output 16 \sdram_we_n
+ attribute \src "ls180.v:34.13-34.23"
+ wire output 30 \sdram_cs_n
+ attribute \src "ls180.v:37.19-37.27"
+ wire width 2 output 33 \sdram_dm
+ attribute \src "ls180.v:28.21-28.31"
+ wire width 16 output 24 \sdram_dq_i
+ attribute \src "ls180.v:29.20-29.30"
+ wire width 16 output 25 \sdram_dq_o
+ attribute \src "ls180.v:30.13-30.24"
+ wire output 26 \sdram_dq_oe
+ attribute \src "ls180.v:32.13-32.24"
+ wire output 28 \sdram_ras_n
+ attribute \src "ls180.v:31.13-31.23"
+ wire output 27 \sdram_we_n
attribute \src "ls180.v:2647.6-2647.15"
wire \sdrio_clk
attribute \src "ls180.v:2648.6-2648.17"
wire \sdrio_clk_8
attribute \src "ls180.v:2656.6-2656.17"
wire \sdrio_clk_9
- attribute \src "ls180.v:39.13-39.26"
- wire output 35 \spimaster_clk
- attribute \src "ls180.v:41.13-41.27"
- wire output 37 \spimaster_cs_n
- attribute \src "ls180.v:42.14-42.28"
- wire output 38 \spimaster_miso
- attribute \src "ls180.v:40.13-40.27"
- wire output 36 \spimaster_mosi
attribute \src "ls180.v:5.13-5.26"
- wire output 1 \spisdcard_clk
+ wire output 1 \spimaster_clk
attribute \src "ls180.v:7.13-7.27"
- wire output 3 \spisdcard_cs_n
+ wire output 3 \spimaster_cs_n
attribute \src "ls180.v:8.14-8.28"
- wire output 4 \spisdcard_miso
+ wire output 4 \spimaster_miso
attribute \src "ls180.v:6.13-6.27"
- wire output 2 \spisdcard_mosi
+ wire output 2 \spimaster_mosi
+ attribute \src "ls180.v:23.13-23.26"
+ wire output 19 \spisdcard_clk
+ attribute \src "ls180.v:25.13-25.27"
+ wire output 21 \spisdcard_cs_n
+ attribute \src "ls180.v:26.14-26.28"
+ wire output 22 \spisdcard_miso
+ attribute \src "ls180.v:24.13-24.27"
+ wire output 20 \spisdcard_mosi
attribute \src "ls180.v:43.13-43.20"
wire input 39 \sys_clk
attribute \src "ls180.v:249.6-249.15"
wire input 40 \sys_rst
attribute \src "ls180.v:250.6-250.15"
wire \sys_rst_1
- attribute \src "ls180.v:33.13-33.20"
- wire input 29 \uart_rx
- attribute \src "ls180.v:32.13-32.20"
- wire output 28 \uart_tx
+ attribute \src "ls180.v:21.13-21.20"
+ wire input 17 \uart_rx
+ attribute \src "ls180.v:20.13-20.20"
+ wire output 16 \uart_tx
attribute \src "ls180.v:10057.12-10057.15"
memory width 32 size 128 \mem
attribute \src "ls180.v:10077.12-10077.19"
attribute \src "ls180.v:132.5-132.74"
process $proc$ls180.v:132$2787
assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0
sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
+ update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
sync init
end
attribute \src "ls180.v:1320.5-1320.48"
update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0]
sync init
end
+ attribute \src "ls180.v:133.12-133.74"
+ process $proc$ls180.v:133$2788
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
+ sync init
+ end
attribute \src "ls180.v:1331.5-1331.55"
process $proc$ls180.v:1331$3335
assign { } { }
update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0]
sync init
end
- attribute \src "ls180.v:134.5-134.72"
- process $proc$ls180.v:134$2788
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
- sync init
- end
attribute \src "ls180.v:1340.5-1340.54"
process $proc$ls180.v:1340$3338
assign { } { }
sync init
update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0]
end
- attribute \src "ls180.v:1371.11-1371.42"
- process $proc$ls180.v:1371$3351
+ attribute \src "ls180.v:137.5-137.72"
+ process $proc$ls180.v:137$2789
assign { } { }
- assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0
sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0]
sync init
- update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0]
end
- attribute \src "ls180.v:138.12-138.78"
- process $proc$ls180.v:138$2789
+ attribute \src "ls180.v:1371.11-1371.42"
+ process $proc$ls180.v:1371$3351
assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000
+ assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000
sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
sync init
+ update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0]
end
attribute \src "ls180.v:1384.12-1384.52"
process $proc$ls180.v:1384$3352
sync init
update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0]
end
+ attribute \src "ls180.v:140.11-140.24"
+ process $proc$ls180.v:140$2790
+ assign { } { }
+ assign $0\eint_1[2:0] 3'000
+ sync always
+ update \eint_1 $0\eint_1[2:0]
+ sync init
+ end
attribute \src "ls180.v:1400.12-1400.51"
process $proc$ls180.v:1400$3360
assign { } { }
sync init
update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0]
end
+ attribute \src "ls180.v:145.5-145.74"
+ process $proc$ls180.v:145$2791
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso[0:0]
+ sync init
+ end
attribute \src "ls180.v:1452.5-1452.51"
process $proc$ls180.v:1452$3365
assign { } { }
sync init
update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0]
end
+ attribute \src "ls180.v:147.12-147.78"
+ process $proc$ls180.v:147$2792
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0]
+ sync init
+ end
attribute \src "ls180.v:1472.12-1472.59"
process $proc$ls180.v:1472$3375
assign { } { }
sync init
update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0]
end
- attribute \src "ls180.v:149.11-149.24"
- process $proc$ls180.v:149$2790
- assign { } { }
- assign $0\eint_1[2:0] 3'000
- sync always
- update \eint_1 $0\eint_1[2:0]
- sync init
- end
attribute \src "ls180.v:1490.5-1490.48"
process $proc$ls180.v:1490$3383
assign { } { }
update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0]
sync init
end
- attribute \src "ls180.v:150.12-150.74"
- process $proc$ls180.v:150$2791
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0]
- sync init
- end
attribute \src "ls180.v:1500.11-1500.47"
process $proc$ls180.v:1500$3390
assign { } { }
sync init
update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0]
end
- attribute \src "ls180.v:154.5-154.69"
- process $proc$ls180.v:154$2792
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
- sync init
- end
attribute \src "ls180.v:1540.11-1540.39"
process $proc$ls180.v:1540$3413
assign { } { }
sync init
update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0]
end
+ attribute \src "ls180.v:159.5-159.69"
+ process $proc$ls180.v:159$2793
+ assign { } { }
+ assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0
+ sync always
+ update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0]
+ sync init
+ end
attribute \src "ls180.v:1605.5-1605.51"
process $proc$ls180.v:1605$3428
assign { } { }
sync init
update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[1:0]
end
- attribute \src "ls180.v:161.5-161.74"
- process $proc$ls180.v:161$2793
- assign { } { }
- assign $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0] 1'0
- sync always
- update \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso $0\main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso[0:0]
- sync init
- end
attribute \src "ls180.v:1611.5-1611.49"
process $proc$ls180.v:1611$3433
assign { } { }
end
attribute \src "ls180.v:7431.1-10055.4"
process $proc$ls180.v:7431$2374
- assign $0\spisdcard_clk[0:0] \spisdcard_clk
- assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
+ assign $0\spimaster_clk[0:0] \spimaster_clk
+ assign $0\spimaster_mosi[0:0] \spimaster_mosi
assign { } { }
assign $0\uart_tx[0:0] \uart_tx
assign $0\pwm[1:0] \pwm
- assign $0\spimaster_clk[0:0] \spimaster_clk
- assign $0\spimaster_mosi[0:0] \spimaster_mosi
+ assign $0\spisdcard_clk[0:0] \spisdcard_clk
+ assign $0\spisdcard_mosi[0:0] \spisdcard_mosi
assign { } { }
assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage
assign { } { }
assign $0\main_libresocsim_scratch_storage[31:0] 305419896
assign $0\main_libresocsim_scratch_re[0:0] 1'0
assign $0\main_libresocsim_bus_errors[31:0] 0
- assign $0\spisdcard_clk[0:0] 1'0
- assign $0\spisdcard_mosi[0:0] 1'0
- assign $0\spisdcard_cs_n[0:0] 1'0
- assign $0\uart_tx[0:0] 1'1
- assign $0\pwm[1:0] 2'00
assign $0\spimaster_clk[0:0] 1'0
assign $0\spimaster_mosi[0:0] 1'0
assign $0\spimaster_cs_n[0:0] 1'0
+ assign $0\uart_tx[0:0] 1'1
+ assign $0\pwm[1:0] 2'00
+ assign $0\spisdcard_clk[0:0] 1'0
+ assign $0\spisdcard_mosi[0:0] 1'0
+ assign $0\spisdcard_cs_n[0:0] 1'0
assign $0\main_libresocsim_converter0_counter[0:0] 1'0
assign $0\main_libresocsim_converter1_counter[0:0] 1'0
assign $0\main_libresocsim_converter2_counter[0:0] 1'0
case
end
sync posedge \sys_clk_1
- update \spisdcard_clk $0\spisdcard_clk[0:0]
- update \spisdcard_mosi $0\spisdcard_mosi[0:0]
- update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
- update \uart_tx $0\uart_tx[0:0]
- update \pwm $0\pwm[1:0]
update \spimaster_clk $0\spimaster_clk[0:0]
update \spimaster_mosi $0\spimaster_mosi[0:0]
update \spimaster_cs_n $0\spimaster_cs_n[0:0]
+ update \uart_tx $0\uart_tx[0:0]
+ update \pwm $0\pwm[1:0]
+ update \spisdcard_clk $0\spisdcard_clk[0:0]
+ update \spisdcard_mosi $0\spisdcard_mosi[0:0]
+ update \spisdcard_cs_n $0\spisdcard_cs_n[0:0]
update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0]
update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0]
update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0]
connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9
connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10193$2761_DATA
end
-attribute \src "libresoc.v:45741.1-45782.10"
+attribute \src "libresoc.v:45741.1-45785.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.pll"
attribute \generator "nMigen"
module \pll
attribute \src "libresoc.v:45742.7-45742.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:45771.3-45780.6"
+ attribute \src "libresoc.v:45774.3-45783.6"
wire $0\pll_18_o[0:0]
- attribute \src "libresoc.v:45761.3-45770.6"
+ attribute \src "libresoc.v:45764.3-45773.6"
wire $0\pll_lck_o[0:0]
- attribute \src "libresoc.v:45771.3-45780.6"
+ attribute \src "libresoc.v:45774.3-45783.6"
wire $1\pll_18_o[0:0]
- attribute \src "libresoc.v:45761.3-45770.6"
+ attribute \src "libresoc.v:45764.3-45773.6"
wire $1\pll_lck_o[0:0]
- attribute \src "libresoc.v:45759.17-45759.105"
- wire $eq$libresoc.v:45759$1558_Y
- attribute \src "libresoc.v:45760.17-45760.105"
- wire $eq$libresoc.v:45760$1559_Y
+ attribute \src "libresoc.v:45761.17-45761.105"
+ wire $eq$libresoc.v:45761$1558_Y
+ attribute \src "libresoc.v:45762.17-45762.105"
+ wire $eq$libresoc.v:45762$1559_Y
+ attribute \src "libresoc.v:45763.17-45763.98"
+ wire $not$libresoc.v:45763$1560_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
wire \$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21"
+ wire \$5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9"
wire input 1 \clk_24_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13"
wire output 4 \pll_lck_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- cell $eq $eq$libresoc.v:45759$1558
+ cell $eq $eq$libresoc.v:45761$1558
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clk_sel_i
connect \B 2'00
- connect \Y $eq$libresoc.v:45759$1558_Y
+ connect \Y $eq$libresoc.v:45761$1558_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19"
- cell $eq $eq$libresoc.v:45760$1559
+ cell $eq $eq$libresoc.v:45762$1559
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \clk_sel_i
connect \B 2'00
- connect \Y $eq$libresoc.v:45760$1559_Y
+ connect \Y $eq$libresoc.v:45762$1559_Y
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21"
+ cell $not $not$libresoc.v:45763$1560
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clk_24_i
+ connect \Y $not$libresoc.v:45763$1560_Y
end
attribute \src "libresoc.v:45742.7-45742.20"
- process $proc$libresoc.v:45742$1562
+ process $proc$libresoc.v:45742$1563
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:45761.3-45770.6"
- process $proc$libresoc.v:45761$1560
+ attribute \src "libresoc.v:45764.3-45773.6"
+ process $proc$libresoc.v:45764$1561
assign { } { }
assign { } { }
assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0]
- attribute \src "libresoc.v:45762.5-45762.29"
+ attribute \src "libresoc.v:45765.5-45765.29"
switch \initial
- attribute \src "libresoc.v:45762.9-45762.17"
+ attribute \src "libresoc.v:45765.9-45765.17"
case 1'1
case
end
sync always
update \pll_lck_o $0\pll_lck_o[0:0]
end
- attribute \src "libresoc.v:45771.3-45780.6"
- process $proc$libresoc.v:45771$1561
+ attribute \src "libresoc.v:45774.3-45783.6"
+ process $proc$libresoc.v:45774$1562
assign { } { }
assign { } { }
assign $0\pll_18_o[0:0] $1\pll_18_o[0:0]
- attribute \src "libresoc.v:45772.5-45772.29"
+ attribute \src "libresoc.v:45775.5-45775.29"
switch \initial
- attribute \src "libresoc.v:45772.9-45772.17"
+ attribute \src "libresoc.v:45775.9-45775.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\pll_18_o[0:0] \clk_24_i
+ assign $1\pll_18_o[0:0] \$5
case
assign $1\pll_18_o[0:0] 1'0
end
sync always
update \pll_18_o $0\pll_18_o[0:0]
end
- connect \$1 $eq$libresoc.v:45759$1558_Y
- connect \$3 $eq$libresoc.v:45760$1559_Y
+ connect \$1 $eq$libresoc.v:45761$1558_Y
+ connect \$3 $eq$libresoc.v:45762$1559_Y
+ connect \$5 $not$libresoc.v:45763$1560_Y
connect \clk_pll_o \clk_24_i
end
-attribute \src "libresoc.v:45786.1-45870.10"
+attribute \src "libresoc.v:45789.1-45873.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick"
attribute \generator "nMigen"
module \ppick
- attribute \src "libresoc.v:45843.17-45843.91"
- wire $not$libresoc.v:45843$1563_Y
- attribute \src "libresoc.v:45845.18-45845.93"
- wire $not$libresoc.v:45845$1565_Y
- attribute \src "libresoc.v:45847.18-45847.93"
- wire $not$libresoc.v:45847$1567_Y
- attribute \src "libresoc.v:45848.17-45848.138"
- wire width 8 $not$libresoc.v:45848$1568_Y
+ attribute \src "libresoc.v:45846.17-45846.91"
+ wire $not$libresoc.v:45846$1564_Y
+ attribute \src "libresoc.v:45848.18-45848.93"
+ wire $not$libresoc.v:45848$1566_Y
attribute \src "libresoc.v:45850.18-45850.93"
- wire $not$libresoc.v:45850$1570_Y
- attribute \src "libresoc.v:45852.18-45852.93"
- wire $not$libresoc.v:45852$1572_Y
- attribute \src "libresoc.v:45854.18-45854.93"
- wire $not$libresoc.v:45854$1574_Y
- attribute \src "libresoc.v:45857.17-45857.91"
- wire $not$libresoc.v:45857$1577_Y
- attribute \src "libresoc.v:45844.18-45844.116"
- wire $reduce_or$libresoc.v:45844$1564_Y
- attribute \src "libresoc.v:45846.18-45846.122"
- wire $reduce_or$libresoc.v:45846$1566_Y
- attribute \src "libresoc.v:45849.18-45849.128"
- wire $reduce_or$libresoc.v:45849$1569_Y
- attribute \src "libresoc.v:45851.18-45851.134"
- wire $reduce_or$libresoc.v:45851$1571_Y
- attribute \src "libresoc.v:45853.18-45853.140"
- wire $reduce_or$libresoc.v:45853$1573_Y
- attribute \src "libresoc.v:45855.18-45855.90"
- wire $reduce_or$libresoc.v:45855$1575_Y
- attribute \src "libresoc.v:45856.17-45856.103"
- wire $reduce_or$libresoc.v:45856$1576_Y
- attribute \src "libresoc.v:45858.17-45858.109"
- wire $reduce_or$libresoc.v:45858$1578_Y
+ wire $not$libresoc.v:45850$1568_Y
+ attribute \src "libresoc.v:45851.17-45851.138"
+ wire width 8 $not$libresoc.v:45851$1569_Y
+ attribute \src "libresoc.v:45853.18-45853.93"
+ wire $not$libresoc.v:45853$1571_Y
+ attribute \src "libresoc.v:45855.18-45855.93"
+ wire $not$libresoc.v:45855$1573_Y
+ attribute \src "libresoc.v:45857.18-45857.93"
+ wire $not$libresoc.v:45857$1575_Y
+ attribute \src "libresoc.v:45860.17-45860.91"
+ wire $not$libresoc.v:45860$1578_Y
+ attribute \src "libresoc.v:45847.18-45847.116"
+ wire $reduce_or$libresoc.v:45847$1565_Y
+ attribute \src "libresoc.v:45849.18-45849.122"
+ wire $reduce_or$libresoc.v:45849$1567_Y
+ attribute \src "libresoc.v:45852.18-45852.128"
+ wire $reduce_or$libresoc.v:45852$1570_Y
+ attribute \src "libresoc.v:45854.18-45854.134"
+ wire $reduce_or$libresoc.v:45854$1572_Y
+ attribute \src "libresoc.v:45856.18-45856.140"
+ wire $reduce_or$libresoc.v:45856$1574_Y
+ attribute \src "libresoc.v:45858.18-45858.90"
+ wire $reduce_or$libresoc.v:45858$1576_Y
+ attribute \src "libresoc.v:45859.17-45859.103"
+ wire $reduce_or$libresoc.v:45859$1577_Y
+ attribute \src "libresoc.v:45861.17-45861.109"
+ wire $reduce_or$libresoc.v:45861$1579_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
wire width 8 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45843$1563
+ cell $not $not$libresoc.v:45846$1564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:45843$1563_Y
+ connect \Y $not$libresoc.v:45846$1564_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45845$1565
+ cell $not $not$libresoc.v:45848$1566
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:45845$1565_Y
+ connect \Y $not$libresoc.v:45848$1566_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45847$1567
+ cell $not $not$libresoc.v:45850$1568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:45847$1567_Y
+ connect \Y $not$libresoc.v:45850$1568_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
- cell $not $not$libresoc.v:45848$1568
+ cell $not $not$libresoc.v:45851$1569
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
- connect \Y $not$libresoc.v:45848$1568_Y
+ connect \Y $not$libresoc.v:45851$1569_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45850$1570
+ cell $not $not$libresoc.v:45853$1571
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:45850$1570_Y
+ connect \Y $not$libresoc.v:45853$1571_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45852$1572
+ cell $not $not$libresoc.v:45855$1573
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:45852$1572_Y
+ connect \Y $not$libresoc.v:45855$1573_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45854$1574
+ cell $not $not$libresoc.v:45857$1575
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:45854$1574_Y
+ connect \Y $not$libresoc.v:45857$1575_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45857$1577
+ cell $not $not$libresoc.v:45860$1578
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:45857$1577_Y
+ connect \Y $not$libresoc.v:45860$1578_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45844$1564
+ cell $reduce_or $reduce_or$libresoc.v:45847$1565
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [5] \i [6] \i [7] \ni [3] }
- connect \Y $reduce_or$libresoc.v:45844$1564_Y
+ connect \Y $reduce_or$libresoc.v:45847$1565_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45846$1566
+ cell $reduce_or $reduce_or$libresoc.v:45849$1567
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
- connect \Y $reduce_or$libresoc.v:45846$1566_Y
+ connect \Y $reduce_or$libresoc.v:45849$1567_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45849$1569
+ cell $reduce_or $reduce_or$libresoc.v:45852$1570
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
- connect \Y $reduce_or$libresoc.v:45849$1569_Y
+ connect \Y $reduce_or$libresoc.v:45852$1570_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45851$1571
+ cell $reduce_or $reduce_or$libresoc.v:45854$1572
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
- connect \Y $reduce_or$libresoc.v:45851$1571_Y
+ connect \Y $reduce_or$libresoc.v:45854$1572_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45853$1573
+ cell $reduce_or $reduce_or$libresoc.v:45856$1574
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
- connect \Y $reduce_or$libresoc.v:45853$1573_Y
+ connect \Y $reduce_or$libresoc.v:45856$1574_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69"
- cell $reduce_or $reduce_or$libresoc.v:45855$1575
+ cell $reduce_or $reduce_or$libresoc.v:45858$1576
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:45855$1575_Y
+ connect \Y $reduce_or$libresoc.v:45858$1576_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45856$1576
+ cell $reduce_or $reduce_or$libresoc.v:45859$1577
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [7] \ni [1] }
- connect \Y $reduce_or$libresoc.v:45856$1576_Y
+ connect \Y $reduce_or$libresoc.v:45859$1577_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45858$1578
+ cell $reduce_or $reduce_or$libresoc.v:45861$1579
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [6] \i [7] \ni [2] }
- connect \Y $reduce_or$libresoc.v:45858$1578_Y
- end
- connect \$7 $not$libresoc.v:45843$1563_Y
- connect \$12 $reduce_or$libresoc.v:45844$1564_Y
- connect \$11 $not$libresoc.v:45845$1565_Y
- connect \$16 $reduce_or$libresoc.v:45846$1566_Y
- connect \$15 $not$libresoc.v:45847$1567_Y
- connect \$1 $not$libresoc.v:45848$1568_Y
- connect \$20 $reduce_or$libresoc.v:45849$1569_Y
- connect \$19 $not$libresoc.v:45850$1570_Y
- connect \$24 $reduce_or$libresoc.v:45851$1571_Y
- connect \$23 $not$libresoc.v:45852$1572_Y
- connect \$28 $reduce_or$libresoc.v:45853$1573_Y
- connect \$27 $not$libresoc.v:45854$1574_Y
- connect \$31 $reduce_or$libresoc.v:45855$1575_Y
- connect \$4 $reduce_or$libresoc.v:45856$1576_Y
- connect \$3 $not$libresoc.v:45857$1577_Y
- connect \$8 $reduce_or$libresoc.v:45858$1578_Y
+ connect \Y $reduce_or$libresoc.v:45861$1579_Y
+ end
+ connect \$7 $not$libresoc.v:45846$1564_Y
+ connect \$12 $reduce_or$libresoc.v:45847$1565_Y
+ connect \$11 $not$libresoc.v:45848$1566_Y
+ connect \$16 $reduce_or$libresoc.v:45849$1567_Y
+ connect \$15 $not$libresoc.v:45850$1568_Y
+ connect \$1 $not$libresoc.v:45851$1569_Y
+ connect \$20 $reduce_or$libresoc.v:45852$1570_Y
+ connect \$19 $not$libresoc.v:45853$1571_Y
+ connect \$24 $reduce_or$libresoc.v:45854$1572_Y
+ connect \$23 $not$libresoc.v:45855$1573_Y
+ connect \$28 $reduce_or$libresoc.v:45856$1574_Y
+ connect \$27 $not$libresoc.v:45857$1575_Y
+ connect \$31 $reduce_or$libresoc.v:45858$1576_Y
+ connect \$4 $reduce_or$libresoc.v:45859$1577_Y
+ connect \$3 $not$libresoc.v:45860$1578_Y
+ connect \$8 $reduce_or$libresoc.v:45861$1579_Y
connect \en_o \$31
connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
connect \t7 \$27
connect \t0 \i [7]
connect \ni \$1
end
-attribute \src "libresoc.v:45874.1-45958.10"
+attribute \src "libresoc.v:45877.1-45961.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick"
attribute \generator "nMigen"
module \ppick$1
- attribute \src "libresoc.v:45931.17-45931.91"
- wire $not$libresoc.v:45931$1579_Y
- attribute \src "libresoc.v:45933.18-45933.93"
- wire $not$libresoc.v:45933$1581_Y
- attribute \src "libresoc.v:45935.18-45935.93"
- wire $not$libresoc.v:45935$1583_Y
- attribute \src "libresoc.v:45936.17-45936.138"
- wire width 8 $not$libresoc.v:45936$1584_Y
+ attribute \src "libresoc.v:45934.17-45934.91"
+ wire $not$libresoc.v:45934$1580_Y
+ attribute \src "libresoc.v:45936.18-45936.93"
+ wire $not$libresoc.v:45936$1582_Y
attribute \src "libresoc.v:45938.18-45938.93"
- wire $not$libresoc.v:45938$1586_Y
- attribute \src "libresoc.v:45940.18-45940.93"
- wire $not$libresoc.v:45940$1588_Y
- attribute \src "libresoc.v:45942.18-45942.93"
- wire $not$libresoc.v:45942$1590_Y
- attribute \src "libresoc.v:45945.17-45945.91"
- wire $not$libresoc.v:45945$1593_Y
- attribute \src "libresoc.v:45932.18-45932.116"
- wire $reduce_or$libresoc.v:45932$1580_Y
- attribute \src "libresoc.v:45934.18-45934.122"
- wire $reduce_or$libresoc.v:45934$1582_Y
- attribute \src "libresoc.v:45937.18-45937.128"
- wire $reduce_or$libresoc.v:45937$1585_Y
- attribute \src "libresoc.v:45939.18-45939.134"
- wire $reduce_or$libresoc.v:45939$1587_Y
- attribute \src "libresoc.v:45941.18-45941.140"
- wire $reduce_or$libresoc.v:45941$1589_Y
- attribute \src "libresoc.v:45943.18-45943.90"
- wire $reduce_or$libresoc.v:45943$1591_Y
- attribute \src "libresoc.v:45944.17-45944.103"
- wire $reduce_or$libresoc.v:45944$1592_Y
- attribute \src "libresoc.v:45946.17-45946.109"
- wire $reduce_or$libresoc.v:45946$1594_Y
+ wire $not$libresoc.v:45938$1584_Y
+ attribute \src "libresoc.v:45939.17-45939.138"
+ wire width 8 $not$libresoc.v:45939$1585_Y
+ attribute \src "libresoc.v:45941.18-45941.93"
+ wire $not$libresoc.v:45941$1587_Y
+ attribute \src "libresoc.v:45943.18-45943.93"
+ wire $not$libresoc.v:45943$1589_Y
+ attribute \src "libresoc.v:45945.18-45945.93"
+ wire $not$libresoc.v:45945$1591_Y
+ attribute \src "libresoc.v:45948.17-45948.91"
+ wire $not$libresoc.v:45948$1594_Y
+ attribute \src "libresoc.v:45935.18-45935.116"
+ wire $reduce_or$libresoc.v:45935$1581_Y
+ attribute \src "libresoc.v:45937.18-45937.122"
+ wire $reduce_or$libresoc.v:45937$1583_Y
+ attribute \src "libresoc.v:45940.18-45940.128"
+ wire $reduce_or$libresoc.v:45940$1586_Y
+ attribute \src "libresoc.v:45942.18-45942.134"
+ wire $reduce_or$libresoc.v:45942$1588_Y
+ attribute \src "libresoc.v:45944.18-45944.140"
+ wire $reduce_or$libresoc.v:45944$1590_Y
+ attribute \src "libresoc.v:45946.18-45946.90"
+ wire $reduce_or$libresoc.v:45946$1592_Y
+ attribute \src "libresoc.v:45947.17-45947.103"
+ wire $reduce_or$libresoc.v:45947$1593_Y
+ attribute \src "libresoc.v:45949.17-45949.109"
+ wire $reduce_or$libresoc.v:45949$1595_Y
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
wire width 8 \$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58"
wire \t7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45931$1579
+ cell $not $not$libresoc.v:45934$1580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$8
- connect \Y $not$libresoc.v:45931$1579_Y
+ connect \Y $not$libresoc.v:45934$1580_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45933$1581
+ cell $not $not$libresoc.v:45936$1582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$12
- connect \Y $not$libresoc.v:45933$1581_Y
+ connect \Y $not$libresoc.v:45936$1582_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45935$1583
+ cell $not $not$libresoc.v:45938$1584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$16
- connect \Y $not$libresoc.v:45935$1583_Y
+ connect \Y $not$libresoc.v:45938$1584_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53"
- cell $not $not$libresoc.v:45936$1584
+ cell $not $not$libresoc.v:45939$1585
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 8
connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] }
- connect \Y $not$libresoc.v:45936$1584_Y
+ connect \Y $not$libresoc.v:45939$1585_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45938$1586
+ cell $not $not$libresoc.v:45941$1587
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$20
- connect \Y $not$libresoc.v:45938$1586_Y
+ connect \Y $not$libresoc.v:45941$1587_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45940$1588
+ cell $not $not$libresoc.v:45943$1589
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$24
- connect \Y $not$libresoc.v:45940$1588_Y
+ connect \Y $not$libresoc.v:45943$1589_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45942$1590
+ cell $not $not$libresoc.v:45945$1591
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$28
- connect \Y $not$libresoc.v:45942$1590_Y
+ connect \Y $not$libresoc.v:45945$1591_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $not $not$libresoc.v:45945$1593
+ cell $not $not$libresoc.v:45948$1594
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \$4
- connect \Y $not$libresoc.v:45945$1593_Y
+ connect \Y $not$libresoc.v:45948$1594_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45932$1580
+ cell $reduce_or $reduce_or$libresoc.v:45935$1581
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \i [5] \i [6] \i [7] \ni [3] }
- connect \Y $reduce_or$libresoc.v:45932$1580_Y
+ connect \Y $reduce_or$libresoc.v:45935$1581_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45934$1582
+ cell $reduce_or $reduce_or$libresoc.v:45937$1583
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] }
- connect \Y $reduce_or$libresoc.v:45934$1582_Y
+ connect \Y $reduce_or$libresoc.v:45937$1583_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45937$1585
+ cell $reduce_or $reduce_or$libresoc.v:45940$1586
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] }
- connect \Y $reduce_or$libresoc.v:45937$1585_Y
+ connect \Y $reduce_or$libresoc.v:45940$1586_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45939$1587
+ cell $reduce_or $reduce_or$libresoc.v:45942$1588
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] }
- connect \Y $reduce_or$libresoc.v:45939$1587_Y
+ connect \Y $reduce_or$libresoc.v:45942$1588_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45941$1589
+ cell $reduce_or $reduce_or$libresoc.v:45944$1590
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] }
- connect \Y $reduce_or$libresoc.v:45941$1589_Y
+ connect \Y $reduce_or$libresoc.v:45944$1590_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69"
- cell $reduce_or $reduce_or$libresoc.v:45943$1591
+ cell $reduce_or $reduce_or$libresoc.v:45946$1592
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $reduce_or$libresoc.v:45943$1591_Y
+ connect \Y $reduce_or$libresoc.v:45946$1592_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45944$1592
+ cell $reduce_or $reduce_or$libresoc.v:45947$1593
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \i [7] \ni [1] }
- connect \Y $reduce_or$libresoc.v:45944$1592_Y
+ connect \Y $reduce_or$libresoc.v:45947$1593_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63"
- cell $reduce_or $reduce_or$libresoc.v:45946$1594
+ cell $reduce_or $reduce_or$libresoc.v:45949$1595
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A { \i [6] \i [7] \ni [2] }
- connect \Y $reduce_or$libresoc.v:45946$1594_Y
- end
- connect \$7 $not$libresoc.v:45931$1579_Y
- connect \$12 $reduce_or$libresoc.v:45932$1580_Y
- connect \$11 $not$libresoc.v:45933$1581_Y
- connect \$16 $reduce_or$libresoc.v:45934$1582_Y
- connect \$15 $not$libresoc.v:45935$1583_Y
- connect \$1 $not$libresoc.v:45936$1584_Y
- connect \$20 $reduce_or$libresoc.v:45937$1585_Y
- connect \$19 $not$libresoc.v:45938$1586_Y
- connect \$24 $reduce_or$libresoc.v:45939$1587_Y
- connect \$23 $not$libresoc.v:45940$1588_Y
- connect \$28 $reduce_or$libresoc.v:45941$1589_Y
- connect \$27 $not$libresoc.v:45942$1590_Y
- connect \$31 $reduce_or$libresoc.v:45943$1591_Y
- connect \$4 $reduce_or$libresoc.v:45944$1592_Y
- connect \$3 $not$libresoc.v:45945$1593_Y
- connect \$8 $reduce_or$libresoc.v:45946$1594_Y
+ connect \Y $reduce_or$libresoc.v:45949$1595_Y
+ end
+ connect \$7 $not$libresoc.v:45934$1580_Y
+ connect \$12 $reduce_or$libresoc.v:45935$1581_Y
+ connect \$11 $not$libresoc.v:45936$1582_Y
+ connect \$16 $reduce_or$libresoc.v:45937$1583_Y
+ connect \$15 $not$libresoc.v:45938$1584_Y
+ connect \$1 $not$libresoc.v:45939$1585_Y
+ connect \$20 $reduce_or$libresoc.v:45940$1586_Y
+ connect \$19 $not$libresoc.v:45941$1587_Y
+ connect \$24 $reduce_or$libresoc.v:45942$1588_Y
+ connect \$23 $not$libresoc.v:45943$1589_Y
+ connect \$28 $reduce_or$libresoc.v:45944$1590_Y
+ connect \$27 $not$libresoc.v:45945$1591_Y
+ connect \$31 $reduce_or$libresoc.v:45946$1592_Y
+ connect \$4 $reduce_or$libresoc.v:45947$1593_Y
+ connect \$3 $not$libresoc.v:45948$1594_Y
+ connect \$8 $reduce_or$libresoc.v:45949$1595_Y
connect \en_o \$31
connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 }
connect \t7 \$27
connect \t0 \i [7]
connect \ni \$1
end
-attribute \src "libresoc.v:45962.1-46777.10"
+attribute \src "libresoc.v:45965.1-46780.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap"
attribute \generator "nMigen"
module \sprmap
- attribute \src "libresoc.v:46089.3-46119.6"
+ attribute \src "libresoc.v:46092.3-46122.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:46120.3-46150.6"
+ attribute \src "libresoc.v:46123.3-46153.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:45963.7-45963.20"
+ attribute \src "libresoc.v:45966.7-45966.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:46151.3-46463.6"
+ attribute \src "libresoc.v:46154.3-46466.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:46464.3-46776.6"
+ attribute \src "libresoc.v:46467.3-46779.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:46089.3-46119.6"
+ attribute \src "libresoc.v:46092.3-46122.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:46120.3-46150.6"
+ attribute \src "libresoc.v:46123.3-46153.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:46151.3-46463.6"
+ attribute \src "libresoc.v:46154.3-46466.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:46464.3-46776.6"
+ attribute \src "libresoc.v:46467.3-46779.6"
wire $1\spr_o_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 3 output 3 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:45963.7-45963.15"
+ attribute \src "libresoc.v:45966.7-45966.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
wire width 10 input 5 \spr_i
wire width 10 output 1 \spr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:45963.7-45963.20"
- process $proc$libresoc.v:45963$1599
+ attribute \src "libresoc.v:45966.7-45966.20"
+ process $proc$libresoc.v:45966$1600
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:46089.3-46119.6"
- process $proc$libresoc.v:46089$1595
+ attribute \src "libresoc.v:46092.3-46122.6"
+ process $proc$libresoc.v:46092$1596
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:46090.5-46090.29"
+ attribute \src "libresoc.v:46093.5-46093.29"
switch \initial
- attribute \src "libresoc.v:46090.9-46090.17"
+ attribute \src "libresoc.v:46093.9-46093.17"
case 1'1
case
end
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:46120.3-46150.6"
- process $proc$libresoc.v:46120$1596
+ attribute \src "libresoc.v:46123.3-46153.6"
+ process $proc$libresoc.v:46123$1597
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:46121.5-46121.29"
+ attribute \src "libresoc.v:46124.5-46124.29"
switch \initial
- attribute \src "libresoc.v:46121.9-46121.17"
+ attribute \src "libresoc.v:46124.9-46124.17"
case 1'1
case
end
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:46151.3-46463.6"
- process $proc$libresoc.v:46151$1597
+ attribute \src "libresoc.v:46154.3-46466.6"
+ process $proc$libresoc.v:46154$1598
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:46152.5-46152.29"
+ attribute \src "libresoc.v:46155.5-46155.29"
switch \initial
- attribute \src "libresoc.v:46152.9-46152.17"
+ attribute \src "libresoc.v:46155.9-46155.17"
case 1'1
case
end
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:46464.3-46776.6"
- process $proc$libresoc.v:46464$1598
+ attribute \src "libresoc.v:46467.3-46779.6"
+ process $proc$libresoc.v:46467$1599
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:46465.5-46465.29"
+ attribute \src "libresoc.v:46468.5-46468.29"
switch \initial
- attribute \src "libresoc.v:46465.9-46465.17"
+ attribute \src "libresoc.v:46468.9-46468.17"
case 1'1
case
end
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:46781.1-47596.10"
+attribute \src "libresoc.v:46784.1-47599.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap"
attribute \generator "nMigen"
module \sprmap$2
- attribute \src "libresoc.v:46908.3-46938.6"
+ attribute \src "libresoc.v:46911.3-46941.6"
wire width 3 $0\fast_o[2:0]
- attribute \src "libresoc.v:46939.3-46969.6"
+ attribute \src "libresoc.v:46942.3-46972.6"
wire $0\fast_o_ok[0:0]
- attribute \src "libresoc.v:46782.7-46782.20"
+ attribute \src "libresoc.v:46785.7-46785.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:46970.3-47282.6"
+ attribute \src "libresoc.v:46973.3-47285.6"
wire width 10 $0\spr_o[9:0]
- attribute \src "libresoc.v:47283.3-47595.6"
+ attribute \src "libresoc.v:47286.3-47598.6"
wire $0\spr_o_ok[0:0]
- attribute \src "libresoc.v:46908.3-46938.6"
+ attribute \src "libresoc.v:46911.3-46941.6"
wire width 3 $1\fast_o[2:0]
- attribute \src "libresoc.v:46939.3-46969.6"
+ attribute \src "libresoc.v:46942.3-46972.6"
wire $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:46970.3-47282.6"
+ attribute \src "libresoc.v:46973.3-47285.6"
wire width 10 $1\spr_o[9:0]
- attribute \src "libresoc.v:47283.3-47595.6"
+ attribute \src "libresoc.v:47286.3-47598.6"
wire $1\spr_o_ok[0:0]
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire width 3 output 3 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 4 \fast_o_ok
- attribute \src "libresoc.v:46782.7-46782.15"
+ attribute \src "libresoc.v:46785.7-46785.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
wire width 10 input 5 \spr_i
wire width 10 output 1 \spr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18"
wire output 2 \spr_o_ok
- attribute \src "libresoc.v:46782.7-46782.20"
- process $proc$libresoc.v:46782$1604
+ attribute \src "libresoc.v:46785.7-46785.20"
+ process $proc$libresoc.v:46785$1605
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:46908.3-46938.6"
- process $proc$libresoc.v:46908$1600
+ attribute \src "libresoc.v:46911.3-46941.6"
+ process $proc$libresoc.v:46911$1601
assign { } { }
assign { } { }
assign $0\fast_o[2:0] $1\fast_o[2:0]
- attribute \src "libresoc.v:46909.5-46909.29"
+ attribute \src "libresoc.v:46912.5-46912.29"
switch \initial
- attribute \src "libresoc.v:46909.9-46909.17"
+ attribute \src "libresoc.v:46912.9-46912.17"
case 1'1
case
end
sync always
update \fast_o $0\fast_o[2:0]
end
- attribute \src "libresoc.v:46939.3-46969.6"
- process $proc$libresoc.v:46939$1601
+ attribute \src "libresoc.v:46942.3-46972.6"
+ process $proc$libresoc.v:46942$1602
assign { } { }
assign { } { }
assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0]
- attribute \src "libresoc.v:46940.5-46940.29"
+ attribute \src "libresoc.v:46943.5-46943.29"
switch \initial
- attribute \src "libresoc.v:46940.9-46940.17"
+ attribute \src "libresoc.v:46943.9-46943.17"
case 1'1
case
end
sync always
update \fast_o_ok $0\fast_o_ok[0:0]
end
- attribute \src "libresoc.v:46970.3-47282.6"
- process $proc$libresoc.v:46970$1602
+ attribute \src "libresoc.v:46973.3-47285.6"
+ process $proc$libresoc.v:46973$1603
assign { } { }
assign { } { }
assign $0\spr_o[9:0] $1\spr_o[9:0]
- attribute \src "libresoc.v:46971.5-46971.29"
+ attribute \src "libresoc.v:46974.5-46974.29"
switch \initial
- attribute \src "libresoc.v:46971.9-46971.17"
+ attribute \src "libresoc.v:46974.9-46974.17"
case 1'1
case
end
sync always
update \spr_o $0\spr_o[9:0]
end
- attribute \src "libresoc.v:47283.3-47595.6"
- process $proc$libresoc.v:47283$1603
+ attribute \src "libresoc.v:47286.3-47598.6"
+ process $proc$libresoc.v:47286$1604
assign { } { }
assign { } { }
assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0]
- attribute \src "libresoc.v:47284.5-47284.29"
+ attribute \src "libresoc.v:47287.5-47287.29"
switch \initial
- attribute \src "libresoc.v:47284.9-47284.17"
+ attribute \src "libresoc.v:47287.9-47287.17"
case 1'1
case
end
update \spr_o_ok $0\spr_o_ok[0:0]
end
end
-attribute \src "libresoc.v:47601.1-48733.10"
+attribute \src "libresoc.v:47604.1-48736.10"
attribute \cells_not_processed 1
attribute \top 1
attribute \nmigen.hierarchy "test_issuer"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169"
wire \ti_coresync_clk
attribute \module_not_derived 1
- attribute \src "libresoc.v:48368.7-48374.4"
+ attribute \src "libresoc.v:48371.7-48377.4"
cell \pll \pll
connect \clk_24_i \pll_clk_24_i
connect \clk_pll_o \pll_clk_pll_o
connect \pll_lck_o \pll_lck_o
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:48375.6-48727.4"
+ attribute \src "libresoc.v:48378.6-48730.4"
cell \ti \ti
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \pll_clk_24_i \clk
connect \pllclk_clk \pll_clk_pll_o
end
-attribute \src "libresoc.v:48737.1-52515.10"
+attribute \src "libresoc.v:48740.1-52518.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti"
attribute \generator "nMigen"
module \ti
- attribute \src "libresoc.v:52247.3-52283.6"
- wire $0\bigendian_i$next[0:0]$2135
- attribute \src "libresoc.v:50864.3-50865.39"
+ attribute \src "libresoc.v:52250.3-52286.6"
+ wire $0\bigendian_i$next[0:0]$2136
+ attribute \src "libresoc.v:50867.3-50868.39"
wire $0\bigendian_i[0:0]
- attribute \src "libresoc.v:51945.3-51957.6"
+ attribute \src "libresoc.v:51948.3-51960.6"
wire width 4 $0\cia__ren[3:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $0\core_asmcode$next[7:0]$1853
- attribute \src "libresoc.v:50868.3-50869.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $0\core_asmcode$next[7:0]$1854
+ attribute \src "libresoc.v:50871.3-50872.41"
wire width 8 $0\core_asmcode[7:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 64 $0\core_core_cia$next[63:0]$1854
- attribute \src "libresoc.v:50944.3-50945.43"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 64 $0\core_core_cia$next[63:0]$1855
+ attribute \src "libresoc.v:50947.3-50948.43"
wire width 64 $0\core_core_cia[63:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $0\core_core_cr_rd$next[7:0]$1855
- attribute \src "libresoc.v:50988.3-50989.47"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $0\core_core_cr_rd$next[7:0]$1856
+ attribute \src "libresoc.v:50991.3-50992.47"
wire width 8 $0\core_core_cr_rd[7:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_cr_rd_ok$next[0:0]$1856
- attribute \src "libresoc.v:50990.3-50991.53"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_cr_rd_ok$next[0:0]$1857
+ attribute \src "libresoc.v:50993.3-50994.53"
wire $0\core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $0\core_core_cr_wr$next[7:0]$1857
- attribute \src "libresoc.v:50992.3-50993.47"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $0\core_core_cr_wr$next[7:0]$1858
+ attribute \src "libresoc.v:50995.3-50996.47"
wire width 8 $0\core_core_cr_wr[7:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_cr_wr_ok$next[0:0]$1858
- attribute \src "libresoc.v:50994.3-50995.53"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_cr_wr_ok$next[0:0]$1859
+ attribute \src "libresoc.v:50997.3-50998.53"
wire $0\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_exc_$signal$50$next[0:0]$1859
- attribute \src "libresoc.v:50970.3-50971.67"
- wire $0\core_core_exc_$signal$50[0:0]$1728
- attribute \src "libresoc.v:48910.7-48910.40"
- wire $0\core_core_exc_$signal$50[0:0]$2174
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_exc_$signal$51$next[0:0]$1860
- attribute \src "libresoc.v:50972.3-50973.67"
- wire $0\core_core_exc_$signal$51[0:0]$1730
- attribute \src "libresoc.v:48914.7-48914.40"
- wire $0\core_core_exc_$signal$51[0:0]$2176
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_exc_$signal$52$next[0:0]$1861
- attribute \src "libresoc.v:50974.3-50975.67"
- wire $0\core_core_exc_$signal$52[0:0]$1732
- attribute \src "libresoc.v:48918.7-48918.40"
- wire $0\core_core_exc_$signal$52[0:0]$2178
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_exc_$signal$53$next[0:0]$1862
- attribute \src "libresoc.v:50976.3-50977.67"
- wire $0\core_core_exc_$signal$53[0:0]$1734
- attribute \src "libresoc.v:48922.7-48922.40"
- wire $0\core_core_exc_$signal$53[0:0]$2180
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_exc_$signal$54$next[0:0]$1863
- attribute \src "libresoc.v:50978.3-50979.67"
- wire $0\core_core_exc_$signal$54[0:0]$1736
- attribute \src "libresoc.v:48926.7-48926.40"
- wire $0\core_core_exc_$signal$54[0:0]$2182
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_exc_$signal$55$next[0:0]$1864
- attribute \src "libresoc.v:50980.3-50981.67"
- wire $0\core_core_exc_$signal$55[0:0]$1738
- attribute \src "libresoc.v:48930.7-48930.40"
- wire $0\core_core_exc_$signal$55[0:0]$2184
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_exc_$signal$56$next[0:0]$1865
- attribute \src "libresoc.v:50982.3-50983.67"
- wire $0\core_core_exc_$signal$56[0:0]$1740
- attribute \src "libresoc.v:48934.7-48934.40"
- wire $0\core_core_exc_$signal$56[0:0]$2186
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_exc_$signal$next[0:0]$1866
- attribute \src "libresoc.v:50968.3-50969.61"
- wire $0\core_core_exc_$signal[0:0]$1726
- attribute \src "libresoc.v:48908.7-48908.37"
- wire $0\core_core_exc_$signal[0:0]$2172
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 12 $0\core_core_fn_unit$next[11:0]$1867
- attribute \src "libresoc.v:50950.3-50951.51"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_exc_$signal$50$next[0:0]$1860
+ attribute \src "libresoc.v:50973.3-50974.67"
+ wire $0\core_core_exc_$signal$50[0:0]$1729
+ attribute \src "libresoc.v:48913.7-48913.40"
+ wire $0\core_core_exc_$signal$50[0:0]$2175
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_exc_$signal$51$next[0:0]$1861
+ attribute \src "libresoc.v:50975.3-50976.67"
+ wire $0\core_core_exc_$signal$51[0:0]$1731
+ attribute \src "libresoc.v:48917.7-48917.40"
+ wire $0\core_core_exc_$signal$51[0:0]$2177
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_exc_$signal$52$next[0:0]$1862
+ attribute \src "libresoc.v:50977.3-50978.67"
+ wire $0\core_core_exc_$signal$52[0:0]$1733
+ attribute \src "libresoc.v:48921.7-48921.40"
+ wire $0\core_core_exc_$signal$52[0:0]$2179
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_exc_$signal$53$next[0:0]$1863
+ attribute \src "libresoc.v:50979.3-50980.67"
+ wire $0\core_core_exc_$signal$53[0:0]$1735
+ attribute \src "libresoc.v:48925.7-48925.40"
+ wire $0\core_core_exc_$signal$53[0:0]$2181
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_exc_$signal$54$next[0:0]$1864
+ attribute \src "libresoc.v:50981.3-50982.67"
+ wire $0\core_core_exc_$signal$54[0:0]$1737
+ attribute \src "libresoc.v:48929.7-48929.40"
+ wire $0\core_core_exc_$signal$54[0:0]$2183
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_exc_$signal$55$next[0:0]$1865
+ attribute \src "libresoc.v:50983.3-50984.67"
+ wire $0\core_core_exc_$signal$55[0:0]$1739
+ attribute \src "libresoc.v:48933.7-48933.40"
+ wire $0\core_core_exc_$signal$55[0:0]$2185
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_exc_$signal$56$next[0:0]$1866
+ attribute \src "libresoc.v:50985.3-50986.67"
+ wire $0\core_core_exc_$signal$56[0:0]$1741
+ attribute \src "libresoc.v:48937.7-48937.40"
+ wire $0\core_core_exc_$signal$56[0:0]$2187
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_exc_$signal$next[0:0]$1867
+ attribute \src "libresoc.v:50971.3-50972.61"
+ wire $0\core_core_exc_$signal[0:0]$1727
+ attribute \src "libresoc.v:48911.7-48911.37"
+ wire $0\core_core_exc_$signal[0:0]$2173
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 12 $0\core_core_fn_unit$next[11:0]$1868
+ attribute \src "libresoc.v:50953.3-50954.51"
wire width 12 $0\core_core_fn_unit[11:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 2 $0\core_core_input_carry$next[1:0]$1868
- attribute \src "libresoc.v:50964.3-50965.59"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 2 $0\core_core_input_carry$next[1:0]$1869
+ attribute \src "libresoc.v:50967.3-50968.59"
wire width 2 $0\core_core_input_carry[1:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 32 $0\core_core_insn$next[31:0]$1869
- attribute \src "libresoc.v:50946.3-50947.45"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 32 $0\core_core_insn$next[31:0]$1870
+ attribute \src "libresoc.v:50949.3-50950.45"
wire width 32 $0\core_core_insn[31:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 7 $0\core_core_insn_type$next[6:0]$1870
- attribute \src "libresoc.v:50948.3-50949.55"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 7 $0\core_core_insn_type$next[6:0]$1871
+ attribute \src "libresoc.v:50951.3-50952.55"
wire width 7 $0\core_core_insn_type[6:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_is_32bit$next[0:0]$1871
- attribute \src "libresoc.v:50996.3-50997.53"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_is_32bit$next[0:0]$1872
+ attribute \src "libresoc.v:50999.3-51000.53"
wire $0\core_core_is_32bit[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_lk$next[0:0]$1872
- attribute \src "libresoc.v:50952.3-50953.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_lk$next[0:0]$1873
+ attribute \src "libresoc.v:50955.3-50956.41"
wire $0\core_core_lk[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 64 $0\core_core_msr$next[63:0]$1873
- attribute \src "libresoc.v:50942.3-50943.43"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 64 $0\core_core_msr$next[63:0]$1874
+ attribute \src "libresoc.v:50945.3-50946.43"
wire width 64 $0\core_core_msr[63:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_oe$next[0:0]$1874
- attribute \src "libresoc.v:50958.3-50959.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_oe$next[0:0]$1875
+ attribute \src "libresoc.v:50961.3-50962.41"
wire $0\core_core_oe[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_oe_ok$next[0:0]$1875
- attribute \src "libresoc.v:50960.3-50961.47"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_oe_ok$next[0:0]$1876
+ attribute \src "libresoc.v:50963.3-50964.47"
wire $0\core_core_oe_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_rc$next[0:0]$1876
- attribute \src "libresoc.v:50954.3-50955.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_rc$next[0:0]$1877
+ attribute \src "libresoc.v:50957.3-50958.41"
wire $0\core_core_rc[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_core_rc_ok$next[0:0]$1877
- attribute \src "libresoc.v:50956.3-50957.47"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_core_rc_ok$next[0:0]$1878
+ attribute \src "libresoc.v:50959.3-50960.47"
wire $0\core_core_rc_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 13 $0\core_core_trapaddr$next[12:0]$1878
- attribute \src "libresoc.v:50986.3-50987.53"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 13 $0\core_core_trapaddr$next[12:0]$1879
+ attribute \src "libresoc.v:50989.3-50990.53"
wire width 13 $0\core_core_trapaddr[12:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $0\core_core_traptype$next[7:0]$1879
- attribute \src "libresoc.v:50966.3-50967.53"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $0\core_core_traptype$next[7:0]$1880
+ attribute \src "libresoc.v:50969.3-50970.53"
wire width 8 $0\core_core_traptype[7:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $0\core_cr_in1$next[2:0]$1880
- attribute \src "libresoc.v:50924.3-50925.39"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $0\core_cr_in1$next[2:0]$1881
+ attribute \src "libresoc.v:50927.3-50928.39"
wire width 3 $0\core_cr_in1[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_cr_in1_ok$next[0:0]$1881
- attribute \src "libresoc.v:50926.3-50927.45"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_cr_in1_ok$next[0:0]$1882
+ attribute \src "libresoc.v:50929.3-50930.45"
wire $0\core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $0\core_cr_in2$48$next[2:0]$1882
- attribute \src "libresoc.v:50932.3-50933.47"
- wire width 3 $0\core_cr_in2$48[2:0]$1706
- attribute \src "libresoc.v:49095.13-49095.36"
- wire width 3 $0\core_cr_in2$48[2:0]$2204
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $0\core_cr_in2$next[2:0]$1883
- attribute \src "libresoc.v:50928.3-50929.39"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $0\core_cr_in2$48$next[2:0]$1883
+ attribute \src "libresoc.v:50935.3-50936.47"
+ wire width 3 $0\core_cr_in2$48[2:0]$1707
+ attribute \src "libresoc.v:49098.13-49098.36"
+ wire width 3 $0\core_cr_in2$48[2:0]$2205
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $0\core_cr_in2$next[2:0]$1884
+ attribute \src "libresoc.v:50931.3-50932.39"
wire width 3 $0\core_cr_in2[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_cr_in2_ok$49$next[0:0]$1884
- attribute \src "libresoc.v:50934.3-50935.53"
- wire $0\core_cr_in2_ok$49[0:0]$1708
- attribute \src "libresoc.v:49103.7-49103.33"
- wire $0\core_cr_in2_ok$49[0:0]$2207
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_cr_in2_ok$next[0:0]$1885
- attribute \src "libresoc.v:50930.3-50931.45"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_cr_in2_ok$49$next[0:0]$1885
+ attribute \src "libresoc.v:50937.3-50938.53"
+ wire $0\core_cr_in2_ok$49[0:0]$1709
+ attribute \src "libresoc.v:49106.7-49106.33"
+ wire $0\core_cr_in2_ok$49[0:0]$2208
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_cr_in2_ok$next[0:0]$1886
+ attribute \src "libresoc.v:50933.3-50934.45"
wire $0\core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $0\core_cr_out$next[2:0]$1886
- attribute \src "libresoc.v:50936.3-50937.39"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $0\core_cr_out$next[2:0]$1887
+ attribute \src "libresoc.v:50939.3-50940.39"
wire width 3 $0\core_cr_out[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_cr_out_ok$next[0:0]$1887
- attribute \src "libresoc.v:50938.3-50939.45"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_cr_out_ok$next[0:0]$1888
+ attribute \src "libresoc.v:50941.3-50942.45"
wire $0\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $0\core_dec$next[63:0]$1774
- attribute \src "libresoc.v:50854.3-50855.33"
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $0\core_dec$next[63:0]$1775
+ attribute \src "libresoc.v:50857.3-50858.33"
wire width 64 $0\core_dec[63:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $0\core_ea$next[4:0]$1888
- attribute \src "libresoc.v:50876.3-50877.31"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $0\core_ea$next[4:0]$1889
+ attribute \src "libresoc.v:50879.3-50880.31"
wire width 5 $0\core_ea[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_ea_ok$next[0:0]$1889
- attribute \src "libresoc.v:50878.3-50879.37"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_ea_ok$next[0:0]$1890
+ attribute \src "libresoc.v:50881.3-50882.37"
wire $0\core_ea_ok[0:0]
- attribute \src "libresoc.v:51556.3-51587.6"
- wire $0\core_eint$next[0:0]$1775
- attribute \src "libresoc.v:51022.3-51023.35"
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire $0\core_eint$next[0:0]$1776
+ attribute \src "libresoc.v:51025.3-51026.35"
wire $0\core_eint[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $0\core_fast1$next[2:0]$1890
- attribute \src "libresoc.v:50906.3-50907.37"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $0\core_fast1$next[2:0]$1891
+ attribute \src "libresoc.v:50909.3-50910.37"
wire width 3 $0\core_fast1[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_fast1_ok$next[0:0]$1891
- attribute \src "libresoc.v:50908.3-50909.43"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_fast1_ok$next[0:0]$1892
+ attribute \src "libresoc.v:50911.3-50912.43"
wire $0\core_fast1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $0\core_fast2$next[2:0]$1892
- attribute \src "libresoc.v:50910.3-50911.37"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $0\core_fast2$next[2:0]$1893
+ attribute \src "libresoc.v:50913.3-50914.37"
wire width 3 $0\core_fast2[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_fast2_ok$next[0:0]$1893
- attribute \src "libresoc.v:50912.3-50913.43"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_fast2_ok$next[0:0]$1894
+ attribute \src "libresoc.v:50915.3-50916.43"
wire $0\core_fast2_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $0\core_fasto1$next[2:0]$1894
- attribute \src "libresoc.v:50914.3-50915.39"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $0\core_fasto1$next[2:0]$1895
+ attribute \src "libresoc.v:50917.3-50918.39"
wire width 3 $0\core_fasto1[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_fasto1_ok$next[0:0]$1895
- attribute \src "libresoc.v:50916.3-50917.45"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_fasto1_ok$next[0:0]$1896
+ attribute \src "libresoc.v:50919.3-50920.45"
wire $0\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $0\core_fasto2$next[2:0]$1896
- attribute \src "libresoc.v:50920.3-50921.39"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $0\core_fasto2$next[2:0]$1897
+ attribute \src "libresoc.v:50923.3-50924.39"
wire width 3 $0\core_fasto2[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_fasto2_ok$next[0:0]$1897
- attribute \src "libresoc.v:50922.3-50923.45"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_fasto2_ok$next[0:0]$1898
+ attribute \src "libresoc.v:50925.3-50926.45"
wire $0\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $0\core_msr$next[63:0]$1776
- attribute \src "libresoc.v:51006.3-51007.33"
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $0\core_msr$next[63:0]$1777
+ attribute \src "libresoc.v:51009.3-51010.33"
wire width 64 $0\core_msr[63:0]
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $0\core_pc$next[63:0]$1777
- attribute \src "libresoc.v:50984.3-50985.31"
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $0\core_pc$next[63:0]$1778
+ attribute \src "libresoc.v:50987.3-50988.31"
wire width 64 $0\core_pc[63:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $0\core_reg1$next[4:0]$1898
- attribute \src "libresoc.v:50880.3-50881.35"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $0\core_reg1$next[4:0]$1899
+ attribute \src "libresoc.v:50883.3-50884.35"
wire width 5 $0\core_reg1[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_reg1_ok$next[0:0]$1899
- attribute \src "libresoc.v:50882.3-50883.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_reg1_ok$next[0:0]$1900
+ attribute \src "libresoc.v:50885.3-50886.41"
wire $0\core_reg1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $0\core_reg2$next[4:0]$1900
- attribute \src "libresoc.v:50884.3-50885.35"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $0\core_reg2$next[4:0]$1901
+ attribute \src "libresoc.v:50887.3-50888.35"
wire width 5 $0\core_reg2[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_reg2_ok$next[0:0]$1901
- attribute \src "libresoc.v:50886.3-50887.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_reg2_ok$next[0:0]$1902
+ attribute \src "libresoc.v:50889.3-50890.41"
wire $0\core_reg2_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $0\core_reg3$next[4:0]$1902
- attribute \src "libresoc.v:50888.3-50889.35"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $0\core_reg3$next[4:0]$1903
+ attribute \src "libresoc.v:50891.3-50892.35"
wire width 5 $0\core_reg3[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_reg3_ok$next[0:0]$1903
- attribute \src "libresoc.v:50890.3-50891.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_reg3_ok$next[0:0]$1904
+ attribute \src "libresoc.v:50893.3-50894.41"
wire $0\core_reg3_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $0\core_rego$next[4:0]$1904
- attribute \src "libresoc.v:50870.3-50871.35"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $0\core_rego$next[4:0]$1905
+ attribute \src "libresoc.v:50873.3-50874.35"
wire width 5 $0\core_rego[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_rego_ok$next[0:0]$1905
- attribute \src "libresoc.v:50872.3-50873.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_rego_ok$next[0:0]$1906
+ attribute \src "libresoc.v:50875.3-50876.41"
wire $0\core_rego_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 10 $0\core_spr1$next[9:0]$1906
- attribute \src "libresoc.v:50898.3-50899.35"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 10 $0\core_spr1$next[9:0]$1907
+ attribute \src "libresoc.v:50901.3-50902.35"
wire width 10 $0\core_spr1[9:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_spr1_ok$next[0:0]$1907
- attribute \src "libresoc.v:50900.3-50901.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_spr1_ok$next[0:0]$1908
+ attribute \src "libresoc.v:50903.3-50904.41"
wire $0\core_spr1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 10 $0\core_spro$next[9:0]$1908
- attribute \src "libresoc.v:50892.3-50893.35"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 10 $0\core_spro$next[9:0]$1909
+ attribute \src "libresoc.v:50895.3-50896.35"
wire width 10 $0\core_spro[9:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_spro_ok$next[0:0]$1909
- attribute \src "libresoc.v:50894.3-50895.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_spro_ok$next[0:0]$1910
+ attribute \src "libresoc.v:50897.3-50898.41"
wire $0\core_spro_ok[0:0]
- attribute \src "libresoc.v:52447.3-52465.6"
+ attribute \src "libresoc.v:52450.3-52468.6"
wire $0\core_stopped_i[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $0\core_xer_in$next[2:0]$1910
- attribute \src "libresoc.v:50902.3-50903.39"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $0\core_xer_in$next[2:0]$1911
+ attribute \src "libresoc.v:50905.3-50906.39"
wire width 3 $0\core_xer_in[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $0\core_xer_out$next[0:0]$1911
- attribute \src "libresoc.v:50904.3-50905.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $0\core_xer_out$next[0:0]$1912
+ attribute \src "libresoc.v:50907.3-50908.41"
wire $0\core_xer_out[0:0]
- attribute \src "libresoc.v:51002.3-51003.30"
+ attribute \src "libresoc.v:51005.3-51006.30"
wire $0\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:51702.3-51710.6"
- wire $0\d_cr_delay$next[0:0]$1806
- attribute \src "libresoc.v:50918.3-50919.37"
+ attribute \src "libresoc.v:51705.3-51713.6"
+ wire $0\d_cr_delay$next[0:0]$1807
+ attribute \src "libresoc.v:50921.3-50922.37"
wire $0\d_cr_delay[0:0]
- attribute \src "libresoc.v:51663.3-51671.6"
- wire $0\d_reg_delay$next[0:0]$1800
- attribute \src "libresoc.v:50940.3-50941.39"
+ attribute \src "libresoc.v:51666.3-51674.6"
+ wire $0\d_reg_delay$next[0:0]$1801
+ attribute \src "libresoc.v:50943.3-50944.39"
wire $0\d_reg_delay[0:0]
- attribute \src "libresoc.v:51741.3-51749.6"
- wire $0\d_xer_delay$next[0:0]$1812
- attribute \src "libresoc.v:50896.3-50897.39"
+ attribute \src "libresoc.v:51744.3-51752.6"
+ wire $0\d_xer_delay$next[0:0]$1813
+ attribute \src "libresoc.v:50899.3-50900.39"
wire $0\d_xer_delay[0:0]
- attribute \src "libresoc.v:51979.3-51999.6"
+ attribute \src "libresoc.v:51982.3-52002.6"
wire width 64 $0\data_i[63:0]
- attribute \src "libresoc.v:52466.3-52484.6"
+ attribute \src "libresoc.v:52469.3-52487.6"
wire $0\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:51721.3-51730.6"
+ attribute \src "libresoc.v:51724.3-51733.6"
wire $0\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:51711.3-51720.6"
+ attribute \src "libresoc.v:51714.3-51723.6"
wire width 64 $0\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:51682.3-51691.6"
+ attribute \src "libresoc.v:51685.3-51694.6"
wire $0\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:51672.3-51681.6"
+ attribute \src "libresoc.v:51675.3-51684.6"
wire width 64 $0\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:51760.3-51769.6"
+ attribute \src "libresoc.v:51763.3-51772.6"
wire $0\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:51750.3-51759.6"
+ attribute \src "libresoc.v:51753.3-51762.6"
wire width 64 $0\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:51498.3-51506.6"
- wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1762
- attribute \src "libresoc.v:51020.3-51021.45"
+ attribute \src "libresoc.v:51501.3-51509.6"
+ wire width 4 $0\dbg_dmi_addr_i$next[3:0]$1763
+ attribute \src "libresoc.v:51023.3-51024.45"
wire width 4 $0\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:52016.3-52024.6"
- wire width 64 $0\dbg_dmi_din$next[63:0]$1845
- attribute \src "libresoc.v:51014.3-51015.39"
+ attribute \src "libresoc.v:52019.3-52027.6"
+ wire width 64 $0\dbg_dmi_din$next[63:0]$1846
+ attribute \src "libresoc.v:51017.3-51018.39"
wire width 64 $0\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:51507.3-51515.6"
- wire $0\dbg_dmi_req_i$next[0:0]$1765
- attribute \src "libresoc.v:51018.3-51019.43"
+ attribute \src "libresoc.v:51510.3-51518.6"
+ wire $0\dbg_dmi_req_i$next[0:0]$1766
+ attribute \src "libresoc.v:51021.3-51022.43"
wire $0\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:51911.3-51919.6"
- wire $0\dbg_dmi_we_i$next[0:0]$1834
- attribute \src "libresoc.v:51016.3-51017.41"
+ attribute \src "libresoc.v:51914.3-51922.6"
+ wire $0\dbg_dmi_we_i$next[0:0]$1835
+ attribute \src "libresoc.v:51019.3-51020.41"
wire $0\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:51884.3-51899.6"
- wire width 64 $0\dec2_cur_dec$next[63:0]$1829
- attribute \src "libresoc.v:50852.3-50853.41"
+ attribute \src "libresoc.v:51887.3-51902.6"
+ wire width 64 $0\dec2_cur_dec$next[63:0]$1830
+ attribute \src "libresoc.v:50855.3-50856.41"
wire width 64 $0\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:52191.3-52199.6"
- wire $0\dec2_cur_eint$next[0:0]$2123
- attribute \src "libresoc.v:51008.3-51009.43"
+ attribute \src "libresoc.v:52194.3-52202.6"
+ wire $0\dec2_cur_eint$next[0:0]$2124
+ attribute \src "libresoc.v:51011.3-51012.43"
wire $0\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:51516.3-51536.6"
- wire width 64 $0\dec2_cur_msr$next[63:0]$1768
- attribute \src "libresoc.v:50856.3-50857.41"
+ attribute \src "libresoc.v:51519.3-51539.6"
+ wire width 64 $0\dec2_cur_msr$next[63:0]$1769
+ attribute \src "libresoc.v:50859.3-50860.41"
wire width 64 $0\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:52350.3-52370.6"
- wire width 64 $0\dec2_cur_pc$next[63:0]$2144
- attribute \src "libresoc.v:50862.3-50863.39"
+ attribute \src "libresoc.v:52353.3-52373.6"
+ wire width 64 $0\dec2_cur_pc$next[63:0]$2145
+ attribute \src "libresoc.v:50865.3-50866.39"
wire width 64 $0\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:51537.3-51555.6"
+ attribute \src "libresoc.v:51540.3-51558.6"
wire width 32 $0\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:52200.3-52209.6"
- wire width 2 $0\delay$next[1:0]$2126
- attribute \src "libresoc.v:51004.3-51005.27"
+ attribute \src "libresoc.v:52203.3-52212.6"
+ wire width 2 $0\delay$next[1:0]$2127
+ attribute \src "libresoc.v:51007.3-51008.27"
wire width 2 $0\delay[1:0]
- attribute \src "libresoc.v:51643.3-51652.6"
+ attribute \src "libresoc.v:51646.3-51655.6"
wire width 5 $0\dmi__addr[4:0]
- attribute \src "libresoc.v:51653.3-51662.6"
+ attribute \src "libresoc.v:51656.3-51665.6"
wire $0\dmi__ren[0:0]
- attribute \src "libresoc.v:51800.3-51827.6"
- wire width 2 $0\fsm_state$131$next[1:0]$1819
- attribute \src "libresoc.v:50874.3-50875.45"
- wire width 2 $0\fsm_state$131[1:0]$1676
- attribute \src "libresoc.v:50014.13-50014.35"
- wire width 2 $0\fsm_state$131[1:0]$2253
- attribute \src "libresoc.v:52401.3-52446.6"
- wire width 2 $0\fsm_state$next[1:0]$2155
- attribute \src "libresoc.v:50858.3-50859.35"
+ attribute \src "libresoc.v:51803.3-51830.6"
+ wire width 2 $0\fsm_state$131$next[1:0]$1820
+ attribute \src "libresoc.v:50877.3-50878.45"
+ wire width 2 $0\fsm_state$131[1:0]$1677
+ attribute \src "libresoc.v:50017.13-50017.35"
+ wire width 2 $0\fsm_state$131[1:0]$2254
+ attribute \src "libresoc.v:52404.3-52449.6"
+ wire width 2 $0\fsm_state$next[1:0]$2156
+ attribute \src "libresoc.v:50861.3-50862.35"
wire width 2 $0\fsm_state[1:0]
- attribute \src "libresoc.v:51692.3-51701.6"
+ attribute \src "libresoc.v:51695.3-51704.6"
wire width 8 $0\full_rd2__ren[7:0]
- attribute \src "libresoc.v:51731.3-51740.6"
+ attribute \src "libresoc.v:51734.3-51743.6"
wire width 3 $0\full_rd__ren[2:0]
- attribute \src "libresoc.v:51588.3-51611.6"
- wire width 32 $0\ilatch$next[31:0]$1791
- attribute \src "libresoc.v:50962.3-50963.29"
+ attribute \src "libresoc.v:51591.3-51614.6"
+ wire width 32 $0\ilatch$next[31:0]$1792
+ attribute \src "libresoc.v:50965.3-50966.29"
wire width 32 $0\ilatch[31:0]
- attribute \src "libresoc.v:52284.3-52299.6"
+ attribute \src "libresoc.v:52287.3-52302.6"
wire width 48 $0\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:52300.3-52324.6"
+ attribute \src "libresoc.v:52303.3-52327.6"
wire $0\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52325.3-52349.6"
+ attribute \src "libresoc.v:52328.3-52352.6"
wire $0\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:48738.7-48738.20"
+ attribute \src "libresoc.v:48741.7-48741.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:51839.3-51853.6"
- wire width 3 $0\issue__addr$135[2:0]$1824
- attribute \src "libresoc.v:51770.3-51784.6"
+ attribute \src "libresoc.v:51842.3-51856.6"
+ wire width 3 $0\issue__addr$135[2:0]$1825
+ attribute \src "libresoc.v:51773.3-51787.6"
wire width 3 $0\issue__addr[2:0]
- attribute \src "libresoc.v:51869.3-51883.6"
+ attribute \src "libresoc.v:51872.3-51886.6"
wire width 64 $0\issue__data_i[63:0]
- attribute \src "libresoc.v:51785.3-51799.6"
+ attribute \src "libresoc.v:51788.3-51802.6"
wire $0\issue__ren[0:0]
- attribute \src "libresoc.v:51854.3-51868.6"
+ attribute \src "libresoc.v:51857.3-51871.6"
wire $0\issue__wen[0:0]
- attribute \src "libresoc.v:51632.3-51642.6"
+ attribute \src "libresoc.v:51635.3-51645.6"
wire $0\issue_i[0:0]
- attribute \src "libresoc.v:51612.3-51631.6"
+ attribute \src "libresoc.v:51615.3-51634.6"
wire $0\ivalid_i[0:0]
- attribute \src "libresoc.v:52173.3-52181.6"
- wire $0\jtag_dmi0__ack_o$next[0:0]$2117
- attribute \src "libresoc.v:51012.3-51013.49"
+ attribute \src "libresoc.v:52176.3-52184.6"
+ wire $0\jtag_dmi0__ack_o$next[0:0]$2118
+ attribute \src "libresoc.v:51015.3-51016.49"
wire $0\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:52182.3-52190.6"
- wire width 64 $0\jtag_dmi0__dout$next[63:0]$2120
- attribute \src "libresoc.v:51010.3-51011.47"
+ attribute \src "libresoc.v:52185.3-52193.6"
+ wire width 64 $0\jtag_dmi0__dout$next[63:0]$2121
+ attribute \src "libresoc.v:51013.3-51014.47"
wire width 64 $0\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:52000.3-52015.6"
+ attribute \src "libresoc.v:52003.3-52018.6"
wire width 4 $0\msr__ren[3:0]
- attribute \src "libresoc.v:52371.3-52400.6"
- wire $0\msr_read$next[0:0]$2149
- attribute \src "libresoc.v:50860.3-50861.33"
+ attribute \src "libresoc.v:52374.3-52403.6"
+ wire $0\msr_read$next[0:0]$2150
+ attribute \src "libresoc.v:50863.3-50864.33"
wire $0\msr_read[0:0]
- attribute \src "libresoc.v:51828.3-51838.6"
+ attribute \src "libresoc.v:51831.3-51841.6"
wire width 64 $0\new_dec[63:0]
- attribute \src "libresoc.v:51900.3-51910.6"
+ attribute \src "libresoc.v:51903.3-51913.6"
wire width 64 $0\new_tb[63:0]
- attribute \src "libresoc.v:51929.3-51944.6"
+ attribute \src "libresoc.v:51932.3-51947.6"
wire width 64 $0\pc[63:0]
- attribute \src "libresoc.v:52025.3-52049.6"
- wire $0\pc_changed$next[0:0]$1848
- attribute \src "libresoc.v:50998.3-50999.37"
+ attribute \src "libresoc.v:52028.3-52052.6"
+ wire $0\pc_changed$next[0:0]$1849
+ attribute \src "libresoc.v:51001.3-51002.37"
wire $0\pc_changed[0:0]
- attribute \src "libresoc.v:51920.3-51928.6"
- wire $0\pc_ok_delay$next[0:0]$1837
- attribute \src "libresoc.v:51000.3-51001.39"
+ attribute \src "libresoc.v:51923.3-51931.6"
+ wire $0\pc_ok_delay$next[0:0]$1838
+ attribute \src "libresoc.v:51003.3-51004.39"
wire $0\pc_ok_delay[0:0]
- attribute \src "libresoc.v:52210.3-52246.6"
- wire width 32 $0\raw_insn_i$next[31:0]$2129
- attribute \src "libresoc.v:50866.3-50867.37"
+ attribute \src "libresoc.v:52213.3-52249.6"
+ wire width 32 $0\raw_insn_i$next[31:0]$2130
+ attribute \src "libresoc.v:50869.3-50870.37"
wire width 32 $0\raw_insn_i[31:0]
- attribute \src "libresoc.v:51958.3-51978.6"
+ attribute \src "libresoc.v:51961.3-51981.6"
wire width 4 $0\wen[3:0]
- attribute \src "libresoc.v:52247.3-52283.6"
- wire $1\bigendian_i$next[0:0]$2136
- attribute \src "libresoc.v:48870.7-48870.25"
+ attribute \src "libresoc.v:52250.3-52286.6"
+ wire $1\bigendian_i$next[0:0]$2137
+ attribute \src "libresoc.v:48873.7-48873.25"
wire $1\bigendian_i[0:0]
- attribute \src "libresoc.v:51945.3-51957.6"
+ attribute \src "libresoc.v:51948.3-51960.6"
wire width 4 $1\cia__ren[3:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $1\core_asmcode$next[7:0]$1912
- attribute \src "libresoc.v:48882.13-48882.33"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $1\core_asmcode$next[7:0]$1913
+ attribute \src "libresoc.v:48885.13-48885.33"
wire width 8 $1\core_asmcode[7:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 64 $1\core_core_cia$next[63:0]$1913
- attribute \src "libresoc.v:48888.14-48888.50"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 64 $1\core_core_cia$next[63:0]$1914
+ attribute \src "libresoc.v:48891.14-48891.50"
wire width 64 $1\core_core_cia[63:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $1\core_core_cr_rd$next[7:0]$1914
- attribute \src "libresoc.v:48892.13-48892.36"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $1\core_core_cr_rd$next[7:0]$1915
+ attribute \src "libresoc.v:48895.13-48895.36"
wire width 8 $1\core_core_cr_rd[7:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_cr_rd_ok$next[0:0]$1915
- attribute \src "libresoc.v:48896.7-48896.32"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_cr_rd_ok$next[0:0]$1916
+ attribute \src "libresoc.v:48899.7-48899.32"
wire $1\core_core_cr_rd_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $1\core_core_cr_wr$next[7:0]$1916
- attribute \src "libresoc.v:48900.13-48900.36"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $1\core_core_cr_wr$next[7:0]$1917
+ attribute \src "libresoc.v:48903.13-48903.36"
wire width 8 $1\core_core_cr_wr[7:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_cr_wr_ok$next[0:0]$1917
- attribute \src "libresoc.v:48904.7-48904.32"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_cr_wr_ok$next[0:0]$1918
+ attribute \src "libresoc.v:48907.7-48907.32"
wire $1\core_core_cr_wr_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_exc_$signal$50$next[0:0]$1918
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_exc_$signal$51$next[0:0]$1919
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_exc_$signal$52$next[0:0]$1920
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_exc_$signal$53$next[0:0]$1921
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_exc_$signal$54$next[0:0]$1922
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_exc_$signal$55$next[0:0]$1923
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_exc_$signal$56$next[0:0]$1924
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_exc_$signal$next[0:0]$1925
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 12 $1\core_core_fn_unit$next[11:0]$1926
- attribute \src "libresoc.v:48953.14-48953.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_exc_$signal$50$next[0:0]$1919
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_exc_$signal$51$next[0:0]$1920
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_exc_$signal$52$next[0:0]$1921
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_exc_$signal$53$next[0:0]$1922
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_exc_$signal$54$next[0:0]$1923
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_exc_$signal$55$next[0:0]$1924
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_exc_$signal$56$next[0:0]$1925
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_exc_$signal$next[0:0]$1926
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 12 $1\core_core_fn_unit$next[11:0]$1927
+ attribute \src "libresoc.v:48956.14-48956.41"
wire width 12 $1\core_core_fn_unit[11:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 2 $1\core_core_input_carry$next[1:0]$1927
- attribute \src "libresoc.v:48961.13-48961.41"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 2 $1\core_core_input_carry$next[1:0]$1928
+ attribute \src "libresoc.v:48964.13-48964.41"
wire width 2 $1\core_core_input_carry[1:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 32 $1\core_core_insn$next[31:0]$1928
- attribute \src "libresoc.v:48965.14-48965.36"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 32 $1\core_core_insn$next[31:0]$1929
+ attribute \src "libresoc.v:48968.14-48968.36"
wire width 32 $1\core_core_insn[31:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 7 $1\core_core_insn_type$next[6:0]$1929
- attribute \src "libresoc.v:49043.13-49043.40"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 7 $1\core_core_insn_type$next[6:0]$1930
+ attribute \src "libresoc.v:49046.13-49046.40"
wire width 7 $1\core_core_insn_type[6:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_is_32bit$next[0:0]$1930
- attribute \src "libresoc.v:49047.7-49047.32"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_is_32bit$next[0:0]$1931
+ attribute \src "libresoc.v:49050.7-49050.32"
wire $1\core_core_is_32bit[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_lk$next[0:0]$1931
- attribute \src "libresoc.v:49051.7-49051.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_lk$next[0:0]$1932
+ attribute \src "libresoc.v:49054.7-49054.26"
wire $1\core_core_lk[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 64 $1\core_core_msr$next[63:0]$1932
- attribute \src "libresoc.v:49055.14-49055.50"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 64 $1\core_core_msr$next[63:0]$1933
+ attribute \src "libresoc.v:49058.14-49058.50"
wire width 64 $1\core_core_msr[63:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_oe$next[0:0]$1933
- attribute \src "libresoc.v:49059.7-49059.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_oe$next[0:0]$1934
+ attribute \src "libresoc.v:49062.7-49062.26"
wire $1\core_core_oe[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_oe_ok$next[0:0]$1934
- attribute \src "libresoc.v:49063.7-49063.29"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_oe_ok$next[0:0]$1935
+ attribute \src "libresoc.v:49066.7-49066.29"
wire $1\core_core_oe_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_rc$next[0:0]$1935
- attribute \src "libresoc.v:49067.7-49067.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_rc$next[0:0]$1936
+ attribute \src "libresoc.v:49070.7-49070.26"
wire $1\core_core_rc[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_core_rc_ok$next[0:0]$1936
- attribute \src "libresoc.v:49071.7-49071.29"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_core_rc_ok$next[0:0]$1937
+ attribute \src "libresoc.v:49074.7-49074.29"
wire $1\core_core_rc_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 13 $1\core_core_trapaddr$next[12:0]$1937
- attribute \src "libresoc.v:49075.14-49075.43"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 13 $1\core_core_trapaddr$next[12:0]$1938
+ attribute \src "libresoc.v:49078.14-49078.43"
wire width 13 $1\core_core_trapaddr[12:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $1\core_core_traptype$next[7:0]$1938
- attribute \src "libresoc.v:49079.13-49079.39"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $1\core_core_traptype$next[7:0]$1939
+ attribute \src "libresoc.v:49082.13-49082.39"
wire width 8 $1\core_core_traptype[7:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $1\core_cr_in1$next[2:0]$1939
- attribute \src "libresoc.v:49085.13-49085.31"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $1\core_cr_in1$next[2:0]$1940
+ attribute \src "libresoc.v:49088.13-49088.31"
wire width 3 $1\core_cr_in1[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_cr_in1_ok$next[0:0]$1940
- attribute \src "libresoc.v:49089.7-49089.28"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_cr_in1_ok$next[0:0]$1941
+ attribute \src "libresoc.v:49092.7-49092.28"
wire $1\core_cr_in1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $1\core_cr_in2$48$next[2:0]$1941
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $1\core_cr_in2$next[2:0]$1942
- attribute \src "libresoc.v:49093.13-49093.31"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $1\core_cr_in2$48$next[2:0]$1942
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $1\core_cr_in2$next[2:0]$1943
+ attribute \src "libresoc.v:49096.13-49096.31"
wire width 3 $1\core_cr_in2[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_cr_in2_ok$49$next[0:0]$1943
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_cr_in2_ok$next[0:0]$1944
- attribute \src "libresoc.v:49101.7-49101.28"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_cr_in2_ok$49$next[0:0]$1944
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_cr_in2_ok$next[0:0]$1945
+ attribute \src "libresoc.v:49104.7-49104.28"
wire $1\core_cr_in2_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $1\core_cr_out$next[2:0]$1945
- attribute \src "libresoc.v:49109.13-49109.31"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $1\core_cr_out$next[2:0]$1946
+ attribute \src "libresoc.v:49112.13-49112.31"
wire width 3 $1\core_cr_out[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_cr_out_ok$next[0:0]$1946
- attribute \src "libresoc.v:49113.7-49113.28"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_cr_out_ok$next[0:0]$1947
+ attribute \src "libresoc.v:49116.7-49116.28"
wire $1\core_cr_out_ok[0:0]
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $1\core_dec$next[63:0]$1778
- attribute \src "libresoc.v:49117.14-49117.45"
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $1\core_dec$next[63:0]$1779
+ attribute \src "libresoc.v:49120.14-49120.45"
wire width 64 $1\core_dec[63:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $1\core_ea$next[4:0]$1947
- attribute \src "libresoc.v:49121.13-49121.28"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $1\core_ea$next[4:0]$1948
+ attribute \src "libresoc.v:49124.13-49124.28"
wire width 5 $1\core_ea[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_ea_ok$next[0:0]$1948
- attribute \src "libresoc.v:49125.7-49125.24"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_ea_ok$next[0:0]$1949
+ attribute \src "libresoc.v:49128.7-49128.24"
wire $1\core_ea_ok[0:0]
- attribute \src "libresoc.v:51556.3-51587.6"
- wire $1\core_eint$next[0:0]$1779
- attribute \src "libresoc.v:49129.7-49129.23"
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire $1\core_eint$next[0:0]$1780
+ attribute \src "libresoc.v:49132.7-49132.23"
wire $1\core_eint[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $1\core_fast1$next[2:0]$1949
- attribute \src "libresoc.v:49133.13-49133.30"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $1\core_fast1$next[2:0]$1950
+ attribute \src "libresoc.v:49136.13-49136.30"
wire width 3 $1\core_fast1[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_fast1_ok$next[0:0]$1950
- attribute \src "libresoc.v:49137.7-49137.27"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_fast1_ok$next[0:0]$1951
+ attribute \src "libresoc.v:49140.7-49140.27"
wire $1\core_fast1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $1\core_fast2$next[2:0]$1951
- attribute \src "libresoc.v:49141.13-49141.30"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $1\core_fast2$next[2:0]$1952
+ attribute \src "libresoc.v:49144.13-49144.30"
wire width 3 $1\core_fast2[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_fast2_ok$next[0:0]$1952
- attribute \src "libresoc.v:49145.7-49145.27"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_fast2_ok$next[0:0]$1953
+ attribute \src "libresoc.v:49148.7-49148.27"
wire $1\core_fast2_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $1\core_fasto1$next[2:0]$1953
- attribute \src "libresoc.v:49149.13-49149.31"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $1\core_fasto1$next[2:0]$1954
+ attribute \src "libresoc.v:49152.13-49152.31"
wire width 3 $1\core_fasto1[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_fasto1_ok$next[0:0]$1954
- attribute \src "libresoc.v:49153.7-49153.28"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_fasto1_ok$next[0:0]$1955
+ attribute \src "libresoc.v:49156.7-49156.28"
wire $1\core_fasto1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $1\core_fasto2$next[2:0]$1955
- attribute \src "libresoc.v:49157.13-49157.31"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $1\core_fasto2$next[2:0]$1956
+ attribute \src "libresoc.v:49160.13-49160.31"
wire width 3 $1\core_fasto2[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_fasto2_ok$next[0:0]$1956
- attribute \src "libresoc.v:49161.7-49161.28"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_fasto2_ok$next[0:0]$1957
+ attribute \src "libresoc.v:49164.7-49164.28"
wire $1\core_fasto2_ok[0:0]
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $1\core_msr$next[63:0]$1780
- attribute \src "libresoc.v:49165.14-49165.45"
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $1\core_msr$next[63:0]$1781
+ attribute \src "libresoc.v:49168.14-49168.45"
wire width 64 $1\core_msr[63:0]
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $1\core_pc$next[63:0]$1781
- attribute \src "libresoc.v:49169.14-49169.44"
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $1\core_pc$next[63:0]$1782
+ attribute \src "libresoc.v:49172.14-49172.44"
wire width 64 $1\core_pc[63:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $1\core_reg1$next[4:0]$1957
- attribute \src "libresoc.v:49173.13-49173.30"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $1\core_reg1$next[4:0]$1958
+ attribute \src "libresoc.v:49176.13-49176.30"
wire width 5 $1\core_reg1[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_reg1_ok$next[0:0]$1958
- attribute \src "libresoc.v:49177.7-49177.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_reg1_ok$next[0:0]$1959
+ attribute \src "libresoc.v:49180.7-49180.26"
wire $1\core_reg1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $1\core_reg2$next[4:0]$1959
- attribute \src "libresoc.v:49181.13-49181.30"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $1\core_reg2$next[4:0]$1960
+ attribute \src "libresoc.v:49184.13-49184.30"
wire width 5 $1\core_reg2[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_reg2_ok$next[0:0]$1960
- attribute \src "libresoc.v:49185.7-49185.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_reg2_ok$next[0:0]$1961
+ attribute \src "libresoc.v:49188.7-49188.26"
wire $1\core_reg2_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $1\core_reg3$next[4:0]$1961
- attribute \src "libresoc.v:49189.13-49189.30"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $1\core_reg3$next[4:0]$1962
+ attribute \src "libresoc.v:49192.13-49192.30"
wire width 5 $1\core_reg3[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_reg3_ok$next[0:0]$1962
- attribute \src "libresoc.v:49193.7-49193.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_reg3_ok$next[0:0]$1963
+ attribute \src "libresoc.v:49196.7-49196.26"
wire $1\core_reg3_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $1\core_rego$next[4:0]$1963
- attribute \src "libresoc.v:49197.13-49197.30"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $1\core_rego$next[4:0]$1964
+ attribute \src "libresoc.v:49200.13-49200.30"
wire width 5 $1\core_rego[4:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_rego_ok$next[0:0]$1964
- attribute \src "libresoc.v:49201.7-49201.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_rego_ok$next[0:0]$1965
+ attribute \src "libresoc.v:49204.7-49204.26"
wire $1\core_rego_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 10 $1\core_spr1$next[9:0]$1965
- attribute \src "libresoc.v:49316.13-49316.32"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 10 $1\core_spr1$next[9:0]$1966
+ attribute \src "libresoc.v:49319.13-49319.32"
wire width 10 $1\core_spr1[9:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_spr1_ok$next[0:0]$1966
- attribute \src "libresoc.v:49320.7-49320.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_spr1_ok$next[0:0]$1967
+ attribute \src "libresoc.v:49323.7-49323.26"
wire $1\core_spr1_ok[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 10 $1\core_spro$next[9:0]$1967
- attribute \src "libresoc.v:49435.13-49435.32"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 10 $1\core_spro$next[9:0]$1968
+ attribute \src "libresoc.v:49438.13-49438.32"
wire width 10 $1\core_spro[9:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_spro_ok$next[0:0]$1968
- attribute \src "libresoc.v:49439.7-49439.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_spro_ok$next[0:0]$1969
+ attribute \src "libresoc.v:49442.7-49442.26"
wire $1\core_spro_ok[0:0]
- attribute \src "libresoc.v:52447.3-52465.6"
+ attribute \src "libresoc.v:52450.3-52468.6"
wire $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $1\core_xer_in$next[2:0]$1969
- attribute \src "libresoc.v:49447.13-49447.31"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $1\core_xer_in$next[2:0]$1970
+ attribute \src "libresoc.v:49450.13-49450.31"
wire width 3 $1\core_xer_in[2:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $1\core_xer_out$next[0:0]$1970
- attribute \src "libresoc.v:49451.7-49451.26"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $1\core_xer_out$next[0:0]$1971
+ attribute \src "libresoc.v:49454.7-49454.26"
wire $1\core_xer_out[0:0]
- attribute \src "libresoc.v:49467.7-49467.30"
+ attribute \src "libresoc.v:49470.7-49470.30"
wire $1\cu_st__rel_o_dly[0:0]
- attribute \src "libresoc.v:51702.3-51710.6"
- wire $1\d_cr_delay$next[0:0]$1807
- attribute \src "libresoc.v:49473.7-49473.24"
+ attribute \src "libresoc.v:51705.3-51713.6"
+ wire $1\d_cr_delay$next[0:0]$1808
+ attribute \src "libresoc.v:49476.7-49476.24"
wire $1\d_cr_delay[0:0]
- attribute \src "libresoc.v:51663.3-51671.6"
- wire $1\d_reg_delay$next[0:0]$1801
- attribute \src "libresoc.v:49477.7-49477.25"
+ attribute \src "libresoc.v:51666.3-51674.6"
+ wire $1\d_reg_delay$next[0:0]$1802
+ attribute \src "libresoc.v:49480.7-49480.25"
wire $1\d_reg_delay[0:0]
- attribute \src "libresoc.v:51741.3-51749.6"
- wire $1\d_xer_delay$next[0:0]$1813
- attribute \src "libresoc.v:49481.7-49481.25"
+ attribute \src "libresoc.v:51744.3-51752.6"
+ wire $1\d_xer_delay$next[0:0]$1814
+ attribute \src "libresoc.v:49484.7-49484.25"
wire $1\d_xer_delay[0:0]
- attribute \src "libresoc.v:51979.3-51999.6"
+ attribute \src "libresoc.v:51982.3-52002.6"
wire width 64 $1\data_i[63:0]
- attribute \src "libresoc.v:52466.3-52484.6"
+ attribute \src "libresoc.v:52469.3-52487.6"
wire $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:51721.3-51730.6"
+ attribute \src "libresoc.v:51724.3-51733.6"
wire $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:51711.3-51720.6"
+ attribute \src "libresoc.v:51714.3-51723.6"
wire width 64 $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:51682.3-51691.6"
+ attribute \src "libresoc.v:51685.3-51694.6"
wire $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:51672.3-51681.6"
+ attribute \src "libresoc.v:51675.3-51684.6"
wire width 64 $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:51760.3-51769.6"
+ attribute \src "libresoc.v:51763.3-51772.6"
wire $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:51750.3-51759.6"
+ attribute \src "libresoc.v:51753.3-51762.6"
wire width 64 $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:51498.3-51506.6"
- wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1763
- attribute \src "libresoc.v:49519.13-49519.34"
+ attribute \src "libresoc.v:51501.3-51509.6"
+ wire width 4 $1\dbg_dmi_addr_i$next[3:0]$1764
+ attribute \src "libresoc.v:49522.13-49522.34"
wire width 4 $1\dbg_dmi_addr_i[3:0]
- attribute \src "libresoc.v:52016.3-52024.6"
- wire width 64 $1\dbg_dmi_din$next[63:0]$1846
- attribute \src "libresoc.v:49523.14-49523.48"
+ attribute \src "libresoc.v:52019.3-52027.6"
+ wire width 64 $1\dbg_dmi_din$next[63:0]$1847
+ attribute \src "libresoc.v:49526.14-49526.48"
wire width 64 $1\dbg_dmi_din[63:0]
- attribute \src "libresoc.v:51507.3-51515.6"
- wire $1\dbg_dmi_req_i$next[0:0]$1766
- attribute \src "libresoc.v:49529.7-49529.27"
+ attribute \src "libresoc.v:51510.3-51518.6"
+ wire $1\dbg_dmi_req_i$next[0:0]$1767
+ attribute \src "libresoc.v:49532.7-49532.27"
wire $1\dbg_dmi_req_i[0:0]
- attribute \src "libresoc.v:51911.3-51919.6"
- wire $1\dbg_dmi_we_i$next[0:0]$1835
- attribute \src "libresoc.v:49533.7-49533.26"
+ attribute \src "libresoc.v:51914.3-51922.6"
+ wire $1\dbg_dmi_we_i$next[0:0]$1836
+ attribute \src "libresoc.v:49536.7-49536.26"
wire $1\dbg_dmi_we_i[0:0]
- attribute \src "libresoc.v:51884.3-51899.6"
- wire width 64 $1\dec2_cur_dec$next[63:0]$1830
- attribute \src "libresoc.v:49569.14-49569.49"
+ attribute \src "libresoc.v:51887.3-51902.6"
+ wire width 64 $1\dec2_cur_dec$next[63:0]$1831
+ attribute \src "libresoc.v:49572.14-49572.49"
wire width 64 $1\dec2_cur_dec[63:0]
- attribute \src "libresoc.v:52191.3-52199.6"
- wire $1\dec2_cur_eint$next[0:0]$2124
- attribute \src "libresoc.v:49573.7-49573.27"
+ attribute \src "libresoc.v:52194.3-52202.6"
+ wire $1\dec2_cur_eint$next[0:0]$2125
+ attribute \src "libresoc.v:49576.7-49576.27"
wire $1\dec2_cur_eint[0:0]
- attribute \src "libresoc.v:51516.3-51536.6"
- wire width 64 $1\dec2_cur_msr$next[63:0]$1769
- attribute \src "libresoc.v:49577.14-49577.49"
+ attribute \src "libresoc.v:51519.3-51539.6"
+ wire width 64 $1\dec2_cur_msr$next[63:0]$1770
+ attribute \src "libresoc.v:49580.14-49580.49"
wire width 64 $1\dec2_cur_msr[63:0]
- attribute \src "libresoc.v:52350.3-52370.6"
- wire width 64 $1\dec2_cur_pc$next[63:0]$2145
- attribute \src "libresoc.v:49581.14-49581.48"
+ attribute \src "libresoc.v:52353.3-52373.6"
+ wire width 64 $1\dec2_cur_pc$next[63:0]$2146
+ attribute \src "libresoc.v:49584.14-49584.48"
wire width 64 $1\dec2_cur_pc[63:0]
- attribute \src "libresoc.v:51537.3-51555.6"
+ attribute \src "libresoc.v:51540.3-51558.6"
wire width 32 $1\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:52200.3-52209.6"
- wire width 2 $1\delay$next[1:0]$2127
- attribute \src "libresoc.v:49990.13-49990.25"
+ attribute \src "libresoc.v:52203.3-52212.6"
+ wire width 2 $1\delay$next[1:0]$2128
+ attribute \src "libresoc.v:49993.13-49993.25"
wire width 2 $1\delay[1:0]
- attribute \src "libresoc.v:51643.3-51652.6"
+ attribute \src "libresoc.v:51646.3-51655.6"
wire width 5 $1\dmi__addr[4:0]
- attribute \src "libresoc.v:51653.3-51662.6"
+ attribute \src "libresoc.v:51656.3-51665.6"
wire $1\dmi__ren[0:0]
- attribute \src "libresoc.v:51800.3-51827.6"
- wire width 2 $1\fsm_state$131$next[1:0]$1820
- attribute \src "libresoc.v:52401.3-52446.6"
- wire width 2 $1\fsm_state$next[1:0]$2156
- attribute \src "libresoc.v:50012.13-50012.29"
+ attribute \src "libresoc.v:51803.3-51830.6"
+ wire width 2 $1\fsm_state$131$next[1:0]$1821
+ attribute \src "libresoc.v:52404.3-52449.6"
+ wire width 2 $1\fsm_state$next[1:0]$2157
+ attribute \src "libresoc.v:50015.13-50015.29"
wire width 2 $1\fsm_state[1:0]
- attribute \src "libresoc.v:51692.3-51701.6"
+ attribute \src "libresoc.v:51695.3-51704.6"
wire width 8 $1\full_rd2__ren[7:0]
- attribute \src "libresoc.v:51731.3-51740.6"
+ attribute \src "libresoc.v:51734.3-51743.6"
wire width 3 $1\full_rd__ren[2:0]
- attribute \src "libresoc.v:51588.3-51611.6"
- wire width 32 $1\ilatch$next[31:0]$1792
- attribute \src "libresoc.v:50264.14-50264.28"
+ attribute \src "libresoc.v:51591.3-51614.6"
+ wire width 32 $1\ilatch$next[31:0]$1793
+ attribute \src "libresoc.v:50267.14-50267.28"
wire width 32 $1\ilatch[31:0]
- attribute \src "libresoc.v:52284.3-52299.6"
+ attribute \src "libresoc.v:52287.3-52302.6"
wire width 48 $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:52300.3-52324.6"
+ attribute \src "libresoc.v:52303.3-52327.6"
wire $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52325.3-52349.6"
+ attribute \src "libresoc.v:52328.3-52352.6"
wire $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:51839.3-51853.6"
- wire width 3 $1\issue__addr$135[2:0]$1825
- attribute \src "libresoc.v:51770.3-51784.6"
+ attribute \src "libresoc.v:51842.3-51856.6"
+ wire width 3 $1\issue__addr$135[2:0]$1826
+ attribute \src "libresoc.v:51773.3-51787.6"
wire width 3 $1\issue__addr[2:0]
- attribute \src "libresoc.v:51869.3-51883.6"
+ attribute \src "libresoc.v:51872.3-51886.6"
wire width 64 $1\issue__data_i[63:0]
- attribute \src "libresoc.v:51785.3-51799.6"
+ attribute \src "libresoc.v:51788.3-51802.6"
wire $1\issue__ren[0:0]
- attribute \src "libresoc.v:51854.3-51868.6"
+ attribute \src "libresoc.v:51857.3-51871.6"
wire $1\issue__wen[0:0]
- attribute \src "libresoc.v:51632.3-51642.6"
+ attribute \src "libresoc.v:51635.3-51645.6"
wire $1\issue_i[0:0]
- attribute \src "libresoc.v:51612.3-51631.6"
+ attribute \src "libresoc.v:51615.3-51634.6"
wire $1\ivalid_i[0:0]
- attribute \src "libresoc.v:52173.3-52181.6"
- wire $1\jtag_dmi0__ack_o$next[0:0]$2118
- attribute \src "libresoc.v:50298.7-50298.30"
+ attribute \src "libresoc.v:52176.3-52184.6"
+ wire $1\jtag_dmi0__ack_o$next[0:0]$2119
+ attribute \src "libresoc.v:50301.7-50301.30"
wire $1\jtag_dmi0__ack_o[0:0]
- attribute \src "libresoc.v:52182.3-52190.6"
- wire width 64 $1\jtag_dmi0__dout$next[63:0]$2121
- attribute \src "libresoc.v:50306.14-50306.52"
+ attribute \src "libresoc.v:52185.3-52193.6"
+ wire width 64 $1\jtag_dmi0__dout$next[63:0]$2122
+ attribute \src "libresoc.v:50309.14-50309.52"
wire width 64 $1\jtag_dmi0__dout[63:0]
- attribute \src "libresoc.v:52000.3-52015.6"
+ attribute \src "libresoc.v:52003.3-52018.6"
wire width 4 $1\msr__ren[3:0]
- attribute \src "libresoc.v:52371.3-52400.6"
- wire $1\msr_read$next[0:0]$2150
- attribute \src "libresoc.v:50366.7-50366.22"
+ attribute \src "libresoc.v:52374.3-52403.6"
+ wire $1\msr_read$next[0:0]$2151
+ attribute \src "libresoc.v:50369.7-50369.22"
wire $1\msr_read[0:0]
- attribute \src "libresoc.v:51828.3-51838.6"
+ attribute \src "libresoc.v:51831.3-51841.6"
wire width 64 $1\new_dec[63:0]
- attribute \src "libresoc.v:51900.3-51910.6"
+ attribute \src "libresoc.v:51903.3-51913.6"
wire width 64 $1\new_tb[63:0]
- attribute \src "libresoc.v:51929.3-51944.6"
+ attribute \src "libresoc.v:51932.3-51947.6"
wire width 64 $1\pc[63:0]
- attribute \src "libresoc.v:52025.3-52049.6"
- wire $1\pc_changed$next[0:0]$1849
- attribute \src "libresoc.v:50394.7-50394.24"
+ attribute \src "libresoc.v:52028.3-52052.6"
+ wire $1\pc_changed$next[0:0]$1850
+ attribute \src "libresoc.v:50397.7-50397.24"
wire $1\pc_changed[0:0]
- attribute \src "libresoc.v:51920.3-51928.6"
- wire $1\pc_ok_delay$next[0:0]$1838
- attribute \src "libresoc.v:50404.7-50404.25"
+ attribute \src "libresoc.v:51923.3-51931.6"
+ wire $1\pc_ok_delay$next[0:0]$1839
+ attribute \src "libresoc.v:50407.7-50407.25"
wire $1\pc_ok_delay[0:0]
- attribute \src "libresoc.v:52210.3-52246.6"
- wire width 32 $1\raw_insn_i$next[31:0]$2130
- attribute \src "libresoc.v:50418.14-50418.32"
+ attribute \src "libresoc.v:52213.3-52249.6"
+ wire width 32 $1\raw_insn_i$next[31:0]$2131
+ attribute \src "libresoc.v:50421.14-50421.32"
wire width 32 $1\raw_insn_i[31:0]
- attribute \src "libresoc.v:51958.3-51978.6"
+ attribute \src "libresoc.v:51961.3-51981.6"
wire width 4 $1\wen[3:0]
- attribute \src "libresoc.v:52247.3-52283.6"
- wire $2\bigendian_i$next[0:0]$2137
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $2\core_asmcode$next[7:0]$1971
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 64 $2\core_core_cia$next[63:0]$1972
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $2\core_core_cr_rd$next[7:0]$1973
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_cr_rd_ok$next[0:0]$1974
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $2\core_core_cr_wr$next[7:0]$1975
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_cr_wr_ok$next[0:0]$1976
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_exc_$signal$50$next[0:0]$1977
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_exc_$signal$51$next[0:0]$1978
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_exc_$signal$52$next[0:0]$1979
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_exc_$signal$53$next[0:0]$1980
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_exc_$signal$54$next[0:0]$1981
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_exc_$signal$55$next[0:0]$1982
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_exc_$signal$56$next[0:0]$1983
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_exc_$signal$next[0:0]$1984
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 12 $2\core_core_fn_unit$next[11:0]$1985
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 2 $2\core_core_input_carry$next[1:0]$1986
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 32 $2\core_core_insn$next[31:0]$1987
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 7 $2\core_core_insn_type$next[6:0]$1988
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_is_32bit$next[0:0]$1989
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_lk$next[0:0]$1990
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 64 $2\core_core_msr$next[63:0]$1991
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_oe$next[0:0]$1992
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_oe_ok$next[0:0]$1993
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_rc$next[0:0]$1994
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_core_rc_ok$next[0:0]$1995
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 13 $2\core_core_trapaddr$next[12:0]$1996
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $2\core_core_traptype$next[7:0]$1997
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $2\core_cr_in1$next[2:0]$1998
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_cr_in1_ok$next[0:0]$1999
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $2\core_cr_in2$48$next[2:0]$2000
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $2\core_cr_in2$next[2:0]$2001
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_cr_in2_ok$49$next[0:0]$2002
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_cr_in2_ok$next[0:0]$2003
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $2\core_cr_out$next[2:0]$2004
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_cr_out_ok$next[0:0]$2005
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $2\core_dec$next[63:0]$1782
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $2\core_ea$next[4:0]$2006
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_ea_ok$next[0:0]$2007
- attribute \src "libresoc.v:51556.3-51587.6"
- wire $2\core_eint$next[0:0]$1783
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $2\core_fast1$next[2:0]$2008
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_fast1_ok$next[0:0]$2009
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $2\core_fast2$next[2:0]$2010
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_fast2_ok$next[0:0]$2011
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $2\core_fasto1$next[2:0]$2012
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_fasto1_ok$next[0:0]$2013
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $2\core_fasto2$next[2:0]$2014
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_fasto2_ok$next[0:0]$2015
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $2\core_msr$next[63:0]$1784
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $2\core_pc$next[63:0]$1785
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $2\core_reg1$next[4:0]$2016
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_reg1_ok$next[0:0]$2017
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $2\core_reg2$next[4:0]$2018
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_reg2_ok$next[0:0]$2019
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $2\core_reg3$next[4:0]$2020
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_reg3_ok$next[0:0]$2021
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $2\core_rego$next[4:0]$2022
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_rego_ok$next[0:0]$2023
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 10 $2\core_spr1$next[9:0]$2024
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_spr1_ok$next[0:0]$2025
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 10 $2\core_spro$next[9:0]$2026
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_spro_ok$next[0:0]$2027
- attribute \src "libresoc.v:52447.3-52465.6"
+ attribute \src "libresoc.v:52250.3-52286.6"
+ wire $2\bigendian_i$next[0:0]$2138
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $2\core_asmcode$next[7:0]$1972
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 64 $2\core_core_cia$next[63:0]$1973
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $2\core_core_cr_rd$next[7:0]$1974
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_cr_rd_ok$next[0:0]$1975
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $2\core_core_cr_wr$next[7:0]$1976
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_cr_wr_ok$next[0:0]$1977
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_exc_$signal$50$next[0:0]$1978
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_exc_$signal$51$next[0:0]$1979
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_exc_$signal$52$next[0:0]$1980
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_exc_$signal$53$next[0:0]$1981
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_exc_$signal$54$next[0:0]$1982
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_exc_$signal$55$next[0:0]$1983
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_exc_$signal$56$next[0:0]$1984
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_exc_$signal$next[0:0]$1985
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 12 $2\core_core_fn_unit$next[11:0]$1986
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 2 $2\core_core_input_carry$next[1:0]$1987
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 32 $2\core_core_insn$next[31:0]$1988
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 7 $2\core_core_insn_type$next[6:0]$1989
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_is_32bit$next[0:0]$1990
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_lk$next[0:0]$1991
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 64 $2\core_core_msr$next[63:0]$1992
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_oe$next[0:0]$1993
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_oe_ok$next[0:0]$1994
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_rc$next[0:0]$1995
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_core_rc_ok$next[0:0]$1996
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 13 $2\core_core_trapaddr$next[12:0]$1997
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $2\core_core_traptype$next[7:0]$1998
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $2\core_cr_in1$next[2:0]$1999
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_cr_in1_ok$next[0:0]$2000
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $2\core_cr_in2$48$next[2:0]$2001
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $2\core_cr_in2$next[2:0]$2002
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_cr_in2_ok$49$next[0:0]$2003
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_cr_in2_ok$next[0:0]$2004
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $2\core_cr_out$next[2:0]$2005
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_cr_out_ok$next[0:0]$2006
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $2\core_dec$next[63:0]$1783
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $2\core_ea$next[4:0]$2007
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_ea_ok$next[0:0]$2008
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire $2\core_eint$next[0:0]$1784
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $2\core_fast1$next[2:0]$2009
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_fast1_ok$next[0:0]$2010
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $2\core_fast2$next[2:0]$2011
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_fast2_ok$next[0:0]$2012
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $2\core_fasto1$next[2:0]$2013
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_fasto1_ok$next[0:0]$2014
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $2\core_fasto2$next[2:0]$2015
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_fasto2_ok$next[0:0]$2016
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $2\core_msr$next[63:0]$1785
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $2\core_pc$next[63:0]$1786
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $2\core_reg1$next[4:0]$2017
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_reg1_ok$next[0:0]$2018
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $2\core_reg2$next[4:0]$2019
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_reg2_ok$next[0:0]$2020
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $2\core_reg3$next[4:0]$2021
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_reg3_ok$next[0:0]$2022
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $2\core_rego$next[4:0]$2023
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_rego_ok$next[0:0]$2024
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 10 $2\core_spr1$next[9:0]$2025
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_spr1_ok$next[0:0]$2026
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 10 $2\core_spro$next[9:0]$2027
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_spro_ok$next[0:0]$2028
+ attribute \src "libresoc.v:52450.3-52468.6"
wire $2\core_stopped_i[0:0]
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $2\core_xer_in$next[2:0]$2028
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $2\core_xer_out$next[0:0]$2029
- attribute \src "libresoc.v:51979.3-51999.6"
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $2\core_xer_in$next[2:0]$2029
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $2\core_xer_out$next[0:0]$2030
+ attribute \src "libresoc.v:51982.3-52002.6"
wire width 64 $2\data_i[63:0]
- attribute \src "libresoc.v:52466.3-52484.6"
+ attribute \src "libresoc.v:52469.3-52487.6"
wire $2\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:51884.3-51899.6"
- wire width 64 $2\dec2_cur_dec$next[63:0]$1831
- attribute \src "libresoc.v:51516.3-51536.6"
- wire width 64 $2\dec2_cur_msr$next[63:0]$1770
- attribute \src "libresoc.v:52350.3-52370.6"
- wire width 64 $2\dec2_cur_pc$next[63:0]$2146
- attribute \src "libresoc.v:51537.3-51555.6"
+ attribute \src "libresoc.v:51887.3-51902.6"
+ wire width 64 $2\dec2_cur_dec$next[63:0]$1832
+ attribute \src "libresoc.v:51519.3-51539.6"
+ wire width 64 $2\dec2_cur_msr$next[63:0]$1771
+ attribute \src "libresoc.v:52353.3-52373.6"
+ wire width 64 $2\dec2_cur_pc$next[63:0]$2147
+ attribute \src "libresoc.v:51540.3-51558.6"
wire width 32 $2\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:51800.3-51827.6"
- wire width 2 $2\fsm_state$131$next[1:0]$1821
- attribute \src "libresoc.v:52401.3-52446.6"
- wire width 2 $2\fsm_state$next[1:0]$2157
- attribute \src "libresoc.v:51588.3-51611.6"
- wire width 32 $2\ilatch$next[31:0]$1793
- attribute \src "libresoc.v:52284.3-52299.6"
+ attribute \src "libresoc.v:51803.3-51830.6"
+ wire width 2 $2\fsm_state$131$next[1:0]$1822
+ attribute \src "libresoc.v:52404.3-52449.6"
+ wire width 2 $2\fsm_state$next[1:0]$2158
+ attribute \src "libresoc.v:51591.3-51614.6"
+ wire width 32 $2\ilatch$next[31:0]$1794
+ attribute \src "libresoc.v:52287.3-52302.6"
wire width 48 $2\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:52300.3-52324.6"
+ attribute \src "libresoc.v:52303.3-52327.6"
wire $2\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52325.3-52349.6"
+ attribute \src "libresoc.v:52328.3-52352.6"
wire $2\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:51612.3-51631.6"
+ attribute \src "libresoc.v:51615.3-51634.6"
wire $2\ivalid_i[0:0]
- attribute \src "libresoc.v:52000.3-52015.6"
+ attribute \src "libresoc.v:52003.3-52018.6"
wire width 4 $2\msr__ren[3:0]
- attribute \src "libresoc.v:52371.3-52400.6"
- wire $2\msr_read$next[0:0]$2151
- attribute \src "libresoc.v:51929.3-51944.6"
+ attribute \src "libresoc.v:52374.3-52403.6"
+ wire $2\msr_read$next[0:0]$2152
+ attribute \src "libresoc.v:51932.3-51947.6"
wire width 64 $2\pc[63:0]
- attribute \src "libresoc.v:52025.3-52049.6"
- wire $2\pc_changed$next[0:0]$1850
- attribute \src "libresoc.v:52210.3-52246.6"
- wire width 32 $2\raw_insn_i$next[31:0]$2131
- attribute \src "libresoc.v:51958.3-51978.6"
+ attribute \src "libresoc.v:52028.3-52052.6"
+ wire $2\pc_changed$next[0:0]$1851
+ attribute \src "libresoc.v:52213.3-52249.6"
+ wire width 32 $2\raw_insn_i$next[31:0]$2132
+ attribute \src "libresoc.v:51961.3-51981.6"
wire width 4 $2\wen[3:0]
- attribute \src "libresoc.v:52247.3-52283.6"
- wire $3\bigendian_i$next[0:0]$2138
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $3\core_asmcode$next[7:0]$2030
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 64 $3\core_core_cia$next[63:0]$2031
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $3\core_core_cr_rd$next[7:0]$2032
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_cr_rd_ok$next[0:0]$2033
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $3\core_core_cr_wr$next[7:0]$2034
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_cr_wr_ok$next[0:0]$2035
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_exc_$signal$50$next[0:0]$2036
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_exc_$signal$51$next[0:0]$2037
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_exc_$signal$52$next[0:0]$2038
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_exc_$signal$53$next[0:0]$2039
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_exc_$signal$54$next[0:0]$2040
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_exc_$signal$55$next[0:0]$2041
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_exc_$signal$56$next[0:0]$2042
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_exc_$signal$next[0:0]$2043
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 12 $3\core_core_fn_unit$next[11:0]$2044
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 2 $3\core_core_input_carry$next[1:0]$2045
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 32 $3\core_core_insn$next[31:0]$2046
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 7 $3\core_core_insn_type$next[6:0]$2047
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_is_32bit$next[0:0]$2048
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_lk$next[0:0]$2049
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 64 $3\core_core_msr$next[63:0]$2050
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_oe$next[0:0]$2051
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_oe_ok$next[0:0]$2052
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_rc$next[0:0]$2053
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_core_rc_ok$next[0:0]$2054
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 13 $3\core_core_trapaddr$next[12:0]$2055
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 8 $3\core_core_traptype$next[7:0]$2056
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $3\core_cr_in1$next[2:0]$2057
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_cr_in1_ok$next[0:0]$2058
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $3\core_cr_in2$48$next[2:0]$2059
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $3\core_cr_in2$next[2:0]$2060
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_cr_in2_ok$49$next[0:0]$2061
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_cr_in2_ok$next[0:0]$2062
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $3\core_cr_out$next[2:0]$2063
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_cr_out_ok$next[0:0]$2064
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $3\core_dec$next[63:0]$1786
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $3\core_ea$next[4:0]$2065
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_ea_ok$next[0:0]$2066
- attribute \src "libresoc.v:51556.3-51587.6"
- wire $3\core_eint$next[0:0]$1787
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $3\core_fast1$next[2:0]$2067
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_fast1_ok$next[0:0]$2068
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $3\core_fast2$next[2:0]$2069
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_fast2_ok$next[0:0]$2070
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $3\core_fasto1$next[2:0]$2071
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_fasto1_ok$next[0:0]$2072
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $3\core_fasto2$next[2:0]$2073
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_fasto2_ok$next[0:0]$2074
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $3\core_msr$next[63:0]$1788
- attribute \src "libresoc.v:51556.3-51587.6"
- wire width 64 $3\core_pc$next[63:0]$1789
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $3\core_reg1$next[4:0]$2075
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_reg1_ok$next[0:0]$2076
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $3\core_reg2$next[4:0]$2077
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_reg2_ok$next[0:0]$2078
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $3\core_reg3$next[4:0]$2079
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_reg3_ok$next[0:0]$2080
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 5 $3\core_rego$next[4:0]$2081
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_rego_ok$next[0:0]$2082
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 10 $3\core_spr1$next[9:0]$2083
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_spr1_ok$next[0:0]$2084
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 10 $3\core_spro$next[9:0]$2085
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_spro_ok$next[0:0]$2086
- attribute \src "libresoc.v:52050.3-52172.6"
- wire width 3 $3\core_xer_in$next[2:0]$2087
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $3\core_xer_out$next[0:0]$2088
- attribute \src "libresoc.v:51979.3-51999.6"
+ attribute \src "libresoc.v:52250.3-52286.6"
+ wire $3\bigendian_i$next[0:0]$2139
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $3\core_asmcode$next[7:0]$2031
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 64 $3\core_core_cia$next[63:0]$2032
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $3\core_core_cr_rd$next[7:0]$2033
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_cr_rd_ok$next[0:0]$2034
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $3\core_core_cr_wr$next[7:0]$2035
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_cr_wr_ok$next[0:0]$2036
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_exc_$signal$50$next[0:0]$2037
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_exc_$signal$51$next[0:0]$2038
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_exc_$signal$52$next[0:0]$2039
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_exc_$signal$53$next[0:0]$2040
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_exc_$signal$54$next[0:0]$2041
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_exc_$signal$55$next[0:0]$2042
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_exc_$signal$56$next[0:0]$2043
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_exc_$signal$next[0:0]$2044
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 12 $3\core_core_fn_unit$next[11:0]$2045
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 2 $3\core_core_input_carry$next[1:0]$2046
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 32 $3\core_core_insn$next[31:0]$2047
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 7 $3\core_core_insn_type$next[6:0]$2048
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_is_32bit$next[0:0]$2049
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_lk$next[0:0]$2050
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 64 $3\core_core_msr$next[63:0]$2051
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_oe$next[0:0]$2052
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_oe_ok$next[0:0]$2053
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_rc$next[0:0]$2054
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_core_rc_ok$next[0:0]$2055
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 13 $3\core_core_trapaddr$next[12:0]$2056
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 8 $3\core_core_traptype$next[7:0]$2057
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $3\core_cr_in1$next[2:0]$2058
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_cr_in1_ok$next[0:0]$2059
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $3\core_cr_in2$48$next[2:0]$2060
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $3\core_cr_in2$next[2:0]$2061
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_cr_in2_ok$49$next[0:0]$2062
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_cr_in2_ok$next[0:0]$2063
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $3\core_cr_out$next[2:0]$2064
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_cr_out_ok$next[0:0]$2065
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $3\core_dec$next[63:0]$1787
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $3\core_ea$next[4:0]$2066
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_ea_ok$next[0:0]$2067
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire $3\core_eint$next[0:0]$1788
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $3\core_fast1$next[2:0]$2068
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_fast1_ok$next[0:0]$2069
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $3\core_fast2$next[2:0]$2070
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_fast2_ok$next[0:0]$2071
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $3\core_fasto1$next[2:0]$2072
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_fasto1_ok$next[0:0]$2073
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $3\core_fasto2$next[2:0]$2074
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_fasto2_ok$next[0:0]$2075
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $3\core_msr$next[63:0]$1789
+ attribute \src "libresoc.v:51559.3-51590.6"
+ wire width 64 $3\core_pc$next[63:0]$1790
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $3\core_reg1$next[4:0]$2076
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_reg1_ok$next[0:0]$2077
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $3\core_reg2$next[4:0]$2078
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_reg2_ok$next[0:0]$2079
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $3\core_reg3$next[4:0]$2080
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_reg3_ok$next[0:0]$2081
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 5 $3\core_rego$next[4:0]$2082
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_rego_ok$next[0:0]$2083
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 10 $3\core_spr1$next[9:0]$2084
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_spr1_ok$next[0:0]$2085
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 10 $3\core_spro$next[9:0]$2086
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_spro_ok$next[0:0]$2087
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire width 3 $3\core_xer_in$next[2:0]$2088
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $3\core_xer_out$next[0:0]$2089
+ attribute \src "libresoc.v:51982.3-52002.6"
wire width 64 $3\data_i[63:0]
- attribute \src "libresoc.v:51516.3-51536.6"
- wire width 64 $3\dec2_cur_msr$next[63:0]$1771
- attribute \src "libresoc.v:52350.3-52370.6"
- wire width 64 $3\dec2_cur_pc$next[63:0]$2147
- attribute \src "libresoc.v:52401.3-52446.6"
- wire width 2 $3\fsm_state$next[1:0]$2158
- attribute \src "libresoc.v:51588.3-51611.6"
- wire width 32 $3\ilatch$next[31:0]$1794
- attribute \src "libresoc.v:52300.3-52324.6"
+ attribute \src "libresoc.v:51519.3-51539.6"
+ wire width 64 $3\dec2_cur_msr$next[63:0]$1772
+ attribute \src "libresoc.v:52353.3-52373.6"
+ wire width 64 $3\dec2_cur_pc$next[63:0]$2148
+ attribute \src "libresoc.v:52404.3-52449.6"
+ wire width 2 $3\fsm_state$next[1:0]$2159
+ attribute \src "libresoc.v:51591.3-51614.6"
+ wire width 32 $3\ilatch$next[31:0]$1795
+ attribute \src "libresoc.v:52303.3-52327.6"
wire $3\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52325.3-52349.6"
+ attribute \src "libresoc.v:52328.3-52352.6"
wire $3\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:52371.3-52400.6"
- wire $3\msr_read$next[0:0]$2152
- attribute \src "libresoc.v:52025.3-52049.6"
- wire $3\pc_changed$next[0:0]$1851
- attribute \src "libresoc.v:52210.3-52246.6"
- wire width 32 $3\raw_insn_i$next[31:0]$2132
- attribute \src "libresoc.v:51958.3-51978.6"
+ attribute \src "libresoc.v:52374.3-52403.6"
+ wire $3\msr_read$next[0:0]$2153
+ attribute \src "libresoc.v:52028.3-52052.6"
+ wire $3\pc_changed$next[0:0]$1852
+ attribute \src "libresoc.v:52213.3-52249.6"
+ wire width 32 $3\raw_insn_i$next[31:0]$2133
+ attribute \src "libresoc.v:51961.3-51981.6"
wire width 4 $3\wen[3:0]
- attribute \src "libresoc.v:52247.3-52283.6"
- wire $4\bigendian_i$next[0:0]$2139
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_cr_rd_ok$next[0:0]$2089
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_cr_wr_ok$next[0:0]$2090
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_exc_$signal$50$next[0:0]$2091
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_exc_$signal$51$next[0:0]$2092
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_exc_$signal$52$next[0:0]$2093
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_exc_$signal$53$next[0:0]$2094
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_exc_$signal$54$next[0:0]$2095
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_exc_$signal$55$next[0:0]$2096
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_exc_$signal$56$next[0:0]$2097
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_exc_$signal$next[0:0]$2098
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_oe_ok$next[0:0]$2099
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_core_rc_ok$next[0:0]$2100
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_cr_in1_ok$next[0:0]$2101
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_cr_in2_ok$49$next[0:0]$2102
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_cr_in2_ok$next[0:0]$2103
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_cr_out_ok$next[0:0]$2104
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_ea_ok$next[0:0]$2105
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_fast1_ok$next[0:0]$2106
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_fast2_ok$next[0:0]$2107
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_fasto1_ok$next[0:0]$2108
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_fasto2_ok$next[0:0]$2109
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_reg1_ok$next[0:0]$2110
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_reg2_ok$next[0:0]$2111
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_reg3_ok$next[0:0]$2112
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_rego_ok$next[0:0]$2113
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_spr1_ok$next[0:0]$2114
- attribute \src "libresoc.v:52050.3-52172.6"
- wire $4\core_spro_ok$next[0:0]$2115
- attribute \src "libresoc.v:52401.3-52446.6"
- wire width 2 $4\fsm_state$next[1:0]$2159
- attribute \src "libresoc.v:52371.3-52400.6"
- wire $4\msr_read$next[0:0]$2153
- attribute \src "libresoc.v:52210.3-52246.6"
- wire width 32 $4\raw_insn_i$next[31:0]$2133
- attribute \src "libresoc.v:52401.3-52446.6"
- wire width 2 $5\fsm_state$next[1:0]$2160
- attribute \src "libresoc.v:50813.19-50813.110"
- wire width 65 $add$libresoc.v:50813$1625_Y
- attribute \src "libresoc.v:50820.18-50820.107"
- wire width 65 $add$libresoc.v:50820$1632_Y
- attribute \src "libresoc.v:50795.18-50795.101"
- wire $and$libresoc.v:50795$1605_Y
- attribute \src "libresoc.v:50799.19-50799.104"
- wire $and$libresoc.v:50799$1609_Y
- attribute \src "libresoc.v:50803.19-50803.104"
- wire $and$libresoc.v:50803$1613_Y
- attribute \src "libresoc.v:50819.18-50819.104"
- wire $and$libresoc.v:50819$1631_Y
- attribute \src "libresoc.v:50828.18-50828.101"
- wire $and$libresoc.v:50828$1640_Y
- attribute \src "libresoc.v:50829.18-50829.109"
- wire width 4 $and$libresoc.v:50829$1641_Y
- attribute \src "libresoc.v:50836.18-50836.101"
- wire $and$libresoc.v:50836$1648_Y
+ attribute \src "libresoc.v:52250.3-52286.6"
+ wire $4\bigendian_i$next[0:0]$2140
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_cr_rd_ok$next[0:0]$2090
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_cr_wr_ok$next[0:0]$2091
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_exc_$signal$50$next[0:0]$2092
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_exc_$signal$51$next[0:0]$2093
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_exc_$signal$52$next[0:0]$2094
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_exc_$signal$53$next[0:0]$2095
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_exc_$signal$54$next[0:0]$2096
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_exc_$signal$55$next[0:0]$2097
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_exc_$signal$56$next[0:0]$2098
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_exc_$signal$next[0:0]$2099
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_oe_ok$next[0:0]$2100
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_core_rc_ok$next[0:0]$2101
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_cr_in1_ok$next[0:0]$2102
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_cr_in2_ok$49$next[0:0]$2103
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_cr_in2_ok$next[0:0]$2104
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_cr_out_ok$next[0:0]$2105
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_ea_ok$next[0:0]$2106
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_fast1_ok$next[0:0]$2107
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_fast2_ok$next[0:0]$2108
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_fasto1_ok$next[0:0]$2109
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_fasto2_ok$next[0:0]$2110
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_reg1_ok$next[0:0]$2111
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_reg2_ok$next[0:0]$2112
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_reg3_ok$next[0:0]$2113
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_rego_ok$next[0:0]$2114
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_spr1_ok$next[0:0]$2115
+ attribute \src "libresoc.v:52053.3-52175.6"
+ wire $4\core_spro_ok$next[0:0]$2116
+ attribute \src "libresoc.v:52404.3-52449.6"
+ wire width 2 $4\fsm_state$next[1:0]$2160
+ attribute \src "libresoc.v:52374.3-52403.6"
+ wire $4\msr_read$next[0:0]$2154
+ attribute \src "libresoc.v:52213.3-52249.6"
+ wire width 32 $4\raw_insn_i$next[31:0]$2134
+ attribute \src "libresoc.v:52404.3-52449.6"
+ wire width 2 $5\fsm_state$next[1:0]$2161
+ attribute \src "libresoc.v:50816.19-50816.110"
+ wire width 65 $add$libresoc.v:50816$1626_Y
+ attribute \src "libresoc.v:50823.18-50823.107"
+ wire width 65 $add$libresoc.v:50823$1633_Y
+ attribute \src "libresoc.v:50798.18-50798.101"
+ wire $and$libresoc.v:50798$1606_Y
+ attribute \src "libresoc.v:50802.19-50802.104"
+ wire $and$libresoc.v:50802$1610_Y
+ attribute \src "libresoc.v:50806.19-50806.104"
+ wire $and$libresoc.v:50806$1614_Y
+ attribute \src "libresoc.v:50822.18-50822.104"
+ wire $and$libresoc.v:50822$1632_Y
+ attribute \src "libresoc.v:50831.18-50831.101"
+ wire $and$libresoc.v:50831$1641_Y
+ attribute \src "libresoc.v:50832.18-50832.109"
+ wire width 4 $and$libresoc.v:50832$1642_Y
attribute \src "libresoc.v:50839.18-50839.101"
- wire $and$libresoc.v:50839$1651_Y
+ wire $and$libresoc.v:50839$1649_Y
attribute \src "libresoc.v:50842.18-50842.101"
- wire $and$libresoc.v:50842$1654_Y
+ wire $and$libresoc.v:50842$1652_Y
attribute \src "libresoc.v:50845.18-50845.101"
- wire $and$libresoc.v:50845$1657_Y
+ wire $and$libresoc.v:50845$1655_Y
attribute \src "libresoc.v:50848.18-50848.101"
- wire $and$libresoc.v:50848$1660_Y
- attribute \src "libresoc.v:50810.19-50810.109"
- wire width 64 $extend$libresoc.v:50810$1620_Y
- attribute \src "libresoc.v:50811.19-50811.108"
- wire width 64 $extend$libresoc.v:50811$1622_Y
- attribute \src "libresoc.v:50805.19-50805.111"
- wire width 7 $mul$libresoc.v:50805$1615_Y
- attribute \src "libresoc.v:50807.19-50807.111"
- wire width 7 $mul$libresoc.v:50807$1617_Y
- attribute \src "libresoc.v:50800.18-50800.102"
- wire $ne$libresoc.v:50800$1610_Y
- attribute \src "libresoc.v:50809.19-50809.118"
- wire $ne$libresoc.v:50809$1619_Y
- attribute \src "libresoc.v:50817.18-50817.102"
- wire $ne$libresoc.v:50817$1629_Y
- attribute \src "libresoc.v:50796.19-50796.102"
- wire $not$libresoc.v:50796$1606_Y
- attribute \src "libresoc.v:50797.19-50797.107"
- wire $not$libresoc.v:50797$1607_Y
- attribute \src "libresoc.v:50798.19-50798.109"
- wire $not$libresoc.v:50798$1608_Y
- attribute \src "libresoc.v:50801.19-50801.107"
- wire $not$libresoc.v:50801$1611_Y
- attribute \src "libresoc.v:50802.19-50802.109"
- wire $not$libresoc.v:50802$1612_Y
- attribute \src "libresoc.v:50804.19-50804.100"
- wire $not$libresoc.v:50804$1614_Y
- attribute \src "libresoc.v:50818.18-50818.103"
- wire $not$libresoc.v:50818$1630_Y
- attribute \src "libresoc.v:50821.18-50821.98"
- wire $not$libresoc.v:50821$1633_Y
- attribute \src "libresoc.v:50822.18-50822.101"
- wire $not$libresoc.v:50822$1634_Y
- attribute \src "libresoc.v:50823.18-50823.101"
- wire $not$libresoc.v:50823$1635_Y
- attribute \src "libresoc.v:50824.18-50824.101"
- wire $not$libresoc.v:50824$1636_Y
+ wire $and$libresoc.v:50848$1658_Y
+ attribute \src "libresoc.v:50851.18-50851.101"
+ wire $and$libresoc.v:50851$1661_Y
+ attribute \src "libresoc.v:50813.19-50813.109"
+ wire width 64 $extend$libresoc.v:50813$1621_Y
+ attribute \src "libresoc.v:50814.19-50814.108"
+ wire width 64 $extend$libresoc.v:50814$1623_Y
+ attribute \src "libresoc.v:50808.19-50808.111"
+ wire width 7 $mul$libresoc.v:50808$1616_Y
+ attribute \src "libresoc.v:50810.19-50810.111"
+ wire width 7 $mul$libresoc.v:50810$1618_Y
+ attribute \src "libresoc.v:50803.18-50803.102"
+ wire $ne$libresoc.v:50803$1611_Y
+ attribute \src "libresoc.v:50812.19-50812.118"
+ wire $ne$libresoc.v:50812$1620_Y
+ attribute \src "libresoc.v:50820.18-50820.102"
+ wire $ne$libresoc.v:50820$1630_Y
+ attribute \src "libresoc.v:50799.19-50799.102"
+ wire $not$libresoc.v:50799$1607_Y
+ attribute \src "libresoc.v:50800.19-50800.107"
+ wire $not$libresoc.v:50800$1608_Y
+ attribute \src "libresoc.v:50801.19-50801.109"
+ wire $not$libresoc.v:50801$1609_Y
+ attribute \src "libresoc.v:50804.19-50804.107"
+ wire $not$libresoc.v:50804$1612_Y
+ attribute \src "libresoc.v:50805.19-50805.109"
+ wire $not$libresoc.v:50805$1613_Y
+ attribute \src "libresoc.v:50807.19-50807.100"
+ wire $not$libresoc.v:50807$1615_Y
+ attribute \src "libresoc.v:50821.18-50821.103"
+ wire $not$libresoc.v:50821$1631_Y
+ attribute \src "libresoc.v:50824.18-50824.98"
+ wire $not$libresoc.v:50824$1634_Y
attribute \src "libresoc.v:50825.18-50825.101"
- wire $not$libresoc.v:50825$1637_Y
- attribute \src "libresoc.v:50826.18-50826.106"
- wire $not$libresoc.v:50826$1638_Y
- attribute \src "libresoc.v:50827.18-50827.108"
- wire $not$libresoc.v:50827$1639_Y
- attribute \src "libresoc.v:50831.18-50831.101"
- wire $not$libresoc.v:50831$1643_Y
- attribute \src "libresoc.v:50832.18-50832.101"
- wire $not$libresoc.v:50832$1644_Y
- attribute \src "libresoc.v:50833.18-50833.101"
- wire $not$libresoc.v:50833$1645_Y
- attribute \src "libresoc.v:50834.18-50834.106"
- wire $not$libresoc.v:50834$1646_Y
- attribute \src "libresoc.v:50835.18-50835.108"
- wire $not$libresoc.v:50835$1647_Y
+ wire $not$libresoc.v:50825$1635_Y
+ attribute \src "libresoc.v:50826.18-50826.101"
+ wire $not$libresoc.v:50826$1636_Y
+ attribute \src "libresoc.v:50827.18-50827.101"
+ wire $not$libresoc.v:50827$1637_Y
+ attribute \src "libresoc.v:50828.18-50828.101"
+ wire $not$libresoc.v:50828$1638_Y
+ attribute \src "libresoc.v:50829.18-50829.106"
+ wire $not$libresoc.v:50829$1639_Y
+ attribute \src "libresoc.v:50830.18-50830.108"
+ wire $not$libresoc.v:50830$1640_Y
+ attribute \src "libresoc.v:50834.18-50834.101"
+ wire $not$libresoc.v:50834$1644_Y
+ attribute \src "libresoc.v:50835.18-50835.101"
+ wire $not$libresoc.v:50835$1645_Y
+ attribute \src "libresoc.v:50836.18-50836.101"
+ wire $not$libresoc.v:50836$1646_Y
attribute \src "libresoc.v:50837.18-50837.106"
- wire $not$libresoc.v:50837$1649_Y
+ wire $not$libresoc.v:50837$1647_Y
attribute \src "libresoc.v:50838.18-50838.108"
- wire $not$libresoc.v:50838$1650_Y
+ wire $not$libresoc.v:50838$1648_Y
attribute \src "libresoc.v:50840.18-50840.106"
- wire $not$libresoc.v:50840$1652_Y
+ wire $not$libresoc.v:50840$1650_Y
attribute \src "libresoc.v:50841.18-50841.108"
- wire $not$libresoc.v:50841$1653_Y
+ wire $not$libresoc.v:50841$1651_Y
attribute \src "libresoc.v:50843.18-50843.106"
- wire $not$libresoc.v:50843$1655_Y
+ wire $not$libresoc.v:50843$1653_Y
attribute \src "libresoc.v:50844.18-50844.108"
- wire $not$libresoc.v:50844$1656_Y
+ wire $not$libresoc.v:50844$1654_Y
attribute \src "libresoc.v:50846.18-50846.106"
- wire $not$libresoc.v:50846$1658_Y
+ wire $not$libresoc.v:50846$1656_Y
attribute \src "libresoc.v:50847.18-50847.108"
- wire $not$libresoc.v:50847$1659_Y
- attribute \src "libresoc.v:50849.18-50849.99"
- wire $not$libresoc.v:50849$1661_Y
- attribute \src "libresoc.v:50850.18-50850.106"
- wire $not$libresoc.v:50850$1662_Y
- attribute \src "libresoc.v:50851.18-50851.108"
- wire $not$libresoc.v:50851$1663_Y
- attribute \src "libresoc.v:50815.18-50815.110"
- wire $or$libresoc.v:50815$1627_Y
- attribute \src "libresoc.v:50816.18-50816.100"
- wire $or$libresoc.v:50816$1628_Y
- attribute \src "libresoc.v:50810.19-50810.109"
- wire width 64 $pos$libresoc.v:50810$1621_Y
- attribute \src "libresoc.v:50811.19-50811.108"
- wire width 64 $pos$libresoc.v:50811$1623_Y
- attribute \src "libresoc.v:50830.18-50830.91"
- wire $reduce_or$libresoc.v:50830$1642_Y
- attribute \src "libresoc.v:50806.19-50806.42"
- wire width 64 $shr$libresoc.v:50806$1616_Y
- attribute \src "libresoc.v:50808.19-50808.42"
- wire width 64 $shr$libresoc.v:50808$1618_Y
- attribute \src "libresoc.v:50812.19-50812.110"
- wire width 65 $sub$libresoc.v:50812$1624_Y
- attribute \src "libresoc.v:50814.18-50814.101"
- wire width 3 $sub$libresoc.v:50814$1626_Y
+ wire $not$libresoc.v:50847$1657_Y
+ attribute \src "libresoc.v:50849.18-50849.106"
+ wire $not$libresoc.v:50849$1659_Y
+ attribute \src "libresoc.v:50850.18-50850.108"
+ wire $not$libresoc.v:50850$1660_Y
+ attribute \src "libresoc.v:50852.18-50852.99"
+ wire $not$libresoc.v:50852$1662_Y
+ attribute \src "libresoc.v:50853.18-50853.106"
+ wire $not$libresoc.v:50853$1663_Y
+ attribute \src "libresoc.v:50854.18-50854.108"
+ wire $not$libresoc.v:50854$1664_Y
+ attribute \src "libresoc.v:50818.18-50818.110"
+ wire $or$libresoc.v:50818$1628_Y
+ attribute \src "libresoc.v:50819.18-50819.100"
+ wire $or$libresoc.v:50819$1629_Y
+ attribute \src "libresoc.v:50813.19-50813.109"
+ wire width 64 $pos$libresoc.v:50813$1622_Y
+ attribute \src "libresoc.v:50814.19-50814.108"
+ wire width 64 $pos$libresoc.v:50814$1624_Y
+ attribute \src "libresoc.v:50833.18-50833.91"
+ wire $reduce_or$libresoc.v:50833$1643_Y
+ attribute \src "libresoc.v:50809.19-50809.42"
+ wire width 64 $shr$libresoc.v:50809$1617_Y
+ attribute \src "libresoc.v:50811.19-50811.42"
+ wire width 64 $shr$libresoc.v:50811$1619_Y
+ attribute \src "libresoc.v:50815.19-50815.110"
+ wire width 65 $sub$libresoc.v:50815$1625_Y
+ attribute \src "libresoc.v:50817.18-50817.101"
+ wire width 3 $sub$libresoc.v:50817$1627_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174"
wire \$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
wire \imem_f_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92"
wire \imem_wb_icache_en
- attribute \src "libresoc.v:48738.7-48738.15"
+ attribute \src "libresoc.v:48741.7-48741.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 344 \int_level_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 \xics_ics_icp_o_src
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409"
- cell $add $add$libresoc.v:50813$1625
+ cell $add $add$libresoc.v:50816$1626
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \issue__data_o
connect \B 1'1
- connect \Y $add$libresoc.v:50813$1625_Y
+ connect \Y $add$libresoc.v:50816$1626_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201"
- cell $add $add$libresoc.v:50820$1632
+ cell $add $add$libresoc.v:50823$1633
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \dec2_cur_pc
connect \B 3'100
- connect \Y $add$libresoc.v:50820$1632_Y
+ connect \Y $add$libresoc.v:50823$1633_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50795$1605
+ cell $and $and$libresoc.v:50798$1606
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$95
connect \B \$97
- connect \Y $and$libresoc.v:50795$1605_Y
+ connect \Y $and$libresoc.v:50798$1606_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50799$1609
+ cell $and $and$libresoc.v:50802$1610
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$103
connect \B \$105
- connect \Y $and$libresoc.v:50799$1609_Y
+ connect \Y $and$libresoc.v:50802$1610_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50803$1613
+ cell $and $and$libresoc.v:50806$1614
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$109
connect \B \$111
- connect \Y $and$libresoc.v:50803$1613_Y
+ connect \Y $and$libresoc.v:50806$1614_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $and $and$libresoc.v:50819$1631
+ cell $and $and$libresoc.v:50822$1632
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o
connect \B \$21
- connect \Y $and$libresoc.v:50819$1631_Y
+ connect \Y $and$libresoc.v:50822$1632_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50828$1640
+ cell $and $and$libresoc.v:50831$1641
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$38
connect \B \$40
- connect \Y $and$libresoc.v:50828$1640_Y
+ connect \Y $and$libresoc.v:50831$1641_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
- cell $and $and$libresoc.v:50829$1641
+ cell $and $and$libresoc.v:50832$1642
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \state_nia_wen
connect \B 1'1
- connect \Y $and$libresoc.v:50829$1641_Y
+ connect \Y $and$libresoc.v:50832$1642_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50836$1648
+ cell $and $and$libresoc.v:50839$1649
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$63
connect \B \$65
- connect \Y $and$libresoc.v:50836$1648_Y
+ connect \Y $and$libresoc.v:50839$1649_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50839$1651
+ cell $and $and$libresoc.v:50842$1652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$69
connect \B \$71
- connect \Y $and$libresoc.v:50839$1651_Y
+ connect \Y $and$libresoc.v:50842$1652_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50842$1654
+ cell $and $and$libresoc.v:50845$1655
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$75
connect \B \$77
- connect \Y $and$libresoc.v:50842$1654_Y
+ connect \Y $and$libresoc.v:50845$1655_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50845$1657
+ cell $and $and$libresoc.v:50848$1658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$81
connect \B \$83
- connect \Y $and$libresoc.v:50845$1657_Y
+ connect \Y $and$libresoc.v:50848$1658_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $and $and$libresoc.v:50848$1660
+ cell $and $and$libresoc.v:50851$1661
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$87
connect \B \$89
- connect \Y $and$libresoc.v:50848$1660_Y
+ connect \Y $and$libresoc.v:50851$1661_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $extend$libresoc.v:50810$1620
+ cell $pos $extend$libresoc.v:50813$1621
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \full_rd2__data_o
- connect \Y $extend$libresoc.v:50810$1620_Y
+ connect \Y $extend$libresoc.v:50813$1621_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $extend$libresoc.v:50811$1622
+ cell $pos $extend$libresoc.v:50814$1623
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 64
connect \A \full_rd__data_o
- connect \Y $extend$libresoc.v:50811$1622_Y
+ connect \Y $extend$libresoc.v:50814$1623_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:50805$1615
+ cell $mul $mul$libresoc.v:50808$1616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \dec2_cur_pc [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:50805$1615_Y
+ connect \Y $mul$libresoc.v:50808$1616_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $mul$libresoc.v:50807$1617
+ cell $mul $mul$libresoc.v:50810$1618
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 7
connect \A \dec2_cur_pc [2]
connect \B 6'100000
- connect \Y $mul$libresoc.v:50807$1617_Y
+ connect \Y $mul$libresoc.v:50810$1618_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174"
- cell $ne $ne$libresoc.v:50800$1610
+ cell $ne $ne$libresoc.v:50803$1611
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B 1'0
- connect \Y $ne$libresoc.v:50800$1610_Y
+ connect \Y $ne$libresoc.v:50803$1611_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:307"
- cell $ne $ne$libresoc.v:50809$1619
+ cell $ne $ne$libresoc.v:50812$1620
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \core_core_insn_type
connect \B 7'0000001
- connect \Y $ne$libresoc.v:50809$1619_Y
+ connect \Y $ne$libresoc.v:50812$1620_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
- cell $ne $ne$libresoc.v:50817$1629
+ cell $ne $ne$libresoc.v:50820$1630
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \delay
connect \B \$17
- connect \Y $ne$libresoc.v:50817$1629_Y
+ connect \Y $ne$libresoc.v:50820$1630_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50796$1606
+ cell $not $not$libresoc.v:50799$1607
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50796$1606_Y
+ connect \Y $not$libresoc.v:50799$1607_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50797$1607
+ cell $not $not$libresoc.v:50800$1608
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50797$1607_Y
+ connect \Y $not$libresoc.v:50800$1608_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50798$1608
+ cell $not $not$libresoc.v:50801$1609
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50798$1608_Y
+ connect \Y $not$libresoc.v:50801$1609_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50801$1611
+ cell $not $not$libresoc.v:50804$1612
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50801$1611_Y
+ connect \Y $not$libresoc.v:50804$1612_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50802$1612
+ cell $not $not$libresoc.v:50805$1613
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50802$1612_Y
+ connect \Y $not$libresoc.v:50805$1613_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
- cell $not $not$libresoc.v:50804$1614
+ cell $not $not$libresoc.v:50807$1615
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
- connect \Y $not$libresoc.v:50804$1614_Y
+ connect \Y $not$libresoc.v:50807$1615_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58"
- cell $not $not$libresoc.v:50818$1630
+ cell $not $not$libresoc.v:50821$1631
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cu_st__rel_o_dly
- connect \Y $not$libresoc.v:50818$1630_Y
+ connect \Y $not$libresoc.v:50821$1631_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:206"
- cell $not $not$libresoc.v:50821$1633
+ cell $not $not$libresoc.v:50824$1634
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_i_ok
- connect \Y $not$libresoc.v:50821$1633_Y
+ connect \Y $not$libresoc.v:50824$1634_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50822$1634
+ cell $not $not$libresoc.v:50825$1635
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50822$1634_Y
+ connect \Y $not$libresoc.v:50825$1635_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
- cell $not $not$libresoc.v:50823$1635
+ cell $not $not$libresoc.v:50826$1636
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
- connect \Y $not$libresoc.v:50823$1635_Y
+ connect \Y $not$libresoc.v:50826$1636_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50824$1636
+ cell $not $not$libresoc.v:50827$1637
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50824$1636_Y
+ connect \Y $not$libresoc.v:50827$1637_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:315"
- cell $not $not$libresoc.v:50825$1637
+ cell $not $not$libresoc.v:50828$1638
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
- connect \Y $not$libresoc.v:50825$1637_Y
+ connect \Y $not$libresoc.v:50828$1638_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50826$1638
+ cell $not $not$libresoc.v:50829$1639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50826$1638_Y
+ connect \Y $not$libresoc.v:50829$1639_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50827$1639
+ cell $not $not$libresoc.v:50830$1640
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50827$1639_Y
+ connect \Y $not$libresoc.v:50830$1640_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50831$1643
+ cell $not $not$libresoc.v:50834$1644
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50831$1643_Y
+ connect \Y $not$libresoc.v:50834$1644_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50832$1644
+ cell $not $not$libresoc.v:50835$1645
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50832$1644_Y
+ connect \Y $not$libresoc.v:50835$1645_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
- cell $not $not$libresoc.v:50833$1645
+ cell $not $not$libresoc.v:50836$1646
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \corebusy_o
- connect \Y $not$libresoc.v:50833$1645_Y
+ connect \Y $not$libresoc.v:50836$1646_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50834$1646
+ cell $not $not$libresoc.v:50837$1647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50834$1646_Y
+ connect \Y $not$libresoc.v:50837$1647_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50835$1647
+ cell $not $not$libresoc.v:50838$1648
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50835$1647_Y
+ connect \Y $not$libresoc.v:50838$1648_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50837$1649
+ cell $not $not$libresoc.v:50840$1650
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50837$1649_Y
+ connect \Y $not$libresoc.v:50840$1650_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50838$1650
+ cell $not $not$libresoc.v:50841$1651
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50838$1650_Y
+ connect \Y $not$libresoc.v:50841$1651_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50840$1652
+ cell $not $not$libresoc.v:50843$1653
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50840$1652_Y
+ connect \Y $not$libresoc.v:50843$1653_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50841$1653
+ cell $not $not$libresoc.v:50844$1654
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50841$1653_Y
+ connect \Y $not$libresoc.v:50844$1654_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50843$1655
+ cell $not $not$libresoc.v:50846$1656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50843$1655_Y
+ connect \Y $not$libresoc.v:50846$1656_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50844$1656
+ cell $not $not$libresoc.v:50847$1657
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50844$1656_Y
+ connect \Y $not$libresoc.v:50847$1657_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50846$1658
+ cell $not $not$libresoc.v:50849$1659
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50846$1658_Y
+ connect \Y $not$libresoc.v:50849$1659_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50847$1659
+ cell $not $not$libresoc.v:50850$1660
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50847$1659_Y
+ connect \Y $not$libresoc.v:50850$1660_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
- cell $not $not$libresoc.v:50849$1661
+ cell $not $not$libresoc.v:50852$1662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msr_read
- connect \Y $not$libresoc.v:50849$1661_Y
+ connect \Y $not$libresoc.v:50852$1662_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50850$1662
+ cell $not $not$libresoc.v:50853$1663
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \dbg_core_stop_o
- connect \Y $not$libresoc.v:50850$1662_Y
+ connect \Y $not$libresoc.v:50853$1663_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
- cell $not $not$libresoc.v:50851$1663
+ cell $not $not$libresoc.v:50854$1664
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_coresync_rst
- connect \Y $not$libresoc.v:50851$1663_Y
+ connect \Y $not$libresoc.v:50854$1664_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
- cell $or $or$libresoc.v:50815$1627
+ cell $or $or$libresoc.v:50818$1628
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A 1'0
connect \B \dbg_core_rst_o
- connect \Y $or$libresoc.v:50815$1627_Y
+ connect \Y $or$libresoc.v:50818$1628_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:180"
- cell $or $or$libresoc.v:50816$1628
+ cell $or $or$libresoc.v:50819$1629
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \$15
connect \B \rst
- connect \Y $or$libresoc.v:50816$1628_Y
+ connect \Y $or$libresoc.v:50819$1629_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $pos$libresoc.v:50810$1621
+ cell $pos $pos$libresoc.v:50813$1622
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:50810$1620_Y
- connect \Y $pos$libresoc.v:50810$1621_Y
+ connect \A $extend$libresoc.v:50813$1621_Y
+ connect \Y $pos$libresoc.v:50813$1622_Y
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- cell $pos $pos$libresoc.v:50811$1623
+ cell $pos $pos$libresoc.v:50814$1624
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
- connect \A $extend$libresoc.v:50811$1622_Y
- connect \Y $pos$libresoc.v:50811$1623_Y
+ connect \A $extend$libresoc.v:50814$1623_Y
+ connect \Y $pos$libresoc.v:50814$1624_Y
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
- cell $reduce_or $reduce_or$libresoc.v:50830$1642
+ cell $reduce_or $reduce_or$libresoc.v:50833$1643
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A \$45
- connect \Y $reduce_or$libresoc.v:50830$1642_Y
+ connect \Y $reduce_or$libresoc.v:50833$1643_Y
end
- attribute \src "libresoc.v:50806.19-50806.42"
- cell $shr $shr$libresoc.v:50806$1616
+ attribute \src "libresoc.v:50809.19-50809.42"
+ cell $shr $shr$libresoc.v:50809$1617
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$118
- connect \Y $shr$libresoc.v:50806$1616_Y
+ connect \Y $shr$libresoc.v:50809$1617_Y
end
- attribute \src "libresoc.v:50808.19-50808.42"
- cell $shr $shr$libresoc.v:50808$1618
+ attribute \src "libresoc.v:50811.19-50811.42"
+ cell $shr $shr$libresoc.v:50811$1619
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \imem_f_instr_o
connect \B \$122
- connect \Y $shr$libresoc.v:50808$1618_Y
+ connect \Y $shr$libresoc.v:50811$1619_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:393"
- cell $sub $sub$libresoc.v:50812$1624
+ cell $sub $sub$libresoc.v:50815$1625
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \issue__data_o
connect \B 1'1
- connect \Y $sub$libresoc.v:50812$1624_Y
+ connect \Y $sub$libresoc.v:50815$1625_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175"
- cell $sub $sub$libresoc.v:50814$1626
+ cell $sub $sub$libresoc.v:50817$1627
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \delay
connect \B 1'1
- connect \Y $sub$libresoc.v:50814$1626_Y
+ connect \Y $sub$libresoc.v:50817$1627_Y
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51024.8-51027.4"
+ attribute \src "libresoc.v:51027.8-51030.4"
cell \core \core
connect \coresync_clk \coresync_clk
connect \coresync_rst \core_coresync_rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51028.7-51053.4"
+ attribute \src "libresoc.v:51031.7-51056.4"
cell \dbg \dbg
connect \clk \clk
connect \core_dbg_msr \dbg_core_dbg_msr
connect \terminate_i \dbg_terminate_i
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51054.8-51120.4"
+ attribute \src "libresoc.v:51057.8-51123.4"
cell \dec2 \dec2
connect \asmcode \dec2_asmcode
connect \bigendian \dec2_bigendian
connect \xer_out \dec2_xer_out
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51121.8-51137.4"
+ attribute \src "libresoc.v:51124.8-51140.4"
cell \imem \imem
connect \a_pc_i \imem_a_pc_i
connect \a_valid_i \imem_a_valid_i
connect \wb_icache_en \imem_wb_icache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51138.8-51468.4"
+ attribute \src "libresoc.v:51141.8-51471.4"
cell \jtag \jtag
connect \TAP_bus__tck \TAP_bus__tck
connect \TAP_bus__tdi \TAP_bus__tdi
connect \wb_icache_en \imem_wb_icache_en
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51469.12-51483.4"
+ attribute \src "libresoc.v:51472.12-51486.4"
cell \xics_icp \xics_icp
connect \clk \clk
connect \core_irq_o \xics_icp_core_irq_o
connect \rst \rst
end
attribute \module_not_derived 1
- attribute \src "libresoc.v:51484.12-51497.4"
+ attribute \src "libresoc.v:51487.12-51500.4"
cell \xics_ics \xics_ics
connect \clk \clk
connect \icp_o_pri \xics_ics_icp_o_pri
connect \int_level_i \int_level_i
connect \rst \rst
end
- attribute \src "libresoc.v:48738.7-48738.20"
- process $proc$libresoc.v:48738$2163
+ attribute \src "libresoc.v:48741.7-48741.20"
+ process $proc$libresoc.v:48741$2164
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:48870.7-48870.25"
- process $proc$libresoc.v:48870$2164
+ attribute \src "libresoc.v:48873.7-48873.25"
+ process $proc$libresoc.v:48873$2165
assign { } { }
assign $1\bigendian_i[0:0] 1'0
sync always
sync init
update \bigendian_i $1\bigendian_i[0:0]
end
- attribute \src "libresoc.v:48882.13-48882.33"
- process $proc$libresoc.v:48882$2165
+ attribute \src "libresoc.v:48885.13-48885.33"
+ process $proc$libresoc.v:48885$2166
assign { } { }
assign $1\core_asmcode[7:0] 8'00000000
sync always
sync init
update \core_asmcode $1\core_asmcode[7:0]
end
- attribute \src "libresoc.v:48888.14-48888.50"
- process $proc$libresoc.v:48888$2166
+ attribute \src "libresoc.v:48891.14-48891.50"
+ process $proc$libresoc.v:48891$2167
assign { } { }
assign $1\core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_cia $1\core_core_cia[63:0]
end
- attribute \src "libresoc.v:48892.13-48892.36"
- process $proc$libresoc.v:48892$2167
+ attribute \src "libresoc.v:48895.13-48895.36"
+ process $proc$libresoc.v:48895$2168
assign { } { }
assign $1\core_core_cr_rd[7:0] 8'00000000
sync always
sync init
update \core_core_cr_rd $1\core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:48896.7-48896.32"
- process $proc$libresoc.v:48896$2168
+ attribute \src "libresoc.v:48899.7-48899.32"
+ process $proc$libresoc.v:48899$2169
assign { } { }
assign $1\core_core_cr_rd_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_rd_ok $1\core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:48900.13-48900.36"
- process $proc$libresoc.v:48900$2169
+ attribute \src "libresoc.v:48903.13-48903.36"
+ process $proc$libresoc.v:48903$2170
assign { } { }
assign $1\core_core_cr_wr[7:0] 8'00000000
sync always
sync init
update \core_core_cr_wr $1\core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:48904.7-48904.32"
- process $proc$libresoc.v:48904$2170
+ attribute \src "libresoc.v:48907.7-48907.32"
+ process $proc$libresoc.v:48907$2171
assign { } { }
assign $1\core_core_cr_wr_ok[0:0] 1'0
sync always
sync init
update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:48908.7-48908.37"
- process $proc$libresoc.v:48908$2171
+ attribute \src "libresoc.v:48911.7-48911.37"
+ process $proc$libresoc.v:48911$2172
assign { } { }
- assign $0\core_core_exc_$signal[0:0]$2172 1'0
+ assign $0\core_core_exc_$signal[0:0]$2173 1'0
sync always
sync init
- update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$2172
+ update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$2173
end
- attribute \src "libresoc.v:48910.7-48910.40"
- process $proc$libresoc.v:48910$2173
+ attribute \src "libresoc.v:48913.7-48913.40"
+ process $proc$libresoc.v:48913$2174
assign { } { }
- assign $0\core_core_exc_$signal$50[0:0]$2174 1'0
+ assign $0\core_core_exc_$signal$50[0:0]$2175 1'0
sync always
sync init
- update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$2174
+ update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$2175
end
- attribute \src "libresoc.v:48914.7-48914.40"
- process $proc$libresoc.v:48914$2175
+ attribute \src "libresoc.v:48917.7-48917.40"
+ process $proc$libresoc.v:48917$2176
assign { } { }
- assign $0\core_core_exc_$signal$51[0:0]$2176 1'0
+ assign $0\core_core_exc_$signal$51[0:0]$2177 1'0
sync always
sync init
- update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$2176
+ update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$2177
end
- attribute \src "libresoc.v:48918.7-48918.40"
- process $proc$libresoc.v:48918$2177
+ attribute \src "libresoc.v:48921.7-48921.40"
+ process $proc$libresoc.v:48921$2178
assign { } { }
- assign $0\core_core_exc_$signal$52[0:0]$2178 1'0
+ assign $0\core_core_exc_$signal$52[0:0]$2179 1'0
sync always
sync init
- update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$2178
+ update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$2179
end
- attribute \src "libresoc.v:48922.7-48922.40"
- process $proc$libresoc.v:48922$2179
+ attribute \src "libresoc.v:48925.7-48925.40"
+ process $proc$libresoc.v:48925$2180
assign { } { }
- assign $0\core_core_exc_$signal$53[0:0]$2180 1'0
+ assign $0\core_core_exc_$signal$53[0:0]$2181 1'0
sync always
sync init
- update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$2180
+ update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$2181
end
- attribute \src "libresoc.v:48926.7-48926.40"
- process $proc$libresoc.v:48926$2181
+ attribute \src "libresoc.v:48929.7-48929.40"
+ process $proc$libresoc.v:48929$2182
assign { } { }
- assign $0\core_core_exc_$signal$54[0:0]$2182 1'0
+ assign $0\core_core_exc_$signal$54[0:0]$2183 1'0
sync always
sync init
- update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$2182
+ update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$2183
end
- attribute \src "libresoc.v:48930.7-48930.40"
- process $proc$libresoc.v:48930$2183
+ attribute \src "libresoc.v:48933.7-48933.40"
+ process $proc$libresoc.v:48933$2184
assign { } { }
- assign $0\core_core_exc_$signal$55[0:0]$2184 1'0
+ assign $0\core_core_exc_$signal$55[0:0]$2185 1'0
sync always
sync init
- update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$2184
+ update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$2185
end
- attribute \src "libresoc.v:48934.7-48934.40"
- process $proc$libresoc.v:48934$2185
+ attribute \src "libresoc.v:48937.7-48937.40"
+ process $proc$libresoc.v:48937$2186
assign { } { }
- assign $0\core_core_exc_$signal$56[0:0]$2186 1'0
+ assign $0\core_core_exc_$signal$56[0:0]$2187 1'0
sync always
sync init
- update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$2186
+ update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$2187
end
- attribute \src "libresoc.v:48953.14-48953.41"
- process $proc$libresoc.v:48953$2187
+ attribute \src "libresoc.v:48956.14-48956.41"
+ process $proc$libresoc.v:48956$2188
assign { } { }
assign $1\core_core_fn_unit[11:0] 12'000000000000
sync always
sync init
update \core_core_fn_unit $1\core_core_fn_unit[11:0]
end
- attribute \src "libresoc.v:48961.13-48961.41"
- process $proc$libresoc.v:48961$2188
+ attribute \src "libresoc.v:48964.13-48964.41"
+ process $proc$libresoc.v:48964$2189
assign { } { }
assign $1\core_core_input_carry[1:0] 2'00
sync always
sync init
update \core_core_input_carry $1\core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:48965.14-48965.36"
- process $proc$libresoc.v:48965$2189
+ attribute \src "libresoc.v:48968.14-48968.36"
+ process $proc$libresoc.v:48968$2190
assign { } { }
assign $1\core_core_insn[31:0] 0
sync always
sync init
update \core_core_insn $1\core_core_insn[31:0]
end
- attribute \src "libresoc.v:49043.13-49043.40"
- process $proc$libresoc.v:49043$2190
+ attribute \src "libresoc.v:49046.13-49046.40"
+ process $proc$libresoc.v:49046$2191
assign { } { }
assign $1\core_core_insn_type[6:0] 7'0000000
sync always
sync init
update \core_core_insn_type $1\core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:49047.7-49047.32"
- process $proc$libresoc.v:49047$2191
+ attribute \src "libresoc.v:49050.7-49050.32"
+ process $proc$libresoc.v:49050$2192
assign { } { }
assign $1\core_core_is_32bit[0:0] 1'0
sync always
sync init
update \core_core_is_32bit $1\core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:49051.7-49051.26"
- process $proc$libresoc.v:49051$2192
+ attribute \src "libresoc.v:49054.7-49054.26"
+ process $proc$libresoc.v:49054$2193
assign { } { }
assign $1\core_core_lk[0:0] 1'0
sync always
sync init
update \core_core_lk $1\core_core_lk[0:0]
end
- attribute \src "libresoc.v:49055.14-49055.50"
- process $proc$libresoc.v:49055$2193
+ attribute \src "libresoc.v:49058.14-49058.50"
+ process $proc$libresoc.v:49058$2194
assign { } { }
assign $1\core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_core_msr $1\core_core_msr[63:0]
end
- attribute \src "libresoc.v:49059.7-49059.26"
- process $proc$libresoc.v:49059$2194
+ attribute \src "libresoc.v:49062.7-49062.26"
+ process $proc$libresoc.v:49062$2195
assign { } { }
assign $1\core_core_oe[0:0] 1'0
sync always
sync init
update \core_core_oe $1\core_core_oe[0:0]
end
- attribute \src "libresoc.v:49063.7-49063.29"
- process $proc$libresoc.v:49063$2195
+ attribute \src "libresoc.v:49066.7-49066.29"
+ process $proc$libresoc.v:49066$2196
assign { } { }
assign $1\core_core_oe_ok[0:0] 1'0
sync always
sync init
update \core_core_oe_ok $1\core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:49067.7-49067.26"
- process $proc$libresoc.v:49067$2196
+ attribute \src "libresoc.v:49070.7-49070.26"
+ process $proc$libresoc.v:49070$2197
assign { } { }
assign $1\core_core_rc[0:0] 1'0
sync always
sync init
update \core_core_rc $1\core_core_rc[0:0]
end
- attribute \src "libresoc.v:49071.7-49071.29"
- process $proc$libresoc.v:49071$2197
+ attribute \src "libresoc.v:49074.7-49074.29"
+ process $proc$libresoc.v:49074$2198
assign { } { }
assign $1\core_core_rc_ok[0:0] 1'0
sync always
sync init
update \core_core_rc_ok $1\core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:49075.14-49075.43"
- process $proc$libresoc.v:49075$2198
+ attribute \src "libresoc.v:49078.14-49078.43"
+ process $proc$libresoc.v:49078$2199
assign { } { }
assign $1\core_core_trapaddr[12:0] 13'0000000000000
sync always
sync init
update \core_core_trapaddr $1\core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:49079.13-49079.39"
- process $proc$libresoc.v:49079$2199
+ attribute \src "libresoc.v:49082.13-49082.39"
+ process $proc$libresoc.v:49082$2200
assign { } { }
assign $1\core_core_traptype[7:0] 8'00000000
sync always
sync init
update \core_core_traptype $1\core_core_traptype[7:0]
end
- attribute \src "libresoc.v:49085.13-49085.31"
- process $proc$libresoc.v:49085$2200
+ attribute \src "libresoc.v:49088.13-49088.31"
+ process $proc$libresoc.v:49088$2201
assign { } { }
assign $1\core_cr_in1[2:0] 3'000
sync always
sync init
update \core_cr_in1 $1\core_cr_in1[2:0]
end
- attribute \src "libresoc.v:49089.7-49089.28"
- process $proc$libresoc.v:49089$2201
+ attribute \src "libresoc.v:49092.7-49092.28"
+ process $proc$libresoc.v:49092$2202
assign { } { }
assign $1\core_cr_in1_ok[0:0] 1'0
sync always
sync init
update \core_cr_in1_ok $1\core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:49093.13-49093.31"
- process $proc$libresoc.v:49093$2202
+ attribute \src "libresoc.v:49096.13-49096.31"
+ process $proc$libresoc.v:49096$2203
assign { } { }
assign $1\core_cr_in2[2:0] 3'000
sync always
sync init
update \core_cr_in2 $1\core_cr_in2[2:0]
end
- attribute \src "libresoc.v:49095.13-49095.36"
- process $proc$libresoc.v:49095$2203
+ attribute \src "libresoc.v:49098.13-49098.36"
+ process $proc$libresoc.v:49098$2204
assign { } { }
- assign $0\core_cr_in2$48[2:0]$2204 3'000
+ assign $0\core_cr_in2$48[2:0]$2205 3'000
sync always
sync init
- update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$2204
+ update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$2205
end
- attribute \src "libresoc.v:49101.7-49101.28"
- process $proc$libresoc.v:49101$2205
+ attribute \src "libresoc.v:49104.7-49104.28"
+ process $proc$libresoc.v:49104$2206
assign { } { }
assign $1\core_cr_in2_ok[0:0] 1'0
sync always
sync init
update \core_cr_in2_ok $1\core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:49103.7-49103.33"
- process $proc$libresoc.v:49103$2206
+ attribute \src "libresoc.v:49106.7-49106.33"
+ process $proc$libresoc.v:49106$2207
assign { } { }
- assign $0\core_cr_in2_ok$49[0:0]$2207 1'0
+ assign $0\core_cr_in2_ok$49[0:0]$2208 1'0
sync always
sync init
- update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$2207
+ update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$2208
end
- attribute \src "libresoc.v:49109.13-49109.31"
- process $proc$libresoc.v:49109$2208
+ attribute \src "libresoc.v:49112.13-49112.31"
+ process $proc$libresoc.v:49112$2209
assign { } { }
assign $1\core_cr_out[2:0] 3'000
sync always
sync init
update \core_cr_out $1\core_cr_out[2:0]
end
- attribute \src "libresoc.v:49113.7-49113.28"
- process $proc$libresoc.v:49113$2209
+ attribute \src "libresoc.v:49116.7-49116.28"
+ process $proc$libresoc.v:49116$2210
assign { } { }
assign $1\core_cr_out_ok[0:0] 1'0
sync always
sync init
update \core_cr_out_ok $1\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:49117.14-49117.45"
- process $proc$libresoc.v:49117$2210
+ attribute \src "libresoc.v:49120.14-49120.45"
+ process $proc$libresoc.v:49120$2211
assign { } { }
assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_dec $1\core_dec[63:0]
end
- attribute \src "libresoc.v:49121.13-49121.28"
- process $proc$libresoc.v:49121$2211
+ attribute \src "libresoc.v:49124.13-49124.28"
+ process $proc$libresoc.v:49124$2212
assign { } { }
assign $1\core_ea[4:0] 5'00000
sync always
sync init
update \core_ea $1\core_ea[4:0]
end
- attribute \src "libresoc.v:49125.7-49125.24"
- process $proc$libresoc.v:49125$2212
+ attribute \src "libresoc.v:49128.7-49128.24"
+ process $proc$libresoc.v:49128$2213
assign { } { }
assign $1\core_ea_ok[0:0] 1'0
sync always
sync init
update \core_ea_ok $1\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:49129.7-49129.23"
- process $proc$libresoc.v:49129$2213
+ attribute \src "libresoc.v:49132.7-49132.23"
+ process $proc$libresoc.v:49132$2214
assign { } { }
assign $1\core_eint[0:0] 1'0
sync always
sync init
update \core_eint $1\core_eint[0:0]
end
- attribute \src "libresoc.v:49133.13-49133.30"
- process $proc$libresoc.v:49133$2214
+ attribute \src "libresoc.v:49136.13-49136.30"
+ process $proc$libresoc.v:49136$2215
assign { } { }
assign $1\core_fast1[2:0] 3'000
sync always
sync init
update \core_fast1 $1\core_fast1[2:0]
end
- attribute \src "libresoc.v:49137.7-49137.27"
- process $proc$libresoc.v:49137$2215
+ attribute \src "libresoc.v:49140.7-49140.27"
+ process $proc$libresoc.v:49140$2216
assign { } { }
assign $1\core_fast1_ok[0:0] 1'0
sync always
sync init
update \core_fast1_ok $1\core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:49141.13-49141.30"
- process $proc$libresoc.v:49141$2216
+ attribute \src "libresoc.v:49144.13-49144.30"
+ process $proc$libresoc.v:49144$2217
assign { } { }
assign $1\core_fast2[2:0] 3'000
sync always
sync init
update \core_fast2 $1\core_fast2[2:0]
end
- attribute \src "libresoc.v:49145.7-49145.27"
- process $proc$libresoc.v:49145$2217
+ attribute \src "libresoc.v:49148.7-49148.27"
+ process $proc$libresoc.v:49148$2218
assign { } { }
assign $1\core_fast2_ok[0:0] 1'0
sync always
sync init
update \core_fast2_ok $1\core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:49149.13-49149.31"
- process $proc$libresoc.v:49149$2218
+ attribute \src "libresoc.v:49152.13-49152.31"
+ process $proc$libresoc.v:49152$2219
assign { } { }
assign $1\core_fasto1[2:0] 3'000
sync always
sync init
update \core_fasto1 $1\core_fasto1[2:0]
end
- attribute \src "libresoc.v:49153.7-49153.28"
- process $proc$libresoc.v:49153$2219
+ attribute \src "libresoc.v:49156.7-49156.28"
+ process $proc$libresoc.v:49156$2220
assign { } { }
assign $1\core_fasto1_ok[0:0] 1'0
sync always
sync init
update \core_fasto1_ok $1\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:49157.13-49157.31"
- process $proc$libresoc.v:49157$2220
+ attribute \src "libresoc.v:49160.13-49160.31"
+ process $proc$libresoc.v:49160$2221
assign { } { }
assign $1\core_fasto2[2:0] 3'000
sync always
sync init
update \core_fasto2 $1\core_fasto2[2:0]
end
- attribute \src "libresoc.v:49161.7-49161.28"
- process $proc$libresoc.v:49161$2221
+ attribute \src "libresoc.v:49164.7-49164.28"
+ process $proc$libresoc.v:49164$2222
assign { } { }
assign $1\core_fasto2_ok[0:0] 1'0
sync always
sync init
update \core_fasto2_ok $1\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:49165.14-49165.45"
- process $proc$libresoc.v:49165$2222
+ attribute \src "libresoc.v:49168.14-49168.45"
+ process $proc$libresoc.v:49168$2223
assign { } { }
assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_msr $1\core_msr[63:0]
end
- attribute \src "libresoc.v:49169.14-49169.44"
- process $proc$libresoc.v:49169$2223
+ attribute \src "libresoc.v:49172.14-49172.44"
+ process $proc$libresoc.v:49172$2224
assign { } { }
assign $1\core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \core_pc $1\core_pc[63:0]
end
- attribute \src "libresoc.v:49173.13-49173.30"
- process $proc$libresoc.v:49173$2224
+ attribute \src "libresoc.v:49176.13-49176.30"
+ process $proc$libresoc.v:49176$2225
assign { } { }
assign $1\core_reg1[4:0] 5'00000
sync always
sync init
update \core_reg1 $1\core_reg1[4:0]
end
- attribute \src "libresoc.v:49177.7-49177.26"
- process $proc$libresoc.v:49177$2225
+ attribute \src "libresoc.v:49180.7-49180.26"
+ process $proc$libresoc.v:49180$2226
assign { } { }
assign $1\core_reg1_ok[0:0] 1'0
sync always
sync init
update \core_reg1_ok $1\core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:49181.13-49181.30"
- process $proc$libresoc.v:49181$2226
+ attribute \src "libresoc.v:49184.13-49184.30"
+ process $proc$libresoc.v:49184$2227
assign { } { }
assign $1\core_reg2[4:0] 5'00000
sync always
sync init
update \core_reg2 $1\core_reg2[4:0]
end
- attribute \src "libresoc.v:49185.7-49185.26"
- process $proc$libresoc.v:49185$2227
+ attribute \src "libresoc.v:49188.7-49188.26"
+ process $proc$libresoc.v:49188$2228
assign { } { }
assign $1\core_reg2_ok[0:0] 1'0
sync always
sync init
update \core_reg2_ok $1\core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:49189.13-49189.30"
- process $proc$libresoc.v:49189$2228
+ attribute \src "libresoc.v:49192.13-49192.30"
+ process $proc$libresoc.v:49192$2229
assign { } { }
assign $1\core_reg3[4:0] 5'00000
sync always
sync init
update \core_reg3 $1\core_reg3[4:0]
end
- attribute \src "libresoc.v:49193.7-49193.26"
- process $proc$libresoc.v:49193$2229
+ attribute \src "libresoc.v:49196.7-49196.26"
+ process $proc$libresoc.v:49196$2230
assign { } { }
assign $1\core_reg3_ok[0:0] 1'0
sync always
sync init
update \core_reg3_ok $1\core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:49197.13-49197.30"
- process $proc$libresoc.v:49197$2230
+ attribute \src "libresoc.v:49200.13-49200.30"
+ process $proc$libresoc.v:49200$2231
assign { } { }
assign $1\core_rego[4:0] 5'00000
sync always
sync init
update \core_rego $1\core_rego[4:0]
end
- attribute \src "libresoc.v:49201.7-49201.26"
- process $proc$libresoc.v:49201$2231
+ attribute \src "libresoc.v:49204.7-49204.26"
+ process $proc$libresoc.v:49204$2232
assign { } { }
assign $1\core_rego_ok[0:0] 1'0
sync always
sync init
update \core_rego_ok $1\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:49316.13-49316.32"
- process $proc$libresoc.v:49316$2232
+ attribute \src "libresoc.v:49319.13-49319.32"
+ process $proc$libresoc.v:49319$2233
assign { } { }
assign $1\core_spr1[9:0] 10'0000000000
sync always
sync init
update \core_spr1 $1\core_spr1[9:0]
end
- attribute \src "libresoc.v:49320.7-49320.26"
- process $proc$libresoc.v:49320$2233
+ attribute \src "libresoc.v:49323.7-49323.26"
+ process $proc$libresoc.v:49323$2234
assign { } { }
assign $1\core_spr1_ok[0:0] 1'0
sync always
sync init
update \core_spr1_ok $1\core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:49435.13-49435.32"
- process $proc$libresoc.v:49435$2234
+ attribute \src "libresoc.v:49438.13-49438.32"
+ process $proc$libresoc.v:49438$2235
assign { } { }
assign $1\core_spro[9:0] 10'0000000000
sync always
sync init
update \core_spro $1\core_spro[9:0]
end
- attribute \src "libresoc.v:49439.7-49439.26"
- process $proc$libresoc.v:49439$2235
+ attribute \src "libresoc.v:49442.7-49442.26"
+ process $proc$libresoc.v:49442$2236
assign { } { }
assign $1\core_spro_ok[0:0] 1'0
sync always
sync init
update \core_spro_ok $1\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:49447.13-49447.31"
- process $proc$libresoc.v:49447$2236
+ attribute \src "libresoc.v:49450.13-49450.31"
+ process $proc$libresoc.v:49450$2237
assign { } { }
assign $1\core_xer_in[2:0] 3'000
sync always
sync init
update \core_xer_in $1\core_xer_in[2:0]
end
- attribute \src "libresoc.v:49451.7-49451.26"
- process $proc$libresoc.v:49451$2237
+ attribute \src "libresoc.v:49454.7-49454.26"
+ process $proc$libresoc.v:49454$2238
assign { } { }
assign $1\core_xer_out[0:0] 1'0
sync always
sync init
update \core_xer_out $1\core_xer_out[0:0]
end
- attribute \src "libresoc.v:49467.7-49467.30"
- process $proc$libresoc.v:49467$2238
+ attribute \src "libresoc.v:49470.7-49470.30"
+ process $proc$libresoc.v:49470$2239
assign { } { }
assign $1\cu_st__rel_o_dly[0:0] 1'0
sync always
sync init
update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:49473.7-49473.24"
- process $proc$libresoc.v:49473$2239
+ attribute \src "libresoc.v:49476.7-49476.24"
+ process $proc$libresoc.v:49476$2240
assign { } { }
assign $1\d_cr_delay[0:0] 1'0
sync always
sync init
update \d_cr_delay $1\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:49477.7-49477.25"
- process $proc$libresoc.v:49477$2240
+ attribute \src "libresoc.v:49480.7-49480.25"
+ process $proc$libresoc.v:49480$2241
assign { } { }
assign $1\d_reg_delay[0:0] 1'0
sync always
sync init
update \d_reg_delay $1\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:49481.7-49481.25"
- process $proc$libresoc.v:49481$2241
+ attribute \src "libresoc.v:49484.7-49484.25"
+ process $proc$libresoc.v:49484$2242
assign { } { }
assign $1\d_xer_delay[0:0] 1'0
sync always
sync init
update \d_xer_delay $1\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:49519.13-49519.34"
- process $proc$libresoc.v:49519$2242
+ attribute \src "libresoc.v:49522.13-49522.34"
+ process $proc$libresoc.v:49522$2243
assign { } { }
assign $1\dbg_dmi_addr_i[3:0] 4'0000
sync always
sync init
update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:49523.14-49523.48"
- process $proc$libresoc.v:49523$2243
+ attribute \src "libresoc.v:49526.14-49526.48"
+ process $proc$libresoc.v:49526$2244
assign { } { }
assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dbg_dmi_din $1\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:49529.7-49529.27"
- process $proc$libresoc.v:49529$2244
+ attribute \src "libresoc.v:49532.7-49532.27"
+ process $proc$libresoc.v:49532$2245
assign { } { }
assign $1\dbg_dmi_req_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:49533.7-49533.26"
- process $proc$libresoc.v:49533$2245
+ attribute \src "libresoc.v:49536.7-49536.26"
+ process $proc$libresoc.v:49536$2246
assign { } { }
assign $1\dbg_dmi_we_i[0:0] 1'0
sync always
sync init
update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:49569.14-49569.49"
- process $proc$libresoc.v:49569$2246
+ attribute \src "libresoc.v:49572.14-49572.49"
+ process $proc$libresoc.v:49572$2247
assign { } { }
assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_dec $1\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:49573.7-49573.27"
- process $proc$libresoc.v:49573$2247
+ attribute \src "libresoc.v:49576.7-49576.27"
+ process $proc$libresoc.v:49576$2248
assign { } { }
assign $1\dec2_cur_eint[0:0] 1'0
sync always
sync init
update \dec2_cur_eint $1\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:49577.14-49577.49"
- process $proc$libresoc.v:49577$2248
+ attribute \src "libresoc.v:49580.14-49580.49"
+ process $proc$libresoc.v:49580$2249
assign { } { }
assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_msr $1\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:49581.14-49581.48"
- process $proc$libresoc.v:49581$2249
+ attribute \src "libresoc.v:49584.14-49584.48"
+ process $proc$libresoc.v:49584$2250
assign { } { }
assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \dec2_cur_pc $1\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:49990.13-49990.25"
- process $proc$libresoc.v:49990$2250
+ attribute \src "libresoc.v:49993.13-49993.25"
+ process $proc$libresoc.v:49993$2251
assign { } { }
assign $1\delay[1:0] 2'11
sync always
sync init
update \delay $1\delay[1:0]
end
- attribute \src "libresoc.v:50012.13-50012.29"
- process $proc$libresoc.v:50012$2251
+ attribute \src "libresoc.v:50015.13-50015.29"
+ process $proc$libresoc.v:50015$2252
assign { } { }
assign $1\fsm_state[1:0] 2'00
sync always
sync init
update \fsm_state $1\fsm_state[1:0]
end
- attribute \src "libresoc.v:50014.13-50014.35"
- process $proc$libresoc.v:50014$2252
+ attribute \src "libresoc.v:50017.13-50017.35"
+ process $proc$libresoc.v:50017$2253
assign { } { }
- assign $0\fsm_state$131[1:0]$2253 2'00
+ assign $0\fsm_state$131[1:0]$2254 2'00
sync always
sync init
- update \fsm_state$131 $0\fsm_state$131[1:0]$2253
+ update \fsm_state$131 $0\fsm_state$131[1:0]$2254
end
- attribute \src "libresoc.v:50264.14-50264.28"
- process $proc$libresoc.v:50264$2254
+ attribute \src "libresoc.v:50267.14-50267.28"
+ process $proc$libresoc.v:50267$2255
assign { } { }
assign $1\ilatch[31:0] 0
sync always
sync init
update \ilatch $1\ilatch[31:0]
end
- attribute \src "libresoc.v:50298.7-50298.30"
- process $proc$libresoc.v:50298$2255
+ attribute \src "libresoc.v:50301.7-50301.30"
+ process $proc$libresoc.v:50301$2256
assign { } { }
assign $1\jtag_dmi0__ack_o[0:0] 1'0
sync always
sync init
update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0]
end
- attribute \src "libresoc.v:50306.14-50306.52"
- process $proc$libresoc.v:50306$2256
+ attribute \src "libresoc.v:50309.14-50309.52"
+ process $proc$libresoc.v:50309$2257
assign { } { }
assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000
sync always
sync init
update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0]
end
- attribute \src "libresoc.v:50366.7-50366.22"
- process $proc$libresoc.v:50366$2257
+ attribute \src "libresoc.v:50369.7-50369.22"
+ process $proc$libresoc.v:50369$2258
assign { } { }
assign $1\msr_read[0:0] 1'1
sync always
sync init
update \msr_read $1\msr_read[0:0]
end
- attribute \src "libresoc.v:50394.7-50394.24"
- process $proc$libresoc.v:50394$2258
+ attribute \src "libresoc.v:50397.7-50397.24"
+ process $proc$libresoc.v:50397$2259
assign { } { }
assign $1\pc_changed[0:0] 1'0
sync always
sync init
update \pc_changed $1\pc_changed[0:0]
end
- attribute \src "libresoc.v:50404.7-50404.25"
- process $proc$libresoc.v:50404$2259
+ attribute \src "libresoc.v:50407.7-50407.25"
+ process $proc$libresoc.v:50407$2260
assign { } { }
assign $1\pc_ok_delay[0:0] 1'0
sync always
sync init
update \pc_ok_delay $1\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:50418.14-50418.32"
- process $proc$libresoc.v:50418$2260
+ attribute \src "libresoc.v:50421.14-50421.32"
+ process $proc$libresoc.v:50421$2261
assign { } { }
assign $1\raw_insn_i[31:0] 0
sync always
sync init
update \raw_insn_i $1\raw_insn_i[31:0]
end
- attribute \src "libresoc.v:50852.3-50853.41"
- process $proc$libresoc.v:50852$1664
+ attribute \src "libresoc.v:50855.3-50856.41"
+ process $proc$libresoc.v:50855$1665
assign { } { }
assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next
sync posedge \clk
update \dec2_cur_dec $0\dec2_cur_dec[63:0]
end
- attribute \src "libresoc.v:50854.3-50855.33"
- process $proc$libresoc.v:50854$1665
+ attribute \src "libresoc.v:50857.3-50858.33"
+ process $proc$libresoc.v:50857$1666
assign { } { }
assign $0\core_dec[63:0] \core_dec$next
sync posedge \clk
update \core_dec $0\core_dec[63:0]
end
- attribute \src "libresoc.v:50856.3-50857.41"
- process $proc$libresoc.v:50856$1666
+ attribute \src "libresoc.v:50859.3-50860.41"
+ process $proc$libresoc.v:50859$1667
assign { } { }
assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next
sync posedge \clk
update \dec2_cur_msr $0\dec2_cur_msr[63:0]
end
- attribute \src "libresoc.v:50858.3-50859.35"
- process $proc$libresoc.v:50858$1667
+ attribute \src "libresoc.v:50861.3-50862.35"
+ process $proc$libresoc.v:50861$1668
assign { } { }
assign $0\fsm_state[1:0] \fsm_state$next
sync posedge \clk
update \fsm_state $0\fsm_state[1:0]
end
- attribute \src "libresoc.v:50860.3-50861.33"
- process $proc$libresoc.v:50860$1668
+ attribute \src "libresoc.v:50863.3-50864.33"
+ process $proc$libresoc.v:50863$1669
assign { } { }
assign $0\msr_read[0:0] \msr_read$next
sync posedge \clk
update \msr_read $0\msr_read[0:0]
end
- attribute \src "libresoc.v:50862.3-50863.39"
- process $proc$libresoc.v:50862$1669
+ attribute \src "libresoc.v:50865.3-50866.39"
+ process $proc$libresoc.v:50865$1670
assign { } { }
assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next
sync posedge \clk
update \dec2_cur_pc $0\dec2_cur_pc[63:0]
end
- attribute \src "libresoc.v:50864.3-50865.39"
- process $proc$libresoc.v:50864$1670
+ attribute \src "libresoc.v:50867.3-50868.39"
+ process $proc$libresoc.v:50867$1671
assign { } { }
assign $0\bigendian_i[0:0] \bigendian_i$next
sync posedge \clk
update \bigendian_i $0\bigendian_i[0:0]
end
- attribute \src "libresoc.v:50866.3-50867.37"
- process $proc$libresoc.v:50866$1671
+ attribute \src "libresoc.v:50869.3-50870.37"
+ process $proc$libresoc.v:50869$1672
assign { } { }
assign $0\raw_insn_i[31:0] \raw_insn_i$next
sync posedge \clk
update \raw_insn_i $0\raw_insn_i[31:0]
end
- attribute \src "libresoc.v:50868.3-50869.41"
- process $proc$libresoc.v:50868$1672
+ attribute \src "libresoc.v:50871.3-50872.41"
+ process $proc$libresoc.v:50871$1673
assign { } { }
assign $0\core_asmcode[7:0] \core_asmcode$next
sync posedge \clk
update \core_asmcode $0\core_asmcode[7:0]
end
- attribute \src "libresoc.v:50870.3-50871.35"
- process $proc$libresoc.v:50870$1673
+ attribute \src "libresoc.v:50873.3-50874.35"
+ process $proc$libresoc.v:50873$1674
assign { } { }
assign $0\core_rego[4:0] \core_rego$next
sync posedge \clk
update \core_rego $0\core_rego[4:0]
end
- attribute \src "libresoc.v:50872.3-50873.41"
- process $proc$libresoc.v:50872$1674
+ attribute \src "libresoc.v:50875.3-50876.41"
+ process $proc$libresoc.v:50875$1675
assign { } { }
assign $0\core_rego_ok[0:0] \core_rego_ok$next
sync posedge \clk
update \core_rego_ok $0\core_rego_ok[0:0]
end
- attribute \src "libresoc.v:50874.3-50875.45"
- process $proc$libresoc.v:50874$1675
+ attribute \src "libresoc.v:50877.3-50878.45"
+ process $proc$libresoc.v:50877$1676
assign { } { }
- assign $0\fsm_state$131[1:0]$1676 \fsm_state$131$next
+ assign $0\fsm_state$131[1:0]$1677 \fsm_state$131$next
sync posedge \clk
- update \fsm_state$131 $0\fsm_state$131[1:0]$1676
+ update \fsm_state$131 $0\fsm_state$131[1:0]$1677
end
- attribute \src "libresoc.v:50876.3-50877.31"
- process $proc$libresoc.v:50876$1677
+ attribute \src "libresoc.v:50879.3-50880.31"
+ process $proc$libresoc.v:50879$1678
assign { } { }
assign $0\core_ea[4:0] \core_ea$next
sync posedge \clk
update \core_ea $0\core_ea[4:0]
end
- attribute \src "libresoc.v:50878.3-50879.37"
- process $proc$libresoc.v:50878$1678
+ attribute \src "libresoc.v:50881.3-50882.37"
+ process $proc$libresoc.v:50881$1679
assign { } { }
assign $0\core_ea_ok[0:0] \core_ea_ok$next
sync posedge \clk
update \core_ea_ok $0\core_ea_ok[0:0]
end
- attribute \src "libresoc.v:50880.3-50881.35"
- process $proc$libresoc.v:50880$1679
+ attribute \src "libresoc.v:50883.3-50884.35"
+ process $proc$libresoc.v:50883$1680
assign { } { }
assign $0\core_reg1[4:0] \core_reg1$next
sync posedge \clk
update \core_reg1 $0\core_reg1[4:0]
end
- attribute \src "libresoc.v:50882.3-50883.41"
- process $proc$libresoc.v:50882$1680
+ attribute \src "libresoc.v:50885.3-50886.41"
+ process $proc$libresoc.v:50885$1681
assign { } { }
assign $0\core_reg1_ok[0:0] \core_reg1_ok$next
sync posedge \clk
update \core_reg1_ok $0\core_reg1_ok[0:0]
end
- attribute \src "libresoc.v:50884.3-50885.35"
- process $proc$libresoc.v:50884$1681
+ attribute \src "libresoc.v:50887.3-50888.35"
+ process $proc$libresoc.v:50887$1682
assign { } { }
assign $0\core_reg2[4:0] \core_reg2$next
sync posedge \clk
update \core_reg2 $0\core_reg2[4:0]
end
- attribute \src "libresoc.v:50886.3-50887.41"
- process $proc$libresoc.v:50886$1682
+ attribute \src "libresoc.v:50889.3-50890.41"
+ process $proc$libresoc.v:50889$1683
assign { } { }
assign $0\core_reg2_ok[0:0] \core_reg2_ok$next
sync posedge \clk
update \core_reg2_ok $0\core_reg2_ok[0:0]
end
- attribute \src "libresoc.v:50888.3-50889.35"
- process $proc$libresoc.v:50888$1683
+ attribute \src "libresoc.v:50891.3-50892.35"
+ process $proc$libresoc.v:50891$1684
assign { } { }
assign $0\core_reg3[4:0] \core_reg3$next
sync posedge \clk
update \core_reg3 $0\core_reg3[4:0]
end
- attribute \src "libresoc.v:50890.3-50891.41"
- process $proc$libresoc.v:50890$1684
+ attribute \src "libresoc.v:50893.3-50894.41"
+ process $proc$libresoc.v:50893$1685
assign { } { }
assign $0\core_reg3_ok[0:0] \core_reg3_ok$next
sync posedge \clk
update \core_reg3_ok $0\core_reg3_ok[0:0]
end
- attribute \src "libresoc.v:50892.3-50893.35"
- process $proc$libresoc.v:50892$1685
+ attribute \src "libresoc.v:50895.3-50896.35"
+ process $proc$libresoc.v:50895$1686
assign { } { }
assign $0\core_spro[9:0] \core_spro$next
sync posedge \clk
update \core_spro $0\core_spro[9:0]
end
- attribute \src "libresoc.v:50894.3-50895.41"
- process $proc$libresoc.v:50894$1686
+ attribute \src "libresoc.v:50897.3-50898.41"
+ process $proc$libresoc.v:50897$1687
assign { } { }
assign $0\core_spro_ok[0:0] \core_spro_ok$next
sync posedge \clk
update \core_spro_ok $0\core_spro_ok[0:0]
end
- attribute \src "libresoc.v:50896.3-50897.39"
- process $proc$libresoc.v:50896$1687
+ attribute \src "libresoc.v:50899.3-50900.39"
+ process $proc$libresoc.v:50899$1688
assign { } { }
assign $0\d_xer_delay[0:0] \d_xer_delay$next
sync posedge \clk
update \d_xer_delay $0\d_xer_delay[0:0]
end
- attribute \src "libresoc.v:50898.3-50899.35"
- process $proc$libresoc.v:50898$1688
+ attribute \src "libresoc.v:50901.3-50902.35"
+ process $proc$libresoc.v:50901$1689
assign { } { }
assign $0\core_spr1[9:0] \core_spr1$next
sync posedge \clk
update \core_spr1 $0\core_spr1[9:0]
end
- attribute \src "libresoc.v:50900.3-50901.41"
- process $proc$libresoc.v:50900$1689
+ attribute \src "libresoc.v:50903.3-50904.41"
+ process $proc$libresoc.v:50903$1690
assign { } { }
assign $0\core_spr1_ok[0:0] \core_spr1_ok$next
sync posedge \clk
update \core_spr1_ok $0\core_spr1_ok[0:0]
end
- attribute \src "libresoc.v:50902.3-50903.39"
- process $proc$libresoc.v:50902$1690
+ attribute \src "libresoc.v:50905.3-50906.39"
+ process $proc$libresoc.v:50905$1691
assign { } { }
assign $0\core_xer_in[2:0] \core_xer_in$next
sync posedge \clk
update \core_xer_in $0\core_xer_in[2:0]
end
- attribute \src "libresoc.v:50904.3-50905.41"
- process $proc$libresoc.v:50904$1691
+ attribute \src "libresoc.v:50907.3-50908.41"
+ process $proc$libresoc.v:50907$1692
assign { } { }
assign $0\core_xer_out[0:0] \core_xer_out$next
sync posedge \clk
update \core_xer_out $0\core_xer_out[0:0]
end
- attribute \src "libresoc.v:50906.3-50907.37"
- process $proc$libresoc.v:50906$1692
+ attribute \src "libresoc.v:50909.3-50910.37"
+ process $proc$libresoc.v:50909$1693
assign { } { }
assign $0\core_fast1[2:0] \core_fast1$next
sync posedge \clk
update \core_fast1 $0\core_fast1[2:0]
end
- attribute \src "libresoc.v:50908.3-50909.43"
- process $proc$libresoc.v:50908$1693
+ attribute \src "libresoc.v:50911.3-50912.43"
+ process $proc$libresoc.v:50911$1694
assign { } { }
assign $0\core_fast1_ok[0:0] \core_fast1_ok$next
sync posedge \clk
update \core_fast1_ok $0\core_fast1_ok[0:0]
end
- attribute \src "libresoc.v:50910.3-50911.37"
- process $proc$libresoc.v:50910$1694
+ attribute \src "libresoc.v:50913.3-50914.37"
+ process $proc$libresoc.v:50913$1695
assign { } { }
assign $0\core_fast2[2:0] \core_fast2$next
sync posedge \clk
update \core_fast2 $0\core_fast2[2:0]
end
- attribute \src "libresoc.v:50912.3-50913.43"
- process $proc$libresoc.v:50912$1695
+ attribute \src "libresoc.v:50915.3-50916.43"
+ process $proc$libresoc.v:50915$1696
assign { } { }
assign $0\core_fast2_ok[0:0] \core_fast2_ok$next
sync posedge \clk
update \core_fast2_ok $0\core_fast2_ok[0:0]
end
- attribute \src "libresoc.v:50914.3-50915.39"
- process $proc$libresoc.v:50914$1696
+ attribute \src "libresoc.v:50917.3-50918.39"
+ process $proc$libresoc.v:50917$1697
assign { } { }
assign $0\core_fasto1[2:0] \core_fasto1$next
sync posedge \clk
update \core_fasto1 $0\core_fasto1[2:0]
end
- attribute \src "libresoc.v:50916.3-50917.45"
- process $proc$libresoc.v:50916$1697
+ attribute \src "libresoc.v:50919.3-50920.45"
+ process $proc$libresoc.v:50919$1698
assign { } { }
assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next
sync posedge \clk
update \core_fasto1_ok $0\core_fasto1_ok[0:0]
end
- attribute \src "libresoc.v:50918.3-50919.37"
- process $proc$libresoc.v:50918$1698
+ attribute \src "libresoc.v:50921.3-50922.37"
+ process $proc$libresoc.v:50921$1699
assign { } { }
assign $0\d_cr_delay[0:0] \d_cr_delay$next
sync posedge \clk
update \d_cr_delay $0\d_cr_delay[0:0]
end
- attribute \src "libresoc.v:50920.3-50921.39"
- process $proc$libresoc.v:50920$1699
+ attribute \src "libresoc.v:50923.3-50924.39"
+ process $proc$libresoc.v:50923$1700
assign { } { }
assign $0\core_fasto2[2:0] \core_fasto2$next
sync posedge \clk
update \core_fasto2 $0\core_fasto2[2:0]
end
- attribute \src "libresoc.v:50922.3-50923.45"
- process $proc$libresoc.v:50922$1700
+ attribute \src "libresoc.v:50925.3-50926.45"
+ process $proc$libresoc.v:50925$1701
assign { } { }
assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next
sync posedge \clk
update \core_fasto2_ok $0\core_fasto2_ok[0:0]
end
- attribute \src "libresoc.v:50924.3-50925.39"
- process $proc$libresoc.v:50924$1701
+ attribute \src "libresoc.v:50927.3-50928.39"
+ process $proc$libresoc.v:50927$1702
assign { } { }
assign $0\core_cr_in1[2:0] \core_cr_in1$next
sync posedge \clk
update \core_cr_in1 $0\core_cr_in1[2:0]
end
- attribute \src "libresoc.v:50926.3-50927.45"
- process $proc$libresoc.v:50926$1702
+ attribute \src "libresoc.v:50929.3-50930.45"
+ process $proc$libresoc.v:50929$1703
assign { } { }
assign $0\core_cr_in1_ok[0:0] \core_cr_in1_ok$next
sync posedge \clk
update \core_cr_in1_ok $0\core_cr_in1_ok[0:0]
end
- attribute \src "libresoc.v:50928.3-50929.39"
- process $proc$libresoc.v:50928$1703
+ attribute \src "libresoc.v:50931.3-50932.39"
+ process $proc$libresoc.v:50931$1704
assign { } { }
assign $0\core_cr_in2[2:0] \core_cr_in2$next
sync posedge \clk
update \core_cr_in2 $0\core_cr_in2[2:0]
end
- attribute \src "libresoc.v:50930.3-50931.45"
- process $proc$libresoc.v:50930$1704
+ attribute \src "libresoc.v:50933.3-50934.45"
+ process $proc$libresoc.v:50933$1705
assign { } { }
assign $0\core_cr_in2_ok[0:0] \core_cr_in2_ok$next
sync posedge \clk
update \core_cr_in2_ok $0\core_cr_in2_ok[0:0]
end
- attribute \src "libresoc.v:50932.3-50933.47"
- process $proc$libresoc.v:50932$1705
+ attribute \src "libresoc.v:50935.3-50936.47"
+ process $proc$libresoc.v:50935$1706
assign { } { }
- assign $0\core_cr_in2$48[2:0]$1706 \core_cr_in2$48$next
+ assign $0\core_cr_in2$48[2:0]$1707 \core_cr_in2$48$next
sync posedge \clk
- update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$1706
+ update \core_cr_in2$48 $0\core_cr_in2$48[2:0]$1707
end
- attribute \src "libresoc.v:50934.3-50935.53"
- process $proc$libresoc.v:50934$1707
+ attribute \src "libresoc.v:50937.3-50938.53"
+ process $proc$libresoc.v:50937$1708
assign { } { }
- assign $0\core_cr_in2_ok$49[0:0]$1708 \core_cr_in2_ok$49$next
+ assign $0\core_cr_in2_ok$49[0:0]$1709 \core_cr_in2_ok$49$next
sync posedge \clk
- update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$1708
+ update \core_cr_in2_ok$49 $0\core_cr_in2_ok$49[0:0]$1709
end
- attribute \src "libresoc.v:50936.3-50937.39"
- process $proc$libresoc.v:50936$1709
+ attribute \src "libresoc.v:50939.3-50940.39"
+ process $proc$libresoc.v:50939$1710
assign { } { }
assign $0\core_cr_out[2:0] \core_cr_out$next
sync posedge \clk
update \core_cr_out $0\core_cr_out[2:0]
end
- attribute \src "libresoc.v:50938.3-50939.45"
- process $proc$libresoc.v:50938$1710
+ attribute \src "libresoc.v:50941.3-50942.45"
+ process $proc$libresoc.v:50941$1711
assign { } { }
assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next
sync posedge \clk
update \core_cr_out_ok $0\core_cr_out_ok[0:0]
end
- attribute \src "libresoc.v:50940.3-50941.39"
- process $proc$libresoc.v:50940$1711
+ attribute \src "libresoc.v:50943.3-50944.39"
+ process $proc$libresoc.v:50943$1712
assign { } { }
assign $0\d_reg_delay[0:0] \d_reg_delay$next
sync posedge \clk
update \d_reg_delay $0\d_reg_delay[0:0]
end
- attribute \src "libresoc.v:50942.3-50943.43"
- process $proc$libresoc.v:50942$1712
+ attribute \src "libresoc.v:50945.3-50946.43"
+ process $proc$libresoc.v:50945$1713
assign { } { }
assign $0\core_core_msr[63:0] \core_core_msr$next
sync posedge \clk
update \core_core_msr $0\core_core_msr[63:0]
end
- attribute \src "libresoc.v:50944.3-50945.43"
- process $proc$libresoc.v:50944$1713
+ attribute \src "libresoc.v:50947.3-50948.43"
+ process $proc$libresoc.v:50947$1714
assign { } { }
assign $0\core_core_cia[63:0] \core_core_cia$next
sync posedge \clk
update \core_core_cia $0\core_core_cia[63:0]
end
- attribute \src "libresoc.v:50946.3-50947.45"
- process $proc$libresoc.v:50946$1714
+ attribute \src "libresoc.v:50949.3-50950.45"
+ process $proc$libresoc.v:50949$1715
assign { } { }
assign $0\core_core_insn[31:0] \core_core_insn$next
sync posedge \clk
update \core_core_insn $0\core_core_insn[31:0]
end
- attribute \src "libresoc.v:50948.3-50949.55"
- process $proc$libresoc.v:50948$1715
+ attribute \src "libresoc.v:50951.3-50952.55"
+ process $proc$libresoc.v:50951$1716
assign { } { }
assign $0\core_core_insn_type[6:0] \core_core_insn_type$next
sync posedge \clk
update \core_core_insn_type $0\core_core_insn_type[6:0]
end
- attribute \src "libresoc.v:50950.3-50951.51"
- process $proc$libresoc.v:50950$1716
+ attribute \src "libresoc.v:50953.3-50954.51"
+ process $proc$libresoc.v:50953$1717
assign { } { }
assign $0\core_core_fn_unit[11:0] \core_core_fn_unit$next
sync posedge \clk
update \core_core_fn_unit $0\core_core_fn_unit[11:0]
end
- attribute \src "libresoc.v:50952.3-50953.41"
- process $proc$libresoc.v:50952$1717
+ attribute \src "libresoc.v:50955.3-50956.41"
+ process $proc$libresoc.v:50955$1718
assign { } { }
assign $0\core_core_lk[0:0] \core_core_lk$next
sync posedge \clk
update \core_core_lk $0\core_core_lk[0:0]
end
- attribute \src "libresoc.v:50954.3-50955.41"
- process $proc$libresoc.v:50954$1718
+ attribute \src "libresoc.v:50957.3-50958.41"
+ process $proc$libresoc.v:50957$1719
assign { } { }
assign $0\core_core_rc[0:0] \core_core_rc$next
sync posedge \clk
update \core_core_rc $0\core_core_rc[0:0]
end
- attribute \src "libresoc.v:50956.3-50957.47"
- process $proc$libresoc.v:50956$1719
+ attribute \src "libresoc.v:50959.3-50960.47"
+ process $proc$libresoc.v:50959$1720
assign { } { }
assign $0\core_core_rc_ok[0:0] \core_core_rc_ok$next
sync posedge \clk
update \core_core_rc_ok $0\core_core_rc_ok[0:0]
end
- attribute \src "libresoc.v:50958.3-50959.41"
- process $proc$libresoc.v:50958$1720
+ attribute \src "libresoc.v:50961.3-50962.41"
+ process $proc$libresoc.v:50961$1721
assign { } { }
assign $0\core_core_oe[0:0] \core_core_oe$next
sync posedge \clk
update \core_core_oe $0\core_core_oe[0:0]
end
- attribute \src "libresoc.v:50960.3-50961.47"
- process $proc$libresoc.v:50960$1721
+ attribute \src "libresoc.v:50963.3-50964.47"
+ process $proc$libresoc.v:50963$1722
assign { } { }
assign $0\core_core_oe_ok[0:0] \core_core_oe_ok$next
sync posedge \clk
update \core_core_oe_ok $0\core_core_oe_ok[0:0]
end
- attribute \src "libresoc.v:50962.3-50963.29"
- process $proc$libresoc.v:50962$1722
+ attribute \src "libresoc.v:50965.3-50966.29"
+ process $proc$libresoc.v:50965$1723
assign { } { }
assign $0\ilatch[31:0] \ilatch$next
sync posedge \clk
update \ilatch $0\ilatch[31:0]
end
- attribute \src "libresoc.v:50964.3-50965.59"
- process $proc$libresoc.v:50964$1723
+ attribute \src "libresoc.v:50967.3-50968.59"
+ process $proc$libresoc.v:50967$1724
assign { } { }
assign $0\core_core_input_carry[1:0] \core_core_input_carry$next
sync posedge \clk
update \core_core_input_carry $0\core_core_input_carry[1:0]
end
- attribute \src "libresoc.v:50966.3-50967.53"
- process $proc$libresoc.v:50966$1724
+ attribute \src "libresoc.v:50969.3-50970.53"
+ process $proc$libresoc.v:50969$1725
assign { } { }
assign $0\core_core_traptype[7:0] \core_core_traptype$next
sync posedge \clk
update \core_core_traptype $0\core_core_traptype[7:0]
end
- attribute \src "libresoc.v:50968.3-50969.61"
- process $proc$libresoc.v:50968$1725
+ attribute \src "libresoc.v:50971.3-50972.61"
+ process $proc$libresoc.v:50971$1726
assign { } { }
- assign $0\core_core_exc_$signal[0:0]$1726 \core_core_exc_$signal$next
+ assign $0\core_core_exc_$signal[0:0]$1727 \core_core_exc_$signal$next
sync posedge \clk
- update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$1726
+ update \core_core_exc_$signal $0\core_core_exc_$signal[0:0]$1727
end
- attribute \src "libresoc.v:50970.3-50971.67"
- process $proc$libresoc.v:50970$1727
+ attribute \src "libresoc.v:50973.3-50974.67"
+ process $proc$libresoc.v:50973$1728
assign { } { }
- assign $0\core_core_exc_$signal$50[0:0]$1728 \core_core_exc_$signal$50$next
+ assign $0\core_core_exc_$signal$50[0:0]$1729 \core_core_exc_$signal$50$next
sync posedge \clk
- update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$1728
+ update \core_core_exc_$signal$50 $0\core_core_exc_$signal$50[0:0]$1729
end
- attribute \src "libresoc.v:50972.3-50973.67"
- process $proc$libresoc.v:50972$1729
+ attribute \src "libresoc.v:50975.3-50976.67"
+ process $proc$libresoc.v:50975$1730
assign { } { }
- assign $0\core_core_exc_$signal$51[0:0]$1730 \core_core_exc_$signal$51$next
+ assign $0\core_core_exc_$signal$51[0:0]$1731 \core_core_exc_$signal$51$next
sync posedge \clk
- update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$1730
+ update \core_core_exc_$signal$51 $0\core_core_exc_$signal$51[0:0]$1731
end
- attribute \src "libresoc.v:50974.3-50975.67"
- process $proc$libresoc.v:50974$1731
+ attribute \src "libresoc.v:50977.3-50978.67"
+ process $proc$libresoc.v:50977$1732
assign { } { }
- assign $0\core_core_exc_$signal$52[0:0]$1732 \core_core_exc_$signal$52$next
+ assign $0\core_core_exc_$signal$52[0:0]$1733 \core_core_exc_$signal$52$next
sync posedge \clk
- update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$1732
+ update \core_core_exc_$signal$52 $0\core_core_exc_$signal$52[0:0]$1733
end
- attribute \src "libresoc.v:50976.3-50977.67"
- process $proc$libresoc.v:50976$1733
+ attribute \src "libresoc.v:50979.3-50980.67"
+ process $proc$libresoc.v:50979$1734
assign { } { }
- assign $0\core_core_exc_$signal$53[0:0]$1734 \core_core_exc_$signal$53$next
+ assign $0\core_core_exc_$signal$53[0:0]$1735 \core_core_exc_$signal$53$next
sync posedge \clk
- update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$1734
+ update \core_core_exc_$signal$53 $0\core_core_exc_$signal$53[0:0]$1735
end
- attribute \src "libresoc.v:50978.3-50979.67"
- process $proc$libresoc.v:50978$1735
+ attribute \src "libresoc.v:50981.3-50982.67"
+ process $proc$libresoc.v:50981$1736
assign { } { }
- assign $0\core_core_exc_$signal$54[0:0]$1736 \core_core_exc_$signal$54$next
+ assign $0\core_core_exc_$signal$54[0:0]$1737 \core_core_exc_$signal$54$next
sync posedge \clk
- update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$1736
+ update \core_core_exc_$signal$54 $0\core_core_exc_$signal$54[0:0]$1737
end
- attribute \src "libresoc.v:50980.3-50981.67"
- process $proc$libresoc.v:50980$1737
+ attribute \src "libresoc.v:50983.3-50984.67"
+ process $proc$libresoc.v:50983$1738
assign { } { }
- assign $0\core_core_exc_$signal$55[0:0]$1738 \core_core_exc_$signal$55$next
+ assign $0\core_core_exc_$signal$55[0:0]$1739 \core_core_exc_$signal$55$next
sync posedge \clk
- update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$1738
+ update \core_core_exc_$signal$55 $0\core_core_exc_$signal$55[0:0]$1739
end
- attribute \src "libresoc.v:50982.3-50983.67"
- process $proc$libresoc.v:50982$1739
+ attribute \src "libresoc.v:50985.3-50986.67"
+ process $proc$libresoc.v:50985$1740
assign { } { }
- assign $0\core_core_exc_$signal$56[0:0]$1740 \core_core_exc_$signal$56$next
+ assign $0\core_core_exc_$signal$56[0:0]$1741 \core_core_exc_$signal$56$next
sync posedge \clk
- update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$1740
+ update \core_core_exc_$signal$56 $0\core_core_exc_$signal$56[0:0]$1741
end
- attribute \src "libresoc.v:50984.3-50985.31"
- process $proc$libresoc.v:50984$1741
+ attribute \src "libresoc.v:50987.3-50988.31"
+ process $proc$libresoc.v:50987$1742
assign { } { }
assign $0\core_pc[63:0] \core_pc$next
sync posedge \clk
update \core_pc $0\core_pc[63:0]
end
- attribute \src "libresoc.v:50986.3-50987.53"
- process $proc$libresoc.v:50986$1742
+ attribute \src "libresoc.v:50989.3-50990.53"
+ process $proc$libresoc.v:50989$1743
assign { } { }
assign $0\core_core_trapaddr[12:0] \core_core_trapaddr$next
sync posedge \clk
update \core_core_trapaddr $0\core_core_trapaddr[12:0]
end
- attribute \src "libresoc.v:50988.3-50989.47"
- process $proc$libresoc.v:50988$1743
+ attribute \src "libresoc.v:50991.3-50992.47"
+ process $proc$libresoc.v:50991$1744
assign { } { }
assign $0\core_core_cr_rd[7:0] \core_core_cr_rd$next
sync posedge \clk
update \core_core_cr_rd $0\core_core_cr_rd[7:0]
end
- attribute \src "libresoc.v:50990.3-50991.53"
- process $proc$libresoc.v:50990$1744
+ attribute \src "libresoc.v:50993.3-50994.53"
+ process $proc$libresoc.v:50993$1745
assign { } { }
assign $0\core_core_cr_rd_ok[0:0] \core_core_cr_rd_ok$next
sync posedge \clk
update \core_core_cr_rd_ok $0\core_core_cr_rd_ok[0:0]
end
- attribute \src "libresoc.v:50992.3-50993.47"
- process $proc$libresoc.v:50992$1745
+ attribute \src "libresoc.v:50995.3-50996.47"
+ process $proc$libresoc.v:50995$1746
assign { } { }
assign $0\core_core_cr_wr[7:0] \core_core_cr_wr$next
sync posedge \clk
update \core_core_cr_wr $0\core_core_cr_wr[7:0]
end
- attribute \src "libresoc.v:50994.3-50995.53"
- process $proc$libresoc.v:50994$1746
+ attribute \src "libresoc.v:50997.3-50998.53"
+ process $proc$libresoc.v:50997$1747
assign { } { }
assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next
sync posedge \clk
update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0]
end
- attribute \src "libresoc.v:50996.3-50997.53"
- process $proc$libresoc.v:50996$1747
+ attribute \src "libresoc.v:50999.3-51000.53"
+ process $proc$libresoc.v:50999$1748
assign { } { }
assign $0\core_core_is_32bit[0:0] \core_core_is_32bit$next
sync posedge \clk
update \core_core_is_32bit $0\core_core_is_32bit[0:0]
end
- attribute \src "libresoc.v:50998.3-50999.37"
- process $proc$libresoc.v:50998$1748
+ attribute \src "libresoc.v:51001.3-51002.37"
+ process $proc$libresoc.v:51001$1749
assign { } { }
assign $0\pc_changed[0:0] \pc_changed$next
sync posedge \clk
update \pc_changed $0\pc_changed[0:0]
end
- attribute \src "libresoc.v:51000.3-51001.39"
- process $proc$libresoc.v:51000$1749
+ attribute \src "libresoc.v:51003.3-51004.39"
+ process $proc$libresoc.v:51003$1750
assign { } { }
assign $0\pc_ok_delay[0:0] \pc_ok_delay$next
sync posedge \clk
update \pc_ok_delay $0\pc_ok_delay[0:0]
end
- attribute \src "libresoc.v:51002.3-51003.30"
- process $proc$libresoc.v:51002$1750
+ attribute \src "libresoc.v:51005.3-51006.30"
+ process $proc$libresoc.v:51005$1751
assign { } { }
assign $0\cu_st__rel_o_dly[0:0] 1'0
sync posedge \clk
update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0]
end
- attribute \src "libresoc.v:51004.3-51005.27"
- process $proc$libresoc.v:51004$1751
+ attribute \src "libresoc.v:51007.3-51008.27"
+ process $proc$libresoc.v:51007$1752
assign { } { }
assign $0\delay[1:0] \delay$next
sync posedge \por_clk
update \delay $0\delay[1:0]
end
- attribute \src "libresoc.v:51006.3-51007.33"
- process $proc$libresoc.v:51006$1752
+ attribute \src "libresoc.v:51009.3-51010.33"
+ process $proc$libresoc.v:51009$1753
assign { } { }
assign $0\core_msr[63:0] \core_msr$next
sync posedge \clk
update \core_msr $0\core_msr[63:0]
end
- attribute \src "libresoc.v:51008.3-51009.43"
- process $proc$libresoc.v:51008$1753
+ attribute \src "libresoc.v:51011.3-51012.43"
+ process $proc$libresoc.v:51011$1754
assign { } { }
assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next
sync posedge \clk
update \dec2_cur_eint $0\dec2_cur_eint[0:0]
end
- attribute \src "libresoc.v:51010.3-51011.47"
- process $proc$libresoc.v:51010$1754
+ attribute \src "libresoc.v:51013.3-51014.47"
+ process $proc$libresoc.v:51013$1755
assign { } { }
assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next
sync posedge \clk
update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0]
end
- attribute \src "libresoc.v:51012.3-51013.49"
- process $proc$libresoc.v:51012$1755
+ attribute \src "libresoc.v:51015.3-51016.49"
+ process $proc$libresoc.v:51015$1756
assign { } { }
assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next
sync posedge \clk
update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0]
end
- attribute \src "libresoc.v:51014.3-51015.39"
- process $proc$libresoc.v:51014$1756
+ attribute \src "libresoc.v:51017.3-51018.39"
+ process $proc$libresoc.v:51017$1757
assign { } { }
assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next
sync posedge \clk
update \dbg_dmi_din $0\dbg_dmi_din[63:0]
end
- attribute \src "libresoc.v:51016.3-51017.41"
- process $proc$libresoc.v:51016$1757
+ attribute \src "libresoc.v:51019.3-51020.41"
+ process $proc$libresoc.v:51019$1758
assign { } { }
assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next
sync posedge \clk
update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0]
end
- attribute \src "libresoc.v:51018.3-51019.43"
- process $proc$libresoc.v:51018$1758
+ attribute \src "libresoc.v:51021.3-51022.43"
+ process $proc$libresoc.v:51021$1759
assign { } { }
assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next
sync posedge \clk
update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0]
end
- attribute \src "libresoc.v:51020.3-51021.45"
- process $proc$libresoc.v:51020$1759
+ attribute \src "libresoc.v:51023.3-51024.45"
+ process $proc$libresoc.v:51023$1760
assign { } { }
assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next
sync posedge \clk
update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0]
end
- attribute \src "libresoc.v:51022.3-51023.35"
- process $proc$libresoc.v:51022$1760
+ attribute \src "libresoc.v:51025.3-51026.35"
+ process $proc$libresoc.v:51025$1761
assign { } { }
assign $0\core_eint[0:0] \core_eint$next
sync posedge \clk
update \core_eint $0\core_eint[0:0]
end
- attribute \src "libresoc.v:51498.3-51506.6"
- process $proc$libresoc.v:51498$1761
+ attribute \src "libresoc.v:51501.3-51509.6"
+ process $proc$libresoc.v:51501$1762
assign { } { }
assign { } { }
- assign $0\dbg_dmi_addr_i$next[3:0]$1762 $1\dbg_dmi_addr_i$next[3:0]$1763
- attribute \src "libresoc.v:51499.5-51499.29"
+ assign $0\dbg_dmi_addr_i$next[3:0]$1763 $1\dbg_dmi_addr_i$next[3:0]$1764
+ attribute \src "libresoc.v:51502.5-51502.29"
switch \initial
- attribute \src "libresoc.v:51499.9-51499.17"
+ attribute \src "libresoc.v:51502.9-51502.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_addr_i$next[3:0]$1763 4'0000
+ assign $1\dbg_dmi_addr_i$next[3:0]$1764 4'0000
case
- assign $1\dbg_dmi_addr_i$next[3:0]$1763 \jtag_dmi0__addr_i
+ assign $1\dbg_dmi_addr_i$next[3:0]$1764 \jtag_dmi0__addr_i
end
sync always
- update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1762
+ update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$1763
end
- attribute \src "libresoc.v:51507.3-51515.6"
- process $proc$libresoc.v:51507$1764
+ attribute \src "libresoc.v:51510.3-51518.6"
+ process $proc$libresoc.v:51510$1765
assign { } { }
assign { } { }
- assign $0\dbg_dmi_req_i$next[0:0]$1765 $1\dbg_dmi_req_i$next[0:0]$1766
- attribute \src "libresoc.v:51508.5-51508.29"
+ assign $0\dbg_dmi_req_i$next[0:0]$1766 $1\dbg_dmi_req_i$next[0:0]$1767
+ attribute \src "libresoc.v:51511.5-51511.29"
switch \initial
- attribute \src "libresoc.v:51508.9-51508.17"
+ attribute \src "libresoc.v:51511.9-51511.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_req_i$next[0:0]$1766 1'0
+ assign $1\dbg_dmi_req_i$next[0:0]$1767 1'0
case
- assign $1\dbg_dmi_req_i$next[0:0]$1766 \jtag_dmi0__req_i
+ assign $1\dbg_dmi_req_i$next[0:0]$1767 \jtag_dmi0__req_i
end
sync always
- update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1765
+ update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$1766
end
- attribute \src "libresoc.v:51516.3-51536.6"
- process $proc$libresoc.v:51516$1767
+ attribute \src "libresoc.v:51519.3-51539.6"
+ process $proc$libresoc.v:51519$1768
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_msr$next[63:0]$1768 $3\dec2_cur_msr$next[63:0]$1771
- attribute \src "libresoc.v:51517.5-51517.29"
+ assign $0\dec2_cur_msr$next[63:0]$1769 $3\dec2_cur_msr$next[63:0]$1772
+ attribute \src "libresoc.v:51520.5-51520.29"
switch \initial
- attribute \src "libresoc.v:51517.9-51517.17"
+ attribute \src "libresoc.v:51520.9-51520.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_msr$next[63:0]$1769 $2\dec2_cur_msr$next[63:0]$1770
+ assign $1\dec2_cur_msr$next[63:0]$1770 $2\dec2_cur_msr$next[63:0]$1771
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
switch \$115
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_msr$next[63:0]$1770 \msr__data_o
+ assign $2\dec2_cur_msr$next[63:0]$1771 \msr__data_o
case
- assign $2\dec2_cur_msr$next[63:0]$1770 \dec2_cur_msr
+ assign $2\dec2_cur_msr$next[63:0]$1771 \dec2_cur_msr
end
case
- assign $1\dec2_cur_msr$next[63:0]$1769 \dec2_cur_msr
+ assign $1\dec2_cur_msr$next[63:0]$1770 \dec2_cur_msr
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_msr$next[63:0]$1771 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_msr$next[63:0]$1772 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_msr$next[63:0]$1771 $1\dec2_cur_msr$next[63:0]$1769
+ assign $3\dec2_cur_msr$next[63:0]$1772 $1\dec2_cur_msr$next[63:0]$1770
end
sync always
- update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1768
+ update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$1769
end
- attribute \src "libresoc.v:51537.3-51555.6"
- process $proc$libresoc.v:51537$1772
+ attribute \src "libresoc.v:51540.3-51558.6"
+ process $proc$libresoc.v:51540$1773
assign { } { }
assign { } { }
assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0]
- attribute \src "libresoc.v:51538.5-51538.29"
+ attribute \src "libresoc.v:51541.5-51541.29"
switch \initial
- attribute \src "libresoc.v:51538.9-51538.17"
+ attribute \src "libresoc.v:51541.9-51541.17"
case 1'1
case
end
sync always
update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0]
end
- attribute \src "libresoc.v:51556.3-51587.6"
- process $proc$libresoc.v:51556$1773
+ attribute \src "libresoc.v:51559.3-51590.6"
+ process $proc$libresoc.v:51559$1774
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_dec$next[63:0]$1774 $3\core_dec$next[63:0]$1786
- assign $0\core_eint$next[0:0]$1775 $3\core_eint$next[0:0]$1787
- assign $0\core_msr$next[63:0]$1776 $3\core_msr$next[63:0]$1788
- assign $0\core_pc$next[63:0]$1777 $3\core_pc$next[63:0]$1789
- attribute \src "libresoc.v:51557.5-51557.29"
+ assign $0\core_dec$next[63:0]$1775 $3\core_dec$next[63:0]$1787
+ assign $0\core_eint$next[0:0]$1776 $3\core_eint$next[0:0]$1788
+ assign $0\core_msr$next[63:0]$1777 $3\core_msr$next[63:0]$1789
+ assign $0\core_pc$next[63:0]$1778 $3\core_pc$next[63:0]$1790
+ attribute \src "libresoc.v:51560.5-51560.29"
switch \initial
- attribute \src "libresoc.v:51557.9-51557.17"
+ attribute \src "libresoc.v:51560.9-51560.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_dec$next[63:0]$1778 $2\core_dec$next[63:0]$1782
- assign $1\core_eint$next[0:0]$1779 $2\core_eint$next[0:0]$1783
- assign $1\core_msr$next[63:0]$1780 $2\core_msr$next[63:0]$1784
- assign $1\core_pc$next[63:0]$1781 $2\core_pc$next[63:0]$1785
+ assign $1\core_dec$next[63:0]$1779 $2\core_dec$next[63:0]$1783
+ assign $1\core_eint$next[0:0]$1780 $2\core_eint$next[0:0]$1784
+ assign $1\core_msr$next[63:0]$1781 $2\core_msr$next[63:0]$1785
+ assign $1\core_pc$next[63:0]$1782 $2\core_pc$next[63:0]$1786
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\core_dec$next[63:0]$1782 \core_dec
- assign $2\core_eint$next[0:0]$1783 \core_eint
- assign $2\core_msr$next[63:0]$1784 \core_msr
- assign $2\core_pc$next[63:0]$1785 \core_pc
+ assign $2\core_dec$next[63:0]$1783 \core_dec
+ assign $2\core_eint$next[0:0]$1784 \core_eint
+ assign $2\core_msr$next[63:0]$1785 \core_msr
+ assign $2\core_pc$next[63:0]$1786 \core_pc
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_dec$next[63:0]$1782 $2\core_eint$next[0:0]$1783 $2\core_msr$next[63:0]$1784 $2\core_pc$next[63:0]$1785 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
+ assign { $2\core_dec$next[63:0]$1783 $2\core_eint$next[0:0]$1784 $2\core_msr$next[63:0]$1785 $2\core_pc$next[63:0]$1786 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc }
end
case
- assign $1\core_dec$next[63:0]$1778 \core_dec
- assign $1\core_eint$next[0:0]$1779 \core_eint
- assign $1\core_msr$next[63:0]$1780 \core_msr
- assign $1\core_pc$next[63:0]$1781 \core_pc
+ assign $1\core_dec$next[63:0]$1779 \core_dec
+ assign $1\core_eint$next[0:0]$1780 \core_eint
+ assign $1\core_msr$next[63:0]$1781 \core_msr
+ assign $1\core_pc$next[63:0]$1782 \core_pc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $3\core_pc$next[63:0]$1789 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_msr$next[63:0]$1788 64'0000000000000000000000000000000000000000000000000000000000000000
- assign $3\core_eint$next[0:0]$1787 1'0
- assign $3\core_dec$next[63:0]$1786 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_pc$next[63:0]$1790 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_msr$next[63:0]$1789 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\core_eint$next[0:0]$1788 1'0
+ assign $3\core_dec$next[63:0]$1787 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\core_dec$next[63:0]$1786 $1\core_dec$next[63:0]$1778
- assign $3\core_eint$next[0:0]$1787 $1\core_eint$next[0:0]$1779
- assign $3\core_msr$next[63:0]$1788 $1\core_msr$next[63:0]$1780
- assign $3\core_pc$next[63:0]$1789 $1\core_pc$next[63:0]$1781
+ assign $3\core_dec$next[63:0]$1787 $1\core_dec$next[63:0]$1779
+ assign $3\core_eint$next[0:0]$1788 $1\core_eint$next[0:0]$1780
+ assign $3\core_msr$next[63:0]$1789 $1\core_msr$next[63:0]$1781
+ assign $3\core_pc$next[63:0]$1790 $1\core_pc$next[63:0]$1782
end
sync always
- update \core_dec$next $0\core_dec$next[63:0]$1774
- update \core_eint$next $0\core_eint$next[0:0]$1775
- update \core_msr$next $0\core_msr$next[63:0]$1776
- update \core_pc$next $0\core_pc$next[63:0]$1777
+ update \core_dec$next $0\core_dec$next[63:0]$1775
+ update \core_eint$next $0\core_eint$next[0:0]$1776
+ update \core_msr$next $0\core_msr$next[63:0]$1777
+ update \core_pc$next $0\core_pc$next[63:0]$1778
end
- attribute \src "libresoc.v:51588.3-51611.6"
- process $proc$libresoc.v:51588$1790
+ attribute \src "libresoc.v:51591.3-51614.6"
+ process $proc$libresoc.v:51591$1791
assign { } { }
assign { } { }
assign { } { }
- assign $0\ilatch$next[31:0]$1791 $3\ilatch$next[31:0]$1794
- attribute \src "libresoc.v:51589.5-51589.29"
+ assign $0\ilatch$next[31:0]$1792 $3\ilatch$next[31:0]$1795
+ attribute \src "libresoc.v:51592.5-51592.29"
switch \initial
- attribute \src "libresoc.v:51589.9-51589.17"
+ attribute \src "libresoc.v:51592.9-51592.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\ilatch$next[31:0]$1792 $2\ilatch$next[31:0]$1793
+ assign $1\ilatch$next[31:0]$1793 $2\ilatch$next[31:0]$1794
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\ilatch$next[31:0]$1793 \ilatch
+ assign $2\ilatch$next[31:0]$1794 \ilatch
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\ilatch$next[31:0]$1793 \$121
+ assign $2\ilatch$next[31:0]$1794 \$121
end
case
- assign $1\ilatch$next[31:0]$1792 \ilatch
+ assign $1\ilatch$next[31:0]$1793 \ilatch
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\ilatch$next[31:0]$1794 0
+ assign $3\ilatch$next[31:0]$1795 0
case
- assign $3\ilatch$next[31:0]$1794 $1\ilatch$next[31:0]$1792
+ assign $3\ilatch$next[31:0]$1795 $1\ilatch$next[31:0]$1793
end
sync always
- update \ilatch$next $0\ilatch$next[31:0]$1791
+ update \ilatch$next $0\ilatch$next[31:0]$1792
end
- attribute \src "libresoc.v:51612.3-51631.6"
- process $proc$libresoc.v:51612$1795
+ attribute \src "libresoc.v:51615.3-51634.6"
+ process $proc$libresoc.v:51615$1796
assign { } { }
assign { } { }
assign $0\ivalid_i[0:0] $1\ivalid_i[0:0]
- attribute \src "libresoc.v:51613.5-51613.29"
+ attribute \src "libresoc.v:51616.5-51616.29"
switch \initial
- attribute \src "libresoc.v:51613.9-51613.17"
+ attribute \src "libresoc.v:51616.9-51616.17"
case 1'1
case
end
sync always
update \ivalid_i $0\ivalid_i[0:0]
end
- attribute \src "libresoc.v:51632.3-51642.6"
- process $proc$libresoc.v:51632$1796
+ attribute \src "libresoc.v:51635.3-51645.6"
+ process $proc$libresoc.v:51635$1797
assign { } { }
assign { } { }
assign $0\issue_i[0:0] $1\issue_i[0:0]
- attribute \src "libresoc.v:51633.5-51633.29"
+ attribute \src "libresoc.v:51636.5-51636.29"
switch \initial
- attribute \src "libresoc.v:51633.9-51633.17"
+ attribute \src "libresoc.v:51636.9-51636.17"
case 1'1
case
end
sync always
update \issue_i $0\issue_i[0:0]
end
- attribute \src "libresoc.v:51643.3-51652.6"
- process $proc$libresoc.v:51643$1797
+ attribute \src "libresoc.v:51646.3-51655.6"
+ process $proc$libresoc.v:51646$1798
assign { } { }
assign { } { }
assign $0\dmi__addr[4:0] $1\dmi__addr[4:0]
- attribute \src "libresoc.v:51644.5-51644.29"
+ attribute \src "libresoc.v:51647.5-51647.29"
switch \initial
- attribute \src "libresoc.v:51644.9-51644.17"
+ attribute \src "libresoc.v:51647.9-51647.17"
case 1'1
case
end
sync always
update \dmi__addr $0\dmi__addr[4:0]
end
- attribute \src "libresoc.v:51653.3-51662.6"
- process $proc$libresoc.v:51653$1798
+ attribute \src "libresoc.v:51656.3-51665.6"
+ process $proc$libresoc.v:51656$1799
assign { } { }
assign { } { }
assign $0\dmi__ren[0:0] $1\dmi__ren[0:0]
- attribute \src "libresoc.v:51654.5-51654.29"
+ attribute \src "libresoc.v:51657.5-51657.29"
switch \initial
- attribute \src "libresoc.v:51654.9-51654.17"
+ attribute \src "libresoc.v:51657.9-51657.17"
case 1'1
case
end
sync always
update \dmi__ren $0\dmi__ren[0:0]
end
- attribute \src "libresoc.v:51663.3-51671.6"
- process $proc$libresoc.v:51663$1799
+ attribute \src "libresoc.v:51666.3-51674.6"
+ process $proc$libresoc.v:51666$1800
assign { } { }
assign { } { }
- assign $0\d_reg_delay$next[0:0]$1800 $1\d_reg_delay$next[0:0]$1801
- attribute \src "libresoc.v:51664.5-51664.29"
+ assign $0\d_reg_delay$next[0:0]$1801 $1\d_reg_delay$next[0:0]$1802
+ attribute \src "libresoc.v:51667.5-51667.29"
switch \initial
- attribute \src "libresoc.v:51664.9-51664.17"
+ attribute \src "libresoc.v:51667.9-51667.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_reg_delay$next[0:0]$1801 1'0
+ assign $1\d_reg_delay$next[0:0]$1802 1'0
case
- assign $1\d_reg_delay$next[0:0]$1801 \dbg_d_gpr_req
+ assign $1\d_reg_delay$next[0:0]$1802 \dbg_d_gpr_req
end
sync always
- update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1800
+ update \d_reg_delay$next $0\d_reg_delay$next[0:0]$1801
end
- attribute \src "libresoc.v:51672.3-51681.6"
- process $proc$libresoc.v:51672$1802
+ attribute \src "libresoc.v:51675.3-51684.6"
+ process $proc$libresoc.v:51675$1803
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0]
- attribute \src "libresoc.v:51673.5-51673.29"
+ attribute \src "libresoc.v:51676.5-51676.29"
switch \initial
- attribute \src "libresoc.v:51673.9-51673.17"
+ attribute \src "libresoc.v:51676.9-51676.17"
case 1'1
case
end
sync always
update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0]
end
- attribute \src "libresoc.v:51682.3-51691.6"
- process $proc$libresoc.v:51682$1803
+ attribute \src "libresoc.v:51685.3-51694.6"
+ process $proc$libresoc.v:51685$1804
assign { } { }
assign { } { }
assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0]
- attribute \src "libresoc.v:51683.5-51683.29"
+ attribute \src "libresoc.v:51686.5-51686.29"
switch \initial
- attribute \src "libresoc.v:51683.9-51683.17"
+ attribute \src "libresoc.v:51686.9-51686.17"
case 1'1
case
end
sync always
update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0]
end
- attribute \src "libresoc.v:51692.3-51701.6"
- process $proc$libresoc.v:51692$1804
+ attribute \src "libresoc.v:51695.3-51704.6"
+ process $proc$libresoc.v:51695$1805
assign { } { }
assign { } { }
assign $0\full_rd2__ren[7:0] $1\full_rd2__ren[7:0]
- attribute \src "libresoc.v:51693.5-51693.29"
+ attribute \src "libresoc.v:51696.5-51696.29"
switch \initial
- attribute \src "libresoc.v:51693.9-51693.17"
+ attribute \src "libresoc.v:51696.9-51696.17"
case 1'1
case
end
sync always
update \full_rd2__ren $0\full_rd2__ren[7:0]
end
- attribute \src "libresoc.v:51702.3-51710.6"
- process $proc$libresoc.v:51702$1805
+ attribute \src "libresoc.v:51705.3-51713.6"
+ process $proc$libresoc.v:51705$1806
assign { } { }
assign { } { }
- assign $0\d_cr_delay$next[0:0]$1806 $1\d_cr_delay$next[0:0]$1807
- attribute \src "libresoc.v:51703.5-51703.29"
+ assign $0\d_cr_delay$next[0:0]$1807 $1\d_cr_delay$next[0:0]$1808
+ attribute \src "libresoc.v:51706.5-51706.29"
switch \initial
- attribute \src "libresoc.v:51703.9-51703.17"
+ attribute \src "libresoc.v:51706.9-51706.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_cr_delay$next[0:0]$1807 1'0
+ assign $1\d_cr_delay$next[0:0]$1808 1'0
case
- assign $1\d_cr_delay$next[0:0]$1807 \dbg_d_cr_req
+ assign $1\d_cr_delay$next[0:0]$1808 \dbg_d_cr_req
end
sync always
- update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1806
+ update \d_cr_delay$next $0\d_cr_delay$next[0:0]$1807
end
- attribute \src "libresoc.v:51711.3-51720.6"
- process $proc$libresoc.v:51711$1808
+ attribute \src "libresoc.v:51714.3-51723.6"
+ process $proc$libresoc.v:51714$1809
assign { } { }
assign { } { }
assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0]
- attribute \src "libresoc.v:51712.5-51712.29"
+ attribute \src "libresoc.v:51715.5-51715.29"
switch \initial
- attribute \src "libresoc.v:51712.9-51712.17"
+ attribute \src "libresoc.v:51715.9-51715.17"
case 1'1
case
end
sync always
update \dbg_d_cr_data $0\dbg_d_cr_data[63:0]
end
- attribute \src "libresoc.v:51721.3-51730.6"
- process $proc$libresoc.v:51721$1809
+ attribute \src "libresoc.v:51724.3-51733.6"
+ process $proc$libresoc.v:51724$1810
assign { } { }
assign { } { }
assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0]
- attribute \src "libresoc.v:51722.5-51722.29"
+ attribute \src "libresoc.v:51725.5-51725.29"
switch \initial
- attribute \src "libresoc.v:51722.9-51722.17"
+ attribute \src "libresoc.v:51725.9-51725.17"
case 1'1
case
end
sync always
update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0]
end
- attribute \src "libresoc.v:51731.3-51740.6"
- process $proc$libresoc.v:51731$1810
+ attribute \src "libresoc.v:51734.3-51743.6"
+ process $proc$libresoc.v:51734$1811
assign { } { }
assign { } { }
assign $0\full_rd__ren[2:0] $1\full_rd__ren[2:0]
- attribute \src "libresoc.v:51732.5-51732.29"
+ attribute \src "libresoc.v:51735.5-51735.29"
switch \initial
- attribute \src "libresoc.v:51732.9-51732.17"
+ attribute \src "libresoc.v:51735.9-51735.17"
case 1'1
case
end
sync always
update \full_rd__ren $0\full_rd__ren[2:0]
end
- attribute \src "libresoc.v:51741.3-51749.6"
- process $proc$libresoc.v:51741$1811
+ attribute \src "libresoc.v:51744.3-51752.6"
+ process $proc$libresoc.v:51744$1812
assign { } { }
assign { } { }
- assign $0\d_xer_delay$next[0:0]$1812 $1\d_xer_delay$next[0:0]$1813
- attribute \src "libresoc.v:51742.5-51742.29"
+ assign $0\d_xer_delay$next[0:0]$1813 $1\d_xer_delay$next[0:0]$1814
+ attribute \src "libresoc.v:51745.5-51745.29"
switch \initial
- attribute \src "libresoc.v:51742.9-51742.17"
+ attribute \src "libresoc.v:51745.9-51745.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\d_xer_delay$next[0:0]$1813 1'0
+ assign $1\d_xer_delay$next[0:0]$1814 1'0
case
- assign $1\d_xer_delay$next[0:0]$1813 \dbg_d_xer_req
+ assign $1\d_xer_delay$next[0:0]$1814 \dbg_d_xer_req
end
sync always
- update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1812
+ update \d_xer_delay$next $0\d_xer_delay$next[0:0]$1813
end
- attribute \src "libresoc.v:51750.3-51759.6"
- process $proc$libresoc.v:51750$1814
+ attribute \src "libresoc.v:51753.3-51762.6"
+ process $proc$libresoc.v:51753$1815
assign { } { }
assign { } { }
assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0]
- attribute \src "libresoc.v:51751.5-51751.29"
+ attribute \src "libresoc.v:51754.5-51754.29"
switch \initial
- attribute \src "libresoc.v:51751.9-51751.17"
+ attribute \src "libresoc.v:51754.9-51754.17"
case 1'1
case
end
sync always
update \dbg_d_xer_data $0\dbg_d_xer_data[63:0]
end
- attribute \src "libresoc.v:51760.3-51769.6"
- process $proc$libresoc.v:51760$1815
+ attribute \src "libresoc.v:51763.3-51772.6"
+ process $proc$libresoc.v:51763$1816
assign { } { }
assign { } { }
assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0]
- attribute \src "libresoc.v:51761.5-51761.29"
+ attribute \src "libresoc.v:51764.5-51764.29"
switch \initial
- attribute \src "libresoc.v:51761.9-51761.17"
+ attribute \src "libresoc.v:51764.9-51764.17"
case 1'1
case
end
sync always
update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0]
end
- attribute \src "libresoc.v:51770.3-51784.6"
- process $proc$libresoc.v:51770$1816
+ attribute \src "libresoc.v:51773.3-51787.6"
+ process $proc$libresoc.v:51773$1817
assign { } { }
assign { } { }
assign $0\issue__addr[2:0] $1\issue__addr[2:0]
- attribute \src "libresoc.v:51771.5-51771.29"
+ attribute \src "libresoc.v:51774.5-51774.29"
switch \initial
- attribute \src "libresoc.v:51771.9-51771.17"
+ attribute \src "libresoc.v:51774.9-51774.17"
case 1'1
case
end
sync always
update \issue__addr $0\issue__addr[2:0]
end
- attribute \src "libresoc.v:51785.3-51799.6"
- process $proc$libresoc.v:51785$1817
+ attribute \src "libresoc.v:51788.3-51802.6"
+ process $proc$libresoc.v:51788$1818
assign { } { }
assign { } { }
assign $0\issue__ren[0:0] $1\issue__ren[0:0]
- attribute \src "libresoc.v:51786.5-51786.29"
+ attribute \src "libresoc.v:51789.5-51789.29"
switch \initial
- attribute \src "libresoc.v:51786.9-51786.17"
+ attribute \src "libresoc.v:51789.9-51789.17"
case 1'1
case
end
sync always
update \issue__ren $0\issue__ren[0:0]
end
- attribute \src "libresoc.v:51800.3-51827.6"
- process $proc$libresoc.v:51800$1818
+ attribute \src "libresoc.v:51803.3-51830.6"
+ process $proc$libresoc.v:51803$1819
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$131$next[1:0]$1819 $2\fsm_state$131$next[1:0]$1821
- attribute \src "libresoc.v:51801.5-51801.29"
+ assign $0\fsm_state$131$next[1:0]$1820 $2\fsm_state$131$next[1:0]$1822
+ attribute \src "libresoc.v:51804.5-51804.29"
switch \initial
- attribute \src "libresoc.v:51801.9-51801.17"
+ attribute \src "libresoc.v:51804.9-51804.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fsm_state$131$next[1:0]$1820 2'01
+ assign $1\fsm_state$131$next[1:0]$1821 2'01
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fsm_state$131$next[1:0]$1820 2'10
+ assign $1\fsm_state$131$next[1:0]$1821 2'10
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fsm_state$131$next[1:0]$1820 2'11
+ assign $1\fsm_state$131$next[1:0]$1821 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fsm_state$131$next[1:0]$1820 2'00
+ assign $1\fsm_state$131$next[1:0]$1821 2'00
case
- assign $1\fsm_state$131$next[1:0]$1820 \fsm_state$131
+ assign $1\fsm_state$131$next[1:0]$1821 \fsm_state$131
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fsm_state$131$next[1:0]$1821 2'00
+ assign $2\fsm_state$131$next[1:0]$1822 2'00
case
- assign $2\fsm_state$131$next[1:0]$1821 $1\fsm_state$131$next[1:0]$1820
+ assign $2\fsm_state$131$next[1:0]$1822 $1\fsm_state$131$next[1:0]$1821
end
sync always
- update \fsm_state$131$next $0\fsm_state$131$next[1:0]$1819
+ update \fsm_state$131$next $0\fsm_state$131$next[1:0]$1820
end
- attribute \src "libresoc.v:51828.3-51838.6"
- process $proc$libresoc.v:51828$1822
+ attribute \src "libresoc.v:51831.3-51841.6"
+ process $proc$libresoc.v:51831$1823
assign { } { }
assign { } { }
assign $0\new_dec[63:0] $1\new_dec[63:0]
- attribute \src "libresoc.v:51829.5-51829.29"
+ attribute \src "libresoc.v:51832.5-51832.29"
switch \initial
- attribute \src "libresoc.v:51829.9-51829.17"
+ attribute \src "libresoc.v:51832.9-51832.17"
case 1'1
case
end
sync always
update \new_dec $0\new_dec[63:0]
end
- attribute \src "libresoc.v:51839.3-51853.6"
- process $proc$libresoc.v:51839$1823
+ attribute \src "libresoc.v:51842.3-51856.6"
+ process $proc$libresoc.v:51842$1824
assign { } { }
assign { } { }
- assign $0\issue__addr$135[2:0]$1824 $1\issue__addr$135[2:0]$1825
- attribute \src "libresoc.v:51840.5-51840.29"
+ assign $0\issue__addr$135[2:0]$1825 $1\issue__addr$135[2:0]$1826
+ attribute \src "libresoc.v:51843.5-51843.29"
switch \initial
- attribute \src "libresoc.v:51840.9-51840.17"
+ attribute \src "libresoc.v:51843.9-51843.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\issue__addr$135[2:0]$1825 3'110
+ assign $1\issue__addr$135[2:0]$1826 3'110
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\issue__addr$135[2:0]$1825 3'111
+ assign $1\issue__addr$135[2:0]$1826 3'111
case
- assign $1\issue__addr$135[2:0]$1825 3'000
+ assign $1\issue__addr$135[2:0]$1826 3'000
end
sync always
- update \issue__addr$135 $0\issue__addr$135[2:0]$1824
+ update \issue__addr$135 $0\issue__addr$135[2:0]$1825
end
- attribute \src "libresoc.v:51854.3-51868.6"
- process $proc$libresoc.v:51854$1826
+ attribute \src "libresoc.v:51857.3-51871.6"
+ process $proc$libresoc.v:51857$1827
assign { } { }
assign { } { }
assign $0\issue__wen[0:0] $1\issue__wen[0:0]
- attribute \src "libresoc.v:51855.5-51855.29"
+ attribute \src "libresoc.v:51858.5-51858.29"
switch \initial
- attribute \src "libresoc.v:51855.9-51855.17"
+ attribute \src "libresoc.v:51858.9-51858.17"
case 1'1
case
end
sync always
update \issue__wen $0\issue__wen[0:0]
end
- attribute \src "libresoc.v:51869.3-51883.6"
- process $proc$libresoc.v:51869$1827
+ attribute \src "libresoc.v:51872.3-51886.6"
+ process $proc$libresoc.v:51872$1828
assign { } { }
assign { } { }
assign $0\issue__data_i[63:0] $1\issue__data_i[63:0]
- attribute \src "libresoc.v:51870.5-51870.29"
+ attribute \src "libresoc.v:51873.5-51873.29"
switch \initial
- attribute \src "libresoc.v:51870.9-51870.17"
+ attribute \src "libresoc.v:51873.9-51873.17"
case 1'1
case
end
sync always
update \issue__data_i $0\issue__data_i[63:0]
end
- attribute \src "libresoc.v:51884.3-51899.6"
- process $proc$libresoc.v:51884$1828
+ attribute \src "libresoc.v:51887.3-51902.6"
+ process $proc$libresoc.v:51887$1829
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_dec$next[63:0]$1829 $2\dec2_cur_dec$next[63:0]$1831
- attribute \src "libresoc.v:51885.5-51885.29"
+ assign $0\dec2_cur_dec$next[63:0]$1830 $2\dec2_cur_dec$next[63:0]$1832
+ attribute \src "libresoc.v:51888.5-51888.29"
switch \initial
- attribute \src "libresoc.v:51885.9-51885.17"
+ attribute \src "libresoc.v:51888.9-51888.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\dec2_cur_dec$next[63:0]$1830 \new_dec
+ assign $1\dec2_cur_dec$next[63:0]$1831 \new_dec
case
- assign $1\dec2_cur_dec$next[63:0]$1830 \dec2_cur_dec
+ assign $1\dec2_cur_dec$next[63:0]$1831 \dec2_cur_dec
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_dec$next[63:0]$1831 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $2\dec2_cur_dec$next[63:0]$1832 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $2\dec2_cur_dec$next[63:0]$1831 $1\dec2_cur_dec$next[63:0]$1830
+ assign $2\dec2_cur_dec$next[63:0]$1832 $1\dec2_cur_dec$next[63:0]$1831
end
sync always
- update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1829
+ update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$1830
end
- attribute \src "libresoc.v:51900.3-51910.6"
- process $proc$libresoc.v:51900$1832
+ attribute \src "libresoc.v:51903.3-51913.6"
+ process $proc$libresoc.v:51903$1833
assign { } { }
assign { } { }
assign $0\new_tb[63:0] $1\new_tb[63:0]
- attribute \src "libresoc.v:51901.5-51901.29"
+ attribute \src "libresoc.v:51904.5-51904.29"
switch \initial
- attribute \src "libresoc.v:51901.9-51901.17"
+ attribute \src "libresoc.v:51904.9-51904.17"
case 1'1
case
end
sync always
update \new_tb $0\new_tb[63:0]
end
- attribute \src "libresoc.v:51911.3-51919.6"
- process $proc$libresoc.v:51911$1833
+ attribute \src "libresoc.v:51914.3-51922.6"
+ process $proc$libresoc.v:51914$1834
assign { } { }
assign { } { }
- assign $0\dbg_dmi_we_i$next[0:0]$1834 $1\dbg_dmi_we_i$next[0:0]$1835
- attribute \src "libresoc.v:51912.5-51912.29"
+ assign $0\dbg_dmi_we_i$next[0:0]$1835 $1\dbg_dmi_we_i$next[0:0]$1836
+ attribute \src "libresoc.v:51915.5-51915.29"
switch \initial
- attribute \src "libresoc.v:51912.9-51912.17"
+ attribute \src "libresoc.v:51915.9-51915.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_we_i$next[0:0]$1835 1'0
+ assign $1\dbg_dmi_we_i$next[0:0]$1836 1'0
case
- assign $1\dbg_dmi_we_i$next[0:0]$1835 \jtag_dmi0__we_i
+ assign $1\dbg_dmi_we_i$next[0:0]$1836 \jtag_dmi0__we_i
end
sync always
- update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1834
+ update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$1835
end
- attribute \src "libresoc.v:51920.3-51928.6"
- process $proc$libresoc.v:51920$1836
+ attribute \src "libresoc.v:51923.3-51931.6"
+ process $proc$libresoc.v:51923$1837
assign { } { }
assign { } { }
- assign $0\pc_ok_delay$next[0:0]$1837 $1\pc_ok_delay$next[0:0]$1838
- attribute \src "libresoc.v:51921.5-51921.29"
+ assign $0\pc_ok_delay$next[0:0]$1838 $1\pc_ok_delay$next[0:0]$1839
+ attribute \src "libresoc.v:51924.5-51924.29"
switch \initial
- attribute \src "libresoc.v:51921.9-51921.17"
+ attribute \src "libresoc.v:51924.9-51924.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\pc_ok_delay$next[0:0]$1838 1'0
+ assign $1\pc_ok_delay$next[0:0]$1839 1'0
case
- assign $1\pc_ok_delay$next[0:0]$1838 \$28
+ assign $1\pc_ok_delay$next[0:0]$1839 \$28
end
sync always
- update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1837
+ update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$1838
end
- attribute \src "libresoc.v:51929.3-51944.6"
- process $proc$libresoc.v:51929$1839
+ attribute \src "libresoc.v:51932.3-51947.6"
+ process $proc$libresoc.v:51932$1840
assign { } { }
assign { } { }
assign { } { }
assign $0\pc[63:0] $2\pc[63:0]
- attribute \src "libresoc.v:51930.5-51930.29"
+ attribute \src "libresoc.v:51933.5-51933.29"
switch \initial
- attribute \src "libresoc.v:51930.9-51930.17"
+ attribute \src "libresoc.v:51933.9-51933.17"
case 1'1
case
end
sync always
update \pc $0\pc[63:0]
end
- attribute \src "libresoc.v:51945.3-51957.6"
- process $proc$libresoc.v:51945$1840
+ attribute \src "libresoc.v:51948.3-51960.6"
+ process $proc$libresoc.v:51948$1841
assign { } { }
assign { } { }
assign $0\cia__ren[3:0] $1\cia__ren[3:0]
- attribute \src "libresoc.v:51946.5-51946.29"
+ attribute \src "libresoc.v:51949.5-51949.29"
switch \initial
- attribute \src "libresoc.v:51946.9-51946.17"
+ attribute \src "libresoc.v:51949.9-51949.17"
case 1'1
case
end
sync always
update \cia__ren $0\cia__ren[3:0]
end
- attribute \src "libresoc.v:51958.3-51978.6"
- process $proc$libresoc.v:51958$1841
+ attribute \src "libresoc.v:51961.3-51981.6"
+ process $proc$libresoc.v:51961$1842
assign { } { }
assign { } { }
assign $0\wen[3:0] $1\wen[3:0]
- attribute \src "libresoc.v:51959.5-51959.29"
+ attribute \src "libresoc.v:51962.5-51962.29"
switch \initial
- attribute \src "libresoc.v:51959.9-51959.17"
+ attribute \src "libresoc.v:51962.9-51962.17"
case 1'1
case
end
sync always
update \wen $0\wen[3:0]
end
- attribute \src "libresoc.v:51979.3-51999.6"
- process $proc$libresoc.v:51979$1842
+ attribute \src "libresoc.v:51982.3-52002.6"
+ process $proc$libresoc.v:51982$1843
assign { } { }
assign { } { }
assign $0\data_i[63:0] $1\data_i[63:0]
- attribute \src "libresoc.v:51980.5-51980.29"
+ attribute \src "libresoc.v:51983.5-51983.29"
switch \initial
- attribute \src "libresoc.v:51980.9-51980.17"
+ attribute \src "libresoc.v:51983.9-51983.17"
case 1'1
case
end
sync always
update \data_i $0\data_i[63:0]
end
- attribute \src "libresoc.v:52000.3-52015.6"
- process $proc$libresoc.v:52000$1843
+ attribute \src "libresoc.v:52003.3-52018.6"
+ process $proc$libresoc.v:52003$1844
assign { } { }
assign { } { }
assign $0\msr__ren[3:0] $1\msr__ren[3:0]
- attribute \src "libresoc.v:52001.5-52001.29"
+ attribute \src "libresoc.v:52004.5-52004.29"
switch \initial
- attribute \src "libresoc.v:52001.9-52001.17"
+ attribute \src "libresoc.v:52004.9-52004.17"
case 1'1
case
end
sync always
update \msr__ren $0\msr__ren[3:0]
end
- attribute \src "libresoc.v:52016.3-52024.6"
- process $proc$libresoc.v:52016$1844
+ attribute \src "libresoc.v:52019.3-52027.6"
+ process $proc$libresoc.v:52019$1845
assign { } { }
assign { } { }
- assign $0\dbg_dmi_din$next[63:0]$1845 $1\dbg_dmi_din$next[63:0]$1846
- attribute \src "libresoc.v:52017.5-52017.29"
+ assign $0\dbg_dmi_din$next[63:0]$1846 $1\dbg_dmi_din$next[63:0]$1847
+ attribute \src "libresoc.v:52020.5-52020.29"
switch \initial
- attribute \src "libresoc.v:52017.9-52017.17"
+ attribute \src "libresoc.v:52020.9-52020.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dbg_dmi_din$next[63:0]$1846 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\dbg_dmi_din$next[63:0]$1847 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\dbg_dmi_din$next[63:0]$1846 \jtag_dmi0__din
+ assign $1\dbg_dmi_din$next[63:0]$1847 \jtag_dmi0__din
end
sync always
- update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1845
+ update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$1846
end
- attribute \src "libresoc.v:52025.3-52049.6"
- process $proc$libresoc.v:52025$1847
+ attribute \src "libresoc.v:52028.3-52052.6"
+ process $proc$libresoc.v:52028$1848
assign { } { }
assign { } { }
assign { } { }
- assign $0\pc_changed$next[0:0]$1848 $3\pc_changed$next[0:0]$1851
- attribute \src "libresoc.v:52026.5-52026.29"
+ assign $0\pc_changed$next[0:0]$1849 $3\pc_changed$next[0:0]$1852
+ attribute \src "libresoc.v:52029.5-52029.29"
switch \initial
- attribute \src "libresoc.v:52026.9-52026.17"
+ attribute \src "libresoc.v:52029.9-52029.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\pc_changed$next[0:0]$1849 1'0
+ assign $1\pc_changed$next[0:0]$1850 1'0
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\pc_changed$next[0:0]$1849 $2\pc_changed$next[0:0]$1850
+ assign $1\pc_changed$next[0:0]$1850 $2\pc_changed$next[0:0]$1851
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:309"
switch \$44
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\pc_changed$next[0:0]$1850 1'1
+ assign $2\pc_changed$next[0:0]$1851 1'1
case
- assign $2\pc_changed$next[0:0]$1850 \pc_changed
+ assign $2\pc_changed$next[0:0]$1851 \pc_changed
end
case
- assign $1\pc_changed$next[0:0]$1849 \pc_changed
+ assign $1\pc_changed$next[0:0]$1850 \pc_changed
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\pc_changed$next[0:0]$1851 1'0
+ assign $3\pc_changed$next[0:0]$1852 1'0
case
- assign $3\pc_changed$next[0:0]$1851 $1\pc_changed$next[0:0]$1849
+ assign $3\pc_changed$next[0:0]$1852 $1\pc_changed$next[0:0]$1850
end
sync always
- update \pc_changed$next $0\pc_changed$next[0:0]$1848
+ update \pc_changed$next $0\pc_changed$next[0:0]$1849
end
- attribute \src "libresoc.v:52050.3-52172.6"
- process $proc$libresoc.v:52050$1852
+ attribute \src "libresoc.v:52053.3-52175.6"
+ process $proc$libresoc.v:52053$1853
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_asmcode$next[7:0]$1853 $1\core_asmcode$next[7:0]$1912
- assign $0\core_core_cia$next[63:0]$1854 $1\core_core_cia$next[63:0]$1913
- assign $0\core_core_cr_rd$next[7:0]$1855 $1\core_core_cr_rd$next[7:0]$1914
+ assign $0\core_asmcode$next[7:0]$1854 $1\core_asmcode$next[7:0]$1913
+ assign $0\core_core_cia$next[63:0]$1855 $1\core_core_cia$next[63:0]$1914
+ assign $0\core_core_cr_rd$next[7:0]$1856 $1\core_core_cr_rd$next[7:0]$1915
assign { } { }
- assign $0\core_core_cr_wr$next[7:0]$1857 $1\core_core_cr_wr$next[7:0]$1916
+ assign $0\core_core_cr_wr$next[7:0]$1858 $1\core_core_cr_wr$next[7:0]$1917
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\core_core_fn_unit$next[11:0]$1867 $1\core_core_fn_unit$next[11:0]$1926
- assign $0\core_core_input_carry$next[1:0]$1868 $1\core_core_input_carry$next[1:0]$1927
- assign $0\core_core_insn$next[31:0]$1869 $1\core_core_insn$next[31:0]$1928
- assign $0\core_core_insn_type$next[6:0]$1870 $1\core_core_insn_type$next[6:0]$1929
- assign $0\core_core_is_32bit$next[0:0]$1871 $1\core_core_is_32bit$next[0:0]$1930
- assign $0\core_core_lk$next[0:0]$1872 $1\core_core_lk$next[0:0]$1931
- assign $0\core_core_msr$next[63:0]$1873 $1\core_core_msr$next[63:0]$1932
- assign $0\core_core_oe$next[0:0]$1874 $1\core_core_oe$next[0:0]$1933
+ assign $0\core_core_fn_unit$next[11:0]$1868 $1\core_core_fn_unit$next[11:0]$1927
+ assign $0\core_core_input_carry$next[1:0]$1869 $1\core_core_input_carry$next[1:0]$1928
+ assign $0\core_core_insn$next[31:0]$1870 $1\core_core_insn$next[31:0]$1929
+ assign $0\core_core_insn_type$next[6:0]$1871 $1\core_core_insn_type$next[6:0]$1930
+ assign $0\core_core_is_32bit$next[0:0]$1872 $1\core_core_is_32bit$next[0:0]$1931
+ assign $0\core_core_lk$next[0:0]$1873 $1\core_core_lk$next[0:0]$1932
+ assign $0\core_core_msr$next[63:0]$1874 $1\core_core_msr$next[63:0]$1933
+ assign $0\core_core_oe$next[0:0]$1875 $1\core_core_oe$next[0:0]$1934
assign { } { }
- assign $0\core_core_rc$next[0:0]$1876 $1\core_core_rc$next[0:0]$1935
+ assign $0\core_core_rc$next[0:0]$1877 $1\core_core_rc$next[0:0]$1936
assign { } { }
- assign $0\core_core_trapaddr$next[12:0]$1878 $1\core_core_trapaddr$next[12:0]$1937
- assign $0\core_core_traptype$next[7:0]$1879 $1\core_core_traptype$next[7:0]$1938
- assign $0\core_cr_in1$next[2:0]$1880 $1\core_cr_in1$next[2:0]$1939
+ assign $0\core_core_trapaddr$next[12:0]$1879 $1\core_core_trapaddr$next[12:0]$1938
+ assign $0\core_core_traptype$next[7:0]$1880 $1\core_core_traptype$next[7:0]$1939
+ assign $0\core_cr_in1$next[2:0]$1881 $1\core_cr_in1$next[2:0]$1940
assign { } { }
- assign $0\core_cr_in2$48$next[2:0]$1882 $1\core_cr_in2$48$next[2:0]$1941
- assign $0\core_cr_in2$next[2:0]$1883 $1\core_cr_in2$next[2:0]$1942
+ assign $0\core_cr_in2$48$next[2:0]$1883 $1\core_cr_in2$48$next[2:0]$1942
+ assign $0\core_cr_in2$next[2:0]$1884 $1\core_cr_in2$next[2:0]$1943
assign { } { }
assign { } { }
- assign $0\core_cr_out$next[2:0]$1886 $1\core_cr_out$next[2:0]$1945
+ assign $0\core_cr_out$next[2:0]$1887 $1\core_cr_out$next[2:0]$1946
assign { } { }
- assign $0\core_ea$next[4:0]$1888 $1\core_ea$next[4:0]$1947
+ assign $0\core_ea$next[4:0]$1889 $1\core_ea$next[4:0]$1948
assign { } { }
- assign $0\core_fast1$next[2:0]$1890 $1\core_fast1$next[2:0]$1949
+ assign $0\core_fast1$next[2:0]$1891 $1\core_fast1$next[2:0]$1950
assign { } { }
- assign $0\core_fast2$next[2:0]$1892 $1\core_fast2$next[2:0]$1951
+ assign $0\core_fast2$next[2:0]$1893 $1\core_fast2$next[2:0]$1952
assign { } { }
- assign $0\core_fasto1$next[2:0]$1894 $1\core_fasto1$next[2:0]$1953
+ assign $0\core_fasto1$next[2:0]$1895 $1\core_fasto1$next[2:0]$1954
assign { } { }
- assign $0\core_fasto2$next[2:0]$1896 $1\core_fasto2$next[2:0]$1955
+ assign $0\core_fasto2$next[2:0]$1897 $1\core_fasto2$next[2:0]$1956
assign { } { }
- assign $0\core_reg1$next[4:0]$1898 $1\core_reg1$next[4:0]$1957
+ assign $0\core_reg1$next[4:0]$1899 $1\core_reg1$next[4:0]$1958
assign { } { }
- assign $0\core_reg2$next[4:0]$1900 $1\core_reg2$next[4:0]$1959
+ assign $0\core_reg2$next[4:0]$1901 $1\core_reg2$next[4:0]$1960
assign { } { }
- assign $0\core_reg3$next[4:0]$1902 $1\core_reg3$next[4:0]$1961
+ assign $0\core_reg3$next[4:0]$1903 $1\core_reg3$next[4:0]$1962
assign { } { }
- assign $0\core_rego$next[4:0]$1904 $1\core_rego$next[4:0]$1963
+ assign $0\core_rego$next[4:0]$1905 $1\core_rego$next[4:0]$1964
assign { } { }
- assign $0\core_spr1$next[9:0]$1906 $1\core_spr1$next[9:0]$1965
+ assign $0\core_spr1$next[9:0]$1907 $1\core_spr1$next[9:0]$1966
assign { } { }
- assign $0\core_spro$next[9:0]$1908 $1\core_spro$next[9:0]$1967
+ assign $0\core_spro$next[9:0]$1909 $1\core_spro$next[9:0]$1968
assign { } { }
- assign $0\core_xer_in$next[2:0]$1910 $1\core_xer_in$next[2:0]$1969
- assign $0\core_xer_out$next[0:0]$1911 $1\core_xer_out$next[0:0]$1970
- assign $0\core_core_cr_rd_ok$next[0:0]$1856 $4\core_core_cr_rd_ok$next[0:0]$2089
- assign $0\core_core_cr_wr_ok$next[0:0]$1858 $4\core_core_cr_wr_ok$next[0:0]$2090
- assign $0\core_core_exc_$signal$50$next[0:0]$1859 $4\core_core_exc_$signal$50$next[0:0]$2091
- assign $0\core_core_exc_$signal$51$next[0:0]$1860 $4\core_core_exc_$signal$51$next[0:0]$2092
- assign $0\core_core_exc_$signal$52$next[0:0]$1861 $4\core_core_exc_$signal$52$next[0:0]$2093
- assign $0\core_core_exc_$signal$53$next[0:0]$1862 $4\core_core_exc_$signal$53$next[0:0]$2094
- assign $0\core_core_exc_$signal$54$next[0:0]$1863 $4\core_core_exc_$signal$54$next[0:0]$2095
- assign $0\core_core_exc_$signal$55$next[0:0]$1864 $4\core_core_exc_$signal$55$next[0:0]$2096
- assign $0\core_core_exc_$signal$56$next[0:0]$1865 $4\core_core_exc_$signal$56$next[0:0]$2097
- assign $0\core_core_exc_$signal$next[0:0]$1866 $4\core_core_exc_$signal$next[0:0]$2098
- assign $0\core_core_oe_ok$next[0:0]$1875 $4\core_core_oe_ok$next[0:0]$2099
- assign $0\core_core_rc_ok$next[0:0]$1877 $4\core_core_rc_ok$next[0:0]$2100
- assign $0\core_cr_in1_ok$next[0:0]$1881 $4\core_cr_in1_ok$next[0:0]$2101
- assign $0\core_cr_in2_ok$49$next[0:0]$1884 $4\core_cr_in2_ok$49$next[0:0]$2102
- assign $0\core_cr_in2_ok$next[0:0]$1885 $4\core_cr_in2_ok$next[0:0]$2103
- assign $0\core_cr_out_ok$next[0:0]$1887 $4\core_cr_out_ok$next[0:0]$2104
- assign $0\core_ea_ok$next[0:0]$1889 $4\core_ea_ok$next[0:0]$2105
- assign $0\core_fast1_ok$next[0:0]$1891 $4\core_fast1_ok$next[0:0]$2106
- assign $0\core_fast2_ok$next[0:0]$1893 $4\core_fast2_ok$next[0:0]$2107
- assign $0\core_fasto1_ok$next[0:0]$1895 $4\core_fasto1_ok$next[0:0]$2108
- assign $0\core_fasto2_ok$next[0:0]$1897 $4\core_fasto2_ok$next[0:0]$2109
- assign $0\core_reg1_ok$next[0:0]$1899 $4\core_reg1_ok$next[0:0]$2110
- assign $0\core_reg2_ok$next[0:0]$1901 $4\core_reg2_ok$next[0:0]$2111
- assign $0\core_reg3_ok$next[0:0]$1903 $4\core_reg3_ok$next[0:0]$2112
- assign $0\core_rego_ok$next[0:0]$1905 $4\core_rego_ok$next[0:0]$2113
- assign $0\core_spr1_ok$next[0:0]$1907 $4\core_spr1_ok$next[0:0]$2114
- assign $0\core_spro_ok$next[0:0]$1909 $4\core_spro_ok$next[0:0]$2115
- attribute \src "libresoc.v:52051.5-52051.29"
+ assign $0\core_xer_in$next[2:0]$1911 $1\core_xer_in$next[2:0]$1970
+ assign $0\core_xer_out$next[0:0]$1912 $1\core_xer_out$next[0:0]$1971
+ assign $0\core_core_cr_rd_ok$next[0:0]$1857 $4\core_core_cr_rd_ok$next[0:0]$2090
+ assign $0\core_core_cr_wr_ok$next[0:0]$1859 $4\core_core_cr_wr_ok$next[0:0]$2091
+ assign $0\core_core_exc_$signal$50$next[0:0]$1860 $4\core_core_exc_$signal$50$next[0:0]$2092
+ assign $0\core_core_exc_$signal$51$next[0:0]$1861 $4\core_core_exc_$signal$51$next[0:0]$2093
+ assign $0\core_core_exc_$signal$52$next[0:0]$1862 $4\core_core_exc_$signal$52$next[0:0]$2094
+ assign $0\core_core_exc_$signal$53$next[0:0]$1863 $4\core_core_exc_$signal$53$next[0:0]$2095
+ assign $0\core_core_exc_$signal$54$next[0:0]$1864 $4\core_core_exc_$signal$54$next[0:0]$2096
+ assign $0\core_core_exc_$signal$55$next[0:0]$1865 $4\core_core_exc_$signal$55$next[0:0]$2097
+ assign $0\core_core_exc_$signal$56$next[0:0]$1866 $4\core_core_exc_$signal$56$next[0:0]$2098
+ assign $0\core_core_exc_$signal$next[0:0]$1867 $4\core_core_exc_$signal$next[0:0]$2099
+ assign $0\core_core_oe_ok$next[0:0]$1876 $4\core_core_oe_ok$next[0:0]$2100
+ assign $0\core_core_rc_ok$next[0:0]$1878 $4\core_core_rc_ok$next[0:0]$2101
+ assign $0\core_cr_in1_ok$next[0:0]$1882 $4\core_cr_in1_ok$next[0:0]$2102
+ assign $0\core_cr_in2_ok$49$next[0:0]$1885 $4\core_cr_in2_ok$49$next[0:0]$2103
+ assign $0\core_cr_in2_ok$next[0:0]$1886 $4\core_cr_in2_ok$next[0:0]$2104
+ assign $0\core_cr_out_ok$next[0:0]$1888 $4\core_cr_out_ok$next[0:0]$2105
+ assign $0\core_ea_ok$next[0:0]$1890 $4\core_ea_ok$next[0:0]$2106
+ assign $0\core_fast1_ok$next[0:0]$1892 $4\core_fast1_ok$next[0:0]$2107
+ assign $0\core_fast2_ok$next[0:0]$1894 $4\core_fast2_ok$next[0:0]$2108
+ assign $0\core_fasto1_ok$next[0:0]$1896 $4\core_fasto1_ok$next[0:0]$2109
+ assign $0\core_fasto2_ok$next[0:0]$1898 $4\core_fasto2_ok$next[0:0]$2110
+ assign $0\core_reg1_ok$next[0:0]$1900 $4\core_reg1_ok$next[0:0]$2111
+ assign $0\core_reg2_ok$next[0:0]$1902 $4\core_reg2_ok$next[0:0]$2112
+ assign $0\core_reg3_ok$next[0:0]$1904 $4\core_reg3_ok$next[0:0]$2113
+ assign $0\core_rego_ok$next[0:0]$1906 $4\core_rego_ok$next[0:0]$2114
+ assign $0\core_spr1_ok$next[0:0]$1908 $4\core_spr1_ok$next[0:0]$2115
+ assign $0\core_spro_ok$next[0:0]$1910 $4\core_spro_ok$next[0:0]$2116
+ attribute \src "libresoc.v:52054.5-52054.29"
switch \initial
- attribute \src "libresoc.v:52051.9-52051.17"
+ attribute \src "libresoc.v:52054.9-52054.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign { $1\core_core_is_32bit$next[0:0]$1930 $1\core_core_cr_wr_ok$next[0:0]$1917 $1\core_core_cr_wr$next[7:0]$1916 $1\core_core_cr_rd_ok$next[0:0]$1915 $1\core_core_cr_rd$next[7:0]$1914 $1\core_core_trapaddr$next[12:0]$1937 $1\core_core_exc_$signal$56$next[0:0]$1924 $1\core_core_exc_$signal$55$next[0:0]$1923 $1\core_core_exc_$signal$54$next[0:0]$1922 $1\core_core_exc_$signal$53$next[0:0]$1921 $1\core_core_exc_$signal$52$next[0:0]$1920 $1\core_core_exc_$signal$51$next[0:0]$1919 $1\core_core_exc_$signal$50$next[0:0]$1918 $1\core_core_exc_$signal$next[0:0]$1925 $1\core_core_traptype$next[7:0]$1938 $1\core_core_input_carry$next[1:0]$1927 $1\core_core_oe_ok$next[0:0]$1934 $1\core_core_oe$next[0:0]$1933 $1\core_core_rc_ok$next[0:0]$1936 $1\core_core_rc$next[0:0]$1935 $1\core_core_lk$next[0:0]$1931 $1\core_core_fn_unit$next[11:0]$1926 $1\core_core_insn_type$next[6:0]$1929 $1\core_core_insn$next[31:0]$1928 $1\core_core_cia$next[63:0]$1913 $1\core_core_msr$next[63:0]$1932 $1\core_cr_out_ok$next[0:0]$1946 $1\core_cr_out$next[2:0]$1945 $1\core_cr_in2_ok$49$next[0:0]$1943 $1\core_cr_in2$48$next[2:0]$1941 $1\core_cr_in2_ok$next[0:0]$1944 $1\core_cr_in2$next[2:0]$1942 $1\core_cr_in1_ok$next[0:0]$1940 $1\core_cr_in1$next[2:0]$1939 $1\core_fasto2_ok$next[0:0]$1956 $1\core_fasto2$next[2:0]$1955 $1\core_fasto1_ok$next[0:0]$1954 $1\core_fasto1$next[2:0]$1953 $1\core_fast2_ok$next[0:0]$1952 $1\core_fast2$next[2:0]$1951 $1\core_fast1_ok$next[0:0]$1950 $1\core_fast1$next[2:0]$1949 $1\core_xer_out$next[0:0]$1970 $1\core_xer_in$next[2:0]$1969 $1\core_spr1_ok$next[0:0]$1966 $1\core_spr1$next[9:0]$1965 $1\core_spro_ok$next[0:0]$1968 $1\core_spro$next[9:0]$1967 $1\core_reg3_ok$next[0:0]$1962 $1\core_reg3$next[4:0]$1961 $1\core_reg2_ok$next[0:0]$1960 $1\core_reg2$next[4:0]$1959 $1\core_reg1_ok$next[0:0]$1958 $1\core_reg1$next[4:0]$1957 $1\core_ea_ok$next[0:0]$1948 $1\core_ea$next[4:0]$1947 $1\core_rego_ok$next[0:0]$1964 $1\core_rego$next[4:0]$1963 $1\core_asmcode$next[7:0]$1912 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $1\core_core_is_32bit$next[0:0]$1931 $1\core_core_cr_wr_ok$next[0:0]$1918 $1\core_core_cr_wr$next[7:0]$1917 $1\core_core_cr_rd_ok$next[0:0]$1916 $1\core_core_cr_rd$next[7:0]$1915 $1\core_core_trapaddr$next[12:0]$1938 $1\core_core_exc_$signal$56$next[0:0]$1925 $1\core_core_exc_$signal$55$next[0:0]$1924 $1\core_core_exc_$signal$54$next[0:0]$1923 $1\core_core_exc_$signal$53$next[0:0]$1922 $1\core_core_exc_$signal$52$next[0:0]$1921 $1\core_core_exc_$signal$51$next[0:0]$1920 $1\core_core_exc_$signal$50$next[0:0]$1919 $1\core_core_exc_$signal$next[0:0]$1926 $1\core_core_traptype$next[7:0]$1939 $1\core_core_input_carry$next[1:0]$1928 $1\core_core_oe_ok$next[0:0]$1935 $1\core_core_oe$next[0:0]$1934 $1\core_core_rc_ok$next[0:0]$1937 $1\core_core_rc$next[0:0]$1936 $1\core_core_lk$next[0:0]$1932 $1\core_core_fn_unit$next[11:0]$1927 $1\core_core_insn_type$next[6:0]$1930 $1\core_core_insn$next[31:0]$1929 $1\core_core_cia$next[63:0]$1914 $1\core_core_msr$next[63:0]$1933 $1\core_cr_out_ok$next[0:0]$1947 $1\core_cr_out$next[2:0]$1946 $1\core_cr_in2_ok$49$next[0:0]$1944 $1\core_cr_in2$48$next[2:0]$1942 $1\core_cr_in2_ok$next[0:0]$1945 $1\core_cr_in2$next[2:0]$1943 $1\core_cr_in1_ok$next[0:0]$1941 $1\core_cr_in1$next[2:0]$1940 $1\core_fasto2_ok$next[0:0]$1957 $1\core_fasto2$next[2:0]$1956 $1\core_fasto1_ok$next[0:0]$1955 $1\core_fasto1$next[2:0]$1954 $1\core_fast2_ok$next[0:0]$1953 $1\core_fast2$next[2:0]$1952 $1\core_fast1_ok$next[0:0]$1951 $1\core_fast1$next[2:0]$1950 $1\core_xer_out$next[0:0]$1971 $1\core_xer_in$next[2:0]$1970 $1\core_spr1_ok$next[0:0]$1967 $1\core_spr1$next[9:0]$1966 $1\core_spro_ok$next[0:0]$1969 $1\core_spro$next[9:0]$1968 $1\core_reg3_ok$next[0:0]$1963 $1\core_reg3$next[4:0]$1962 $1\core_reg2_ok$next[0:0]$1961 $1\core_reg2$next[4:0]$1960 $1\core_reg1_ok$next[0:0]$1959 $1\core_reg1$next[4:0]$1958 $1\core_ea_ok$next[0:0]$1949 $1\core_ea$next[4:0]$1948 $1\core_rego_ok$next[0:0]$1965 $1\core_rego$next[4:0]$1964 $1\core_asmcode$next[7:0]$1913 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_asmcode$next[7:0]$1912 $2\core_asmcode$next[7:0]$1971
- assign $1\core_core_cia$next[63:0]$1913 $2\core_core_cia$next[63:0]$1972
- assign $1\core_core_cr_rd$next[7:0]$1914 $2\core_core_cr_rd$next[7:0]$1973
- assign $1\core_core_cr_rd_ok$next[0:0]$1915 $2\core_core_cr_rd_ok$next[0:0]$1974
- assign $1\core_core_cr_wr$next[7:0]$1916 $2\core_core_cr_wr$next[7:0]$1975
- assign $1\core_core_cr_wr_ok$next[0:0]$1917 $2\core_core_cr_wr_ok$next[0:0]$1976
- assign $1\core_core_exc_$signal$50$next[0:0]$1918 $2\core_core_exc_$signal$50$next[0:0]$1977
- assign $1\core_core_exc_$signal$51$next[0:0]$1919 $2\core_core_exc_$signal$51$next[0:0]$1978
- assign $1\core_core_exc_$signal$52$next[0:0]$1920 $2\core_core_exc_$signal$52$next[0:0]$1979
- assign $1\core_core_exc_$signal$53$next[0:0]$1921 $2\core_core_exc_$signal$53$next[0:0]$1980
- assign $1\core_core_exc_$signal$54$next[0:0]$1922 $2\core_core_exc_$signal$54$next[0:0]$1981
- assign $1\core_core_exc_$signal$55$next[0:0]$1923 $2\core_core_exc_$signal$55$next[0:0]$1982
- assign $1\core_core_exc_$signal$56$next[0:0]$1924 $2\core_core_exc_$signal$56$next[0:0]$1983
- assign $1\core_core_exc_$signal$next[0:0]$1925 $2\core_core_exc_$signal$next[0:0]$1984
- assign $1\core_core_fn_unit$next[11:0]$1926 $2\core_core_fn_unit$next[11:0]$1985
- assign $1\core_core_input_carry$next[1:0]$1927 $2\core_core_input_carry$next[1:0]$1986
- assign $1\core_core_insn$next[31:0]$1928 $2\core_core_insn$next[31:0]$1987
- assign $1\core_core_insn_type$next[6:0]$1929 $2\core_core_insn_type$next[6:0]$1988
- assign $1\core_core_is_32bit$next[0:0]$1930 $2\core_core_is_32bit$next[0:0]$1989
- assign $1\core_core_lk$next[0:0]$1931 $2\core_core_lk$next[0:0]$1990
- assign $1\core_core_msr$next[63:0]$1932 $2\core_core_msr$next[63:0]$1991
- assign $1\core_core_oe$next[0:0]$1933 $2\core_core_oe$next[0:0]$1992
- assign $1\core_core_oe_ok$next[0:0]$1934 $2\core_core_oe_ok$next[0:0]$1993
- assign $1\core_core_rc$next[0:0]$1935 $2\core_core_rc$next[0:0]$1994
- assign $1\core_core_rc_ok$next[0:0]$1936 $2\core_core_rc_ok$next[0:0]$1995
- assign $1\core_core_trapaddr$next[12:0]$1937 $2\core_core_trapaddr$next[12:0]$1996
- assign $1\core_core_traptype$next[7:0]$1938 $2\core_core_traptype$next[7:0]$1997
- assign $1\core_cr_in1$next[2:0]$1939 $2\core_cr_in1$next[2:0]$1998
- assign $1\core_cr_in1_ok$next[0:0]$1940 $2\core_cr_in1_ok$next[0:0]$1999
- assign $1\core_cr_in2$48$next[2:0]$1941 $2\core_cr_in2$48$next[2:0]$2000
- assign $1\core_cr_in2$next[2:0]$1942 $2\core_cr_in2$next[2:0]$2001
- assign $1\core_cr_in2_ok$49$next[0:0]$1943 $2\core_cr_in2_ok$49$next[0:0]$2002
- assign $1\core_cr_in2_ok$next[0:0]$1944 $2\core_cr_in2_ok$next[0:0]$2003
- assign $1\core_cr_out$next[2:0]$1945 $2\core_cr_out$next[2:0]$2004
- assign $1\core_cr_out_ok$next[0:0]$1946 $2\core_cr_out_ok$next[0:0]$2005
- assign $1\core_ea$next[4:0]$1947 $2\core_ea$next[4:0]$2006
- assign $1\core_ea_ok$next[0:0]$1948 $2\core_ea_ok$next[0:0]$2007
- assign $1\core_fast1$next[2:0]$1949 $2\core_fast1$next[2:0]$2008
- assign $1\core_fast1_ok$next[0:0]$1950 $2\core_fast1_ok$next[0:0]$2009
- assign $1\core_fast2$next[2:0]$1951 $2\core_fast2$next[2:0]$2010
- assign $1\core_fast2_ok$next[0:0]$1952 $2\core_fast2_ok$next[0:0]$2011
- assign $1\core_fasto1$next[2:0]$1953 $2\core_fasto1$next[2:0]$2012
- assign $1\core_fasto1_ok$next[0:0]$1954 $2\core_fasto1_ok$next[0:0]$2013
- assign $1\core_fasto2$next[2:0]$1955 $2\core_fasto2$next[2:0]$2014
- assign $1\core_fasto2_ok$next[0:0]$1956 $2\core_fasto2_ok$next[0:0]$2015
- assign $1\core_reg1$next[4:0]$1957 $2\core_reg1$next[4:0]$2016
- assign $1\core_reg1_ok$next[0:0]$1958 $2\core_reg1_ok$next[0:0]$2017
- assign $1\core_reg2$next[4:0]$1959 $2\core_reg2$next[4:0]$2018
- assign $1\core_reg2_ok$next[0:0]$1960 $2\core_reg2_ok$next[0:0]$2019
- assign $1\core_reg3$next[4:0]$1961 $2\core_reg3$next[4:0]$2020
- assign $1\core_reg3_ok$next[0:0]$1962 $2\core_reg3_ok$next[0:0]$2021
- assign $1\core_rego$next[4:0]$1963 $2\core_rego$next[4:0]$2022
- assign $1\core_rego_ok$next[0:0]$1964 $2\core_rego_ok$next[0:0]$2023
- assign $1\core_spr1$next[9:0]$1965 $2\core_spr1$next[9:0]$2024
- assign $1\core_spr1_ok$next[0:0]$1966 $2\core_spr1_ok$next[0:0]$2025
- assign $1\core_spro$next[9:0]$1967 $2\core_spro$next[9:0]$2026
- assign $1\core_spro_ok$next[0:0]$1968 $2\core_spro_ok$next[0:0]$2027
- assign $1\core_xer_in$next[2:0]$1969 $2\core_xer_in$next[2:0]$2028
- assign $1\core_xer_out$next[0:0]$1970 $2\core_xer_out$next[0:0]$2029
+ assign $1\core_asmcode$next[7:0]$1913 $2\core_asmcode$next[7:0]$1972
+ assign $1\core_core_cia$next[63:0]$1914 $2\core_core_cia$next[63:0]$1973
+ assign $1\core_core_cr_rd$next[7:0]$1915 $2\core_core_cr_rd$next[7:0]$1974
+ assign $1\core_core_cr_rd_ok$next[0:0]$1916 $2\core_core_cr_rd_ok$next[0:0]$1975
+ assign $1\core_core_cr_wr$next[7:0]$1917 $2\core_core_cr_wr$next[7:0]$1976
+ assign $1\core_core_cr_wr_ok$next[0:0]$1918 $2\core_core_cr_wr_ok$next[0:0]$1977
+ assign $1\core_core_exc_$signal$50$next[0:0]$1919 $2\core_core_exc_$signal$50$next[0:0]$1978
+ assign $1\core_core_exc_$signal$51$next[0:0]$1920 $2\core_core_exc_$signal$51$next[0:0]$1979
+ assign $1\core_core_exc_$signal$52$next[0:0]$1921 $2\core_core_exc_$signal$52$next[0:0]$1980
+ assign $1\core_core_exc_$signal$53$next[0:0]$1922 $2\core_core_exc_$signal$53$next[0:0]$1981
+ assign $1\core_core_exc_$signal$54$next[0:0]$1923 $2\core_core_exc_$signal$54$next[0:0]$1982
+ assign $1\core_core_exc_$signal$55$next[0:0]$1924 $2\core_core_exc_$signal$55$next[0:0]$1983
+ assign $1\core_core_exc_$signal$56$next[0:0]$1925 $2\core_core_exc_$signal$56$next[0:0]$1984
+ assign $1\core_core_exc_$signal$next[0:0]$1926 $2\core_core_exc_$signal$next[0:0]$1985
+ assign $1\core_core_fn_unit$next[11:0]$1927 $2\core_core_fn_unit$next[11:0]$1986
+ assign $1\core_core_input_carry$next[1:0]$1928 $2\core_core_input_carry$next[1:0]$1987
+ assign $1\core_core_insn$next[31:0]$1929 $2\core_core_insn$next[31:0]$1988
+ assign $1\core_core_insn_type$next[6:0]$1930 $2\core_core_insn_type$next[6:0]$1989
+ assign $1\core_core_is_32bit$next[0:0]$1931 $2\core_core_is_32bit$next[0:0]$1990
+ assign $1\core_core_lk$next[0:0]$1932 $2\core_core_lk$next[0:0]$1991
+ assign $1\core_core_msr$next[63:0]$1933 $2\core_core_msr$next[63:0]$1992
+ assign $1\core_core_oe$next[0:0]$1934 $2\core_core_oe$next[0:0]$1993
+ assign $1\core_core_oe_ok$next[0:0]$1935 $2\core_core_oe_ok$next[0:0]$1994
+ assign $1\core_core_rc$next[0:0]$1936 $2\core_core_rc$next[0:0]$1995
+ assign $1\core_core_rc_ok$next[0:0]$1937 $2\core_core_rc_ok$next[0:0]$1996
+ assign $1\core_core_trapaddr$next[12:0]$1938 $2\core_core_trapaddr$next[12:0]$1997
+ assign $1\core_core_traptype$next[7:0]$1939 $2\core_core_traptype$next[7:0]$1998
+ assign $1\core_cr_in1$next[2:0]$1940 $2\core_cr_in1$next[2:0]$1999
+ assign $1\core_cr_in1_ok$next[0:0]$1941 $2\core_cr_in1_ok$next[0:0]$2000
+ assign $1\core_cr_in2$48$next[2:0]$1942 $2\core_cr_in2$48$next[2:0]$2001
+ assign $1\core_cr_in2$next[2:0]$1943 $2\core_cr_in2$next[2:0]$2002
+ assign $1\core_cr_in2_ok$49$next[0:0]$1944 $2\core_cr_in2_ok$49$next[0:0]$2003
+ assign $1\core_cr_in2_ok$next[0:0]$1945 $2\core_cr_in2_ok$next[0:0]$2004
+ assign $1\core_cr_out$next[2:0]$1946 $2\core_cr_out$next[2:0]$2005
+ assign $1\core_cr_out_ok$next[0:0]$1947 $2\core_cr_out_ok$next[0:0]$2006
+ assign $1\core_ea$next[4:0]$1948 $2\core_ea$next[4:0]$2007
+ assign $1\core_ea_ok$next[0:0]$1949 $2\core_ea_ok$next[0:0]$2008
+ assign $1\core_fast1$next[2:0]$1950 $2\core_fast1$next[2:0]$2009
+ assign $1\core_fast1_ok$next[0:0]$1951 $2\core_fast1_ok$next[0:0]$2010
+ assign $1\core_fast2$next[2:0]$1952 $2\core_fast2$next[2:0]$2011
+ assign $1\core_fast2_ok$next[0:0]$1953 $2\core_fast2_ok$next[0:0]$2012
+ assign $1\core_fasto1$next[2:0]$1954 $2\core_fasto1$next[2:0]$2013
+ assign $1\core_fasto1_ok$next[0:0]$1955 $2\core_fasto1_ok$next[0:0]$2014
+ assign $1\core_fasto2$next[2:0]$1956 $2\core_fasto2$next[2:0]$2015
+ assign $1\core_fasto2_ok$next[0:0]$1957 $2\core_fasto2_ok$next[0:0]$2016
+ assign $1\core_reg1$next[4:0]$1958 $2\core_reg1$next[4:0]$2017
+ assign $1\core_reg1_ok$next[0:0]$1959 $2\core_reg1_ok$next[0:0]$2018
+ assign $1\core_reg2$next[4:0]$1960 $2\core_reg2$next[4:0]$2019
+ assign $1\core_reg2_ok$next[0:0]$1961 $2\core_reg2_ok$next[0:0]$2020
+ assign $1\core_reg3$next[4:0]$1962 $2\core_reg3$next[4:0]$2021
+ assign $1\core_reg3_ok$next[0:0]$1963 $2\core_reg3_ok$next[0:0]$2022
+ assign $1\core_rego$next[4:0]$1964 $2\core_rego$next[4:0]$2023
+ assign $1\core_rego_ok$next[0:0]$1965 $2\core_rego_ok$next[0:0]$2024
+ assign $1\core_spr1$next[9:0]$1966 $2\core_spr1$next[9:0]$2025
+ assign $1\core_spr1_ok$next[0:0]$1967 $2\core_spr1_ok$next[0:0]$2026
+ assign $1\core_spro$next[9:0]$1968 $2\core_spro$next[9:0]$2027
+ assign $1\core_spro_ok$next[0:0]$1969 $2\core_spro_ok$next[0:0]$2028
+ assign $1\core_xer_in$next[2:0]$1970 $2\core_xer_in$next[2:0]$2029
+ assign $1\core_xer_out$next[0:0]$1971 $2\core_xer_out$next[0:0]$2030
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\core_asmcode$next[7:0]$1971 \core_asmcode
- assign $2\core_core_cia$next[63:0]$1972 \core_core_cia
- assign $2\core_core_cr_rd$next[7:0]$1973 \core_core_cr_rd
- assign $2\core_core_cr_rd_ok$next[0:0]$1974 \core_core_cr_rd_ok
- assign $2\core_core_cr_wr$next[7:0]$1975 \core_core_cr_wr
- assign $2\core_core_cr_wr_ok$next[0:0]$1976 \core_core_cr_wr_ok
- assign $2\core_core_exc_$signal$50$next[0:0]$1977 \core_core_exc_$signal$50
- assign $2\core_core_exc_$signal$51$next[0:0]$1978 \core_core_exc_$signal$51
- assign $2\core_core_exc_$signal$52$next[0:0]$1979 \core_core_exc_$signal$52
- assign $2\core_core_exc_$signal$53$next[0:0]$1980 \core_core_exc_$signal$53
- assign $2\core_core_exc_$signal$54$next[0:0]$1981 \core_core_exc_$signal$54
- assign $2\core_core_exc_$signal$55$next[0:0]$1982 \core_core_exc_$signal$55
- assign $2\core_core_exc_$signal$56$next[0:0]$1983 \core_core_exc_$signal$56
- assign $2\core_core_exc_$signal$next[0:0]$1984 \core_core_exc_$signal
- assign $2\core_core_fn_unit$next[11:0]$1985 \core_core_fn_unit
- assign $2\core_core_input_carry$next[1:0]$1986 \core_core_input_carry
- assign $2\core_core_insn$next[31:0]$1987 \core_core_insn
- assign $2\core_core_insn_type$next[6:0]$1988 \core_core_insn_type
- assign $2\core_core_is_32bit$next[0:0]$1989 \core_core_is_32bit
- assign $2\core_core_lk$next[0:0]$1990 \core_core_lk
- assign $2\core_core_msr$next[63:0]$1991 \core_core_msr
- assign $2\core_core_oe$next[0:0]$1992 \core_core_oe
- assign $2\core_core_oe_ok$next[0:0]$1993 \core_core_oe_ok
- assign $2\core_core_rc$next[0:0]$1994 \core_core_rc
- assign $2\core_core_rc_ok$next[0:0]$1995 \core_core_rc_ok
- assign $2\core_core_trapaddr$next[12:0]$1996 \core_core_trapaddr
- assign $2\core_core_traptype$next[7:0]$1997 \core_core_traptype
- assign $2\core_cr_in1$next[2:0]$1998 \core_cr_in1
- assign $2\core_cr_in1_ok$next[0:0]$1999 \core_cr_in1_ok
- assign $2\core_cr_in2$48$next[2:0]$2000 \core_cr_in2$48
- assign $2\core_cr_in2$next[2:0]$2001 \core_cr_in2
- assign $2\core_cr_in2_ok$49$next[0:0]$2002 \core_cr_in2_ok$49
- assign $2\core_cr_in2_ok$next[0:0]$2003 \core_cr_in2_ok
- assign $2\core_cr_out$next[2:0]$2004 \core_cr_out
- assign $2\core_cr_out_ok$next[0:0]$2005 \core_cr_out_ok
- assign $2\core_ea$next[4:0]$2006 \core_ea
- assign $2\core_ea_ok$next[0:0]$2007 \core_ea_ok
- assign $2\core_fast1$next[2:0]$2008 \core_fast1
- assign $2\core_fast1_ok$next[0:0]$2009 \core_fast1_ok
- assign $2\core_fast2$next[2:0]$2010 \core_fast2
- assign $2\core_fast2_ok$next[0:0]$2011 \core_fast2_ok
- assign $2\core_fasto1$next[2:0]$2012 \core_fasto1
- assign $2\core_fasto1_ok$next[0:0]$2013 \core_fasto1_ok
- assign $2\core_fasto2$next[2:0]$2014 \core_fasto2
- assign $2\core_fasto2_ok$next[0:0]$2015 \core_fasto2_ok
- assign $2\core_reg1$next[4:0]$2016 \core_reg1
- assign $2\core_reg1_ok$next[0:0]$2017 \core_reg1_ok
- assign $2\core_reg2$next[4:0]$2018 \core_reg2
- assign $2\core_reg2_ok$next[0:0]$2019 \core_reg2_ok
- assign $2\core_reg3$next[4:0]$2020 \core_reg3
- assign $2\core_reg3_ok$next[0:0]$2021 \core_reg3_ok
- assign $2\core_rego$next[4:0]$2022 \core_rego
- assign $2\core_rego_ok$next[0:0]$2023 \core_rego_ok
- assign $2\core_spr1$next[9:0]$2024 \core_spr1
- assign $2\core_spr1_ok$next[0:0]$2025 \core_spr1_ok
- assign $2\core_spro$next[9:0]$2026 \core_spro
- assign $2\core_spro_ok$next[0:0]$2027 \core_spro_ok
- assign $2\core_xer_in$next[2:0]$2028 \core_xer_in
- assign $2\core_xer_out$next[0:0]$2029 \core_xer_out
+ assign $2\core_asmcode$next[7:0]$1972 \core_asmcode
+ assign $2\core_core_cia$next[63:0]$1973 \core_core_cia
+ assign $2\core_core_cr_rd$next[7:0]$1974 \core_core_cr_rd
+ assign $2\core_core_cr_rd_ok$next[0:0]$1975 \core_core_cr_rd_ok
+ assign $2\core_core_cr_wr$next[7:0]$1976 \core_core_cr_wr
+ assign $2\core_core_cr_wr_ok$next[0:0]$1977 \core_core_cr_wr_ok
+ assign $2\core_core_exc_$signal$50$next[0:0]$1978 \core_core_exc_$signal$50
+ assign $2\core_core_exc_$signal$51$next[0:0]$1979 \core_core_exc_$signal$51
+ assign $2\core_core_exc_$signal$52$next[0:0]$1980 \core_core_exc_$signal$52
+ assign $2\core_core_exc_$signal$53$next[0:0]$1981 \core_core_exc_$signal$53
+ assign $2\core_core_exc_$signal$54$next[0:0]$1982 \core_core_exc_$signal$54
+ assign $2\core_core_exc_$signal$55$next[0:0]$1983 \core_core_exc_$signal$55
+ assign $2\core_core_exc_$signal$56$next[0:0]$1984 \core_core_exc_$signal$56
+ assign $2\core_core_exc_$signal$next[0:0]$1985 \core_core_exc_$signal
+ assign $2\core_core_fn_unit$next[11:0]$1986 \core_core_fn_unit
+ assign $2\core_core_input_carry$next[1:0]$1987 \core_core_input_carry
+ assign $2\core_core_insn$next[31:0]$1988 \core_core_insn
+ assign $2\core_core_insn_type$next[6:0]$1989 \core_core_insn_type
+ assign $2\core_core_is_32bit$next[0:0]$1990 \core_core_is_32bit
+ assign $2\core_core_lk$next[0:0]$1991 \core_core_lk
+ assign $2\core_core_msr$next[63:0]$1992 \core_core_msr
+ assign $2\core_core_oe$next[0:0]$1993 \core_core_oe
+ assign $2\core_core_oe_ok$next[0:0]$1994 \core_core_oe_ok
+ assign $2\core_core_rc$next[0:0]$1995 \core_core_rc
+ assign $2\core_core_rc_ok$next[0:0]$1996 \core_core_rc_ok
+ assign $2\core_core_trapaddr$next[12:0]$1997 \core_core_trapaddr
+ assign $2\core_core_traptype$next[7:0]$1998 \core_core_traptype
+ assign $2\core_cr_in1$next[2:0]$1999 \core_cr_in1
+ assign $2\core_cr_in1_ok$next[0:0]$2000 \core_cr_in1_ok
+ assign $2\core_cr_in2$48$next[2:0]$2001 \core_cr_in2$48
+ assign $2\core_cr_in2$next[2:0]$2002 \core_cr_in2
+ assign $2\core_cr_in2_ok$49$next[0:0]$2003 \core_cr_in2_ok$49
+ assign $2\core_cr_in2_ok$next[0:0]$2004 \core_cr_in2_ok
+ assign $2\core_cr_out$next[2:0]$2005 \core_cr_out
+ assign $2\core_cr_out_ok$next[0:0]$2006 \core_cr_out_ok
+ assign $2\core_ea$next[4:0]$2007 \core_ea
+ assign $2\core_ea_ok$next[0:0]$2008 \core_ea_ok
+ assign $2\core_fast1$next[2:0]$2009 \core_fast1
+ assign $2\core_fast1_ok$next[0:0]$2010 \core_fast1_ok
+ assign $2\core_fast2$next[2:0]$2011 \core_fast2
+ assign $2\core_fast2_ok$next[0:0]$2012 \core_fast2_ok
+ assign $2\core_fasto1$next[2:0]$2013 \core_fasto1
+ assign $2\core_fasto1_ok$next[0:0]$2014 \core_fasto1_ok
+ assign $2\core_fasto2$next[2:0]$2015 \core_fasto2
+ assign $2\core_fasto2_ok$next[0:0]$2016 \core_fasto2_ok
+ assign $2\core_reg1$next[4:0]$2017 \core_reg1
+ assign $2\core_reg1_ok$next[0:0]$2018 \core_reg1_ok
+ assign $2\core_reg2$next[4:0]$2019 \core_reg2
+ assign $2\core_reg2_ok$next[0:0]$2020 \core_reg2_ok
+ assign $2\core_reg3$next[4:0]$2021 \core_reg3
+ assign $2\core_reg3_ok$next[0:0]$2022 \core_reg3_ok
+ assign $2\core_rego$next[4:0]$2023 \core_rego
+ assign $2\core_rego_ok$next[0:0]$2024 \core_rego_ok
+ assign $2\core_spr1$next[9:0]$2025 \core_spr1
+ assign $2\core_spr1_ok$next[0:0]$2026 \core_spr1_ok
+ assign $2\core_spro$next[9:0]$2027 \core_spro
+ assign $2\core_spro_ok$next[0:0]$2028 \core_spro_ok
+ assign $2\core_xer_in$next[2:0]$2029 \core_xer_in
+ assign $2\core_xer_out$next[0:0]$2030 \core_xer_out
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign { $2\core_core_is_32bit$next[0:0]$1989 $2\core_core_cr_wr_ok$next[0:0]$1976 $2\core_core_cr_wr$next[7:0]$1975 $2\core_core_cr_rd_ok$next[0:0]$1974 $2\core_core_cr_rd$next[7:0]$1973 $2\core_core_trapaddr$next[12:0]$1996 $2\core_core_exc_$signal$56$next[0:0]$1983 $2\core_core_exc_$signal$55$next[0:0]$1982 $2\core_core_exc_$signal$54$next[0:0]$1981 $2\core_core_exc_$signal$53$next[0:0]$1980 $2\core_core_exc_$signal$52$next[0:0]$1979 $2\core_core_exc_$signal$51$next[0:0]$1978 $2\core_core_exc_$signal$50$next[0:0]$1977 $2\core_core_exc_$signal$next[0:0]$1984 $2\core_core_traptype$next[7:0]$1997 $2\core_core_input_carry$next[1:0]$1986 $2\core_core_oe_ok$next[0:0]$1993 $2\core_core_oe$next[0:0]$1992 $2\core_core_rc_ok$next[0:0]$1995 $2\core_core_rc$next[0:0]$1994 $2\core_core_lk$next[0:0]$1990 $2\core_core_fn_unit$next[11:0]$1985 $2\core_core_insn_type$next[6:0]$1988 $2\core_core_insn$next[31:0]$1987 $2\core_core_cia$next[63:0]$1972 $2\core_core_msr$next[63:0]$1991 $2\core_cr_out_ok$next[0:0]$2005 $2\core_cr_out$next[2:0]$2004 $2\core_cr_in2_ok$49$next[0:0]$2002 $2\core_cr_in2$48$next[2:0]$2000 $2\core_cr_in2_ok$next[0:0]$2003 $2\core_cr_in2$next[2:0]$2001 $2\core_cr_in1_ok$next[0:0]$1999 $2\core_cr_in1$next[2:0]$1998 $2\core_fasto2_ok$next[0:0]$2015 $2\core_fasto2$next[2:0]$2014 $2\core_fasto1_ok$next[0:0]$2013 $2\core_fasto1$next[2:0]$2012 $2\core_fast2_ok$next[0:0]$2011 $2\core_fast2$next[2:0]$2010 $2\core_fast1_ok$next[0:0]$2009 $2\core_fast1$next[2:0]$2008 $2\core_xer_out$next[0:0]$2029 $2\core_xer_in$next[2:0]$2028 $2\core_spr1_ok$next[0:0]$2025 $2\core_spr1$next[9:0]$2024 $2\core_spro_ok$next[0:0]$2027 $2\core_spro$next[9:0]$2026 $2\core_reg3_ok$next[0:0]$2021 $2\core_reg3$next[4:0]$2020 $2\core_reg2_ok$next[0:0]$2019 $2\core_reg2$next[4:0]$2018 $2\core_reg1_ok$next[0:0]$2017 $2\core_reg1$next[4:0]$2016 $2\core_ea_ok$next[0:0]$2007 $2\core_ea$next[4:0]$2006 $2\core_rego_ok$next[0:0]$2023 $2\core_rego$next[4:0]$2022 $2\core_asmcode$next[7:0]$1971 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$9 \dec2_exc_$signal$8 \dec2_exc_$signal$7 \dec2_exc_$signal$6 \dec2_exc_$signal$5 \dec2_exc_$signal$4 \dec2_exc_$signal$3 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
+ assign { $2\core_core_is_32bit$next[0:0]$1990 $2\core_core_cr_wr_ok$next[0:0]$1977 $2\core_core_cr_wr$next[7:0]$1976 $2\core_core_cr_rd_ok$next[0:0]$1975 $2\core_core_cr_rd$next[7:0]$1974 $2\core_core_trapaddr$next[12:0]$1997 $2\core_core_exc_$signal$56$next[0:0]$1984 $2\core_core_exc_$signal$55$next[0:0]$1983 $2\core_core_exc_$signal$54$next[0:0]$1982 $2\core_core_exc_$signal$53$next[0:0]$1981 $2\core_core_exc_$signal$52$next[0:0]$1980 $2\core_core_exc_$signal$51$next[0:0]$1979 $2\core_core_exc_$signal$50$next[0:0]$1978 $2\core_core_exc_$signal$next[0:0]$1985 $2\core_core_traptype$next[7:0]$1998 $2\core_core_input_carry$next[1:0]$1987 $2\core_core_oe_ok$next[0:0]$1994 $2\core_core_oe$next[0:0]$1993 $2\core_core_rc_ok$next[0:0]$1996 $2\core_core_rc$next[0:0]$1995 $2\core_core_lk$next[0:0]$1991 $2\core_core_fn_unit$next[11:0]$1986 $2\core_core_insn_type$next[6:0]$1989 $2\core_core_insn$next[31:0]$1988 $2\core_core_cia$next[63:0]$1973 $2\core_core_msr$next[63:0]$1992 $2\core_cr_out_ok$next[0:0]$2006 $2\core_cr_out$next[2:0]$2005 $2\core_cr_in2_ok$49$next[0:0]$2003 $2\core_cr_in2$48$next[2:0]$2001 $2\core_cr_in2_ok$next[0:0]$2004 $2\core_cr_in2$next[2:0]$2002 $2\core_cr_in1_ok$next[0:0]$2000 $2\core_cr_in1$next[2:0]$1999 $2\core_fasto2_ok$next[0:0]$2016 $2\core_fasto2$next[2:0]$2015 $2\core_fasto1_ok$next[0:0]$2014 $2\core_fasto1$next[2:0]$2013 $2\core_fast2_ok$next[0:0]$2012 $2\core_fast2$next[2:0]$2011 $2\core_fast1_ok$next[0:0]$2010 $2\core_fast1$next[2:0]$2009 $2\core_xer_out$next[0:0]$2030 $2\core_xer_in$next[2:0]$2029 $2\core_spr1_ok$next[0:0]$2026 $2\core_spr1$next[9:0]$2025 $2\core_spro_ok$next[0:0]$2028 $2\core_spro$next[9:0]$2027 $2\core_reg3_ok$next[0:0]$2022 $2\core_reg3$next[4:0]$2021 $2\core_reg2_ok$next[0:0]$2020 $2\core_reg2$next[4:0]$2019 $2\core_reg1_ok$next[0:0]$2018 $2\core_reg1$next[4:0]$2017 $2\core_ea_ok$next[0:0]$2008 $2\core_ea$next[4:0]$2007 $2\core_rego_ok$next[0:0]$2024 $2\core_rego$next[4:0]$2023 $2\core_asmcode$next[7:0]$1972 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$9 \dec2_exc_$signal$8 \dec2_exc_$signal$7 \dec2_exc_$signal$6 \dec2_exc_$signal$5 \dec2_exc_$signal$4 \dec2_exc_$signal$3 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$2 \dec2_cr_in2$1 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode }
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
assign { } { }
assign { } { }
- assign $1\core_asmcode$next[7:0]$1912 $3\core_asmcode$next[7:0]$2030
- assign $1\core_core_cia$next[63:0]$1913 $3\core_core_cia$next[63:0]$2031
- assign $1\core_core_cr_rd$next[7:0]$1914 $3\core_core_cr_rd$next[7:0]$2032
- assign $1\core_core_cr_rd_ok$next[0:0]$1915 $3\core_core_cr_rd_ok$next[0:0]$2033
- assign $1\core_core_cr_wr$next[7:0]$1916 $3\core_core_cr_wr$next[7:0]$2034
- assign $1\core_core_cr_wr_ok$next[0:0]$1917 $3\core_core_cr_wr_ok$next[0:0]$2035
- assign $1\core_core_exc_$signal$50$next[0:0]$1918 $3\core_core_exc_$signal$50$next[0:0]$2036
- assign $1\core_core_exc_$signal$51$next[0:0]$1919 $3\core_core_exc_$signal$51$next[0:0]$2037
- assign $1\core_core_exc_$signal$52$next[0:0]$1920 $3\core_core_exc_$signal$52$next[0:0]$2038
- assign $1\core_core_exc_$signal$53$next[0:0]$1921 $3\core_core_exc_$signal$53$next[0:0]$2039
- assign $1\core_core_exc_$signal$54$next[0:0]$1922 $3\core_core_exc_$signal$54$next[0:0]$2040
- assign $1\core_core_exc_$signal$55$next[0:0]$1923 $3\core_core_exc_$signal$55$next[0:0]$2041
- assign $1\core_core_exc_$signal$56$next[0:0]$1924 $3\core_core_exc_$signal$56$next[0:0]$2042
- assign $1\core_core_exc_$signal$next[0:0]$1925 $3\core_core_exc_$signal$next[0:0]$2043
- assign $1\core_core_fn_unit$next[11:0]$1926 $3\core_core_fn_unit$next[11:0]$2044
- assign $1\core_core_input_carry$next[1:0]$1927 $3\core_core_input_carry$next[1:0]$2045
- assign $1\core_core_insn$next[31:0]$1928 $3\core_core_insn$next[31:0]$2046
- assign $1\core_core_insn_type$next[6:0]$1929 $3\core_core_insn_type$next[6:0]$2047
- assign $1\core_core_is_32bit$next[0:0]$1930 $3\core_core_is_32bit$next[0:0]$2048
- assign $1\core_core_lk$next[0:0]$1931 $3\core_core_lk$next[0:0]$2049
- assign $1\core_core_msr$next[63:0]$1932 $3\core_core_msr$next[63:0]$2050
- assign $1\core_core_oe$next[0:0]$1933 $3\core_core_oe$next[0:0]$2051
- assign $1\core_core_oe_ok$next[0:0]$1934 $3\core_core_oe_ok$next[0:0]$2052
- assign $1\core_core_rc$next[0:0]$1935 $3\core_core_rc$next[0:0]$2053
- assign $1\core_core_rc_ok$next[0:0]$1936 $3\core_core_rc_ok$next[0:0]$2054
- assign $1\core_core_trapaddr$next[12:0]$1937 $3\core_core_trapaddr$next[12:0]$2055
- assign $1\core_core_traptype$next[7:0]$1938 $3\core_core_traptype$next[7:0]$2056
- assign $1\core_cr_in1$next[2:0]$1939 $3\core_cr_in1$next[2:0]$2057
- assign $1\core_cr_in1_ok$next[0:0]$1940 $3\core_cr_in1_ok$next[0:0]$2058
- assign $1\core_cr_in2$48$next[2:0]$1941 $3\core_cr_in2$48$next[2:0]$2059
- assign $1\core_cr_in2$next[2:0]$1942 $3\core_cr_in2$next[2:0]$2060
- assign $1\core_cr_in2_ok$49$next[0:0]$1943 $3\core_cr_in2_ok$49$next[0:0]$2061
- assign $1\core_cr_in2_ok$next[0:0]$1944 $3\core_cr_in2_ok$next[0:0]$2062
- assign $1\core_cr_out$next[2:0]$1945 $3\core_cr_out$next[2:0]$2063
- assign $1\core_cr_out_ok$next[0:0]$1946 $3\core_cr_out_ok$next[0:0]$2064
- assign $1\core_ea$next[4:0]$1947 $3\core_ea$next[4:0]$2065
- assign $1\core_ea_ok$next[0:0]$1948 $3\core_ea_ok$next[0:0]$2066
- assign $1\core_fast1$next[2:0]$1949 $3\core_fast1$next[2:0]$2067
- assign $1\core_fast1_ok$next[0:0]$1950 $3\core_fast1_ok$next[0:0]$2068
- assign $1\core_fast2$next[2:0]$1951 $3\core_fast2$next[2:0]$2069
- assign $1\core_fast2_ok$next[0:0]$1952 $3\core_fast2_ok$next[0:0]$2070
- assign $1\core_fasto1$next[2:0]$1953 $3\core_fasto1$next[2:0]$2071
- assign $1\core_fasto1_ok$next[0:0]$1954 $3\core_fasto1_ok$next[0:0]$2072
- assign $1\core_fasto2$next[2:0]$1955 $3\core_fasto2$next[2:0]$2073
- assign $1\core_fasto2_ok$next[0:0]$1956 $3\core_fasto2_ok$next[0:0]$2074
- assign $1\core_reg1$next[4:0]$1957 $3\core_reg1$next[4:0]$2075
- assign $1\core_reg1_ok$next[0:0]$1958 $3\core_reg1_ok$next[0:0]$2076
- assign $1\core_reg2$next[4:0]$1959 $3\core_reg2$next[4:0]$2077
- assign $1\core_reg2_ok$next[0:0]$1960 $3\core_reg2_ok$next[0:0]$2078
- assign $1\core_reg3$next[4:0]$1961 $3\core_reg3$next[4:0]$2079
- assign $1\core_reg3_ok$next[0:0]$1962 $3\core_reg3_ok$next[0:0]$2080
- assign $1\core_rego$next[4:0]$1963 $3\core_rego$next[4:0]$2081
- assign $1\core_rego_ok$next[0:0]$1964 $3\core_rego_ok$next[0:0]$2082
- assign $1\core_spr1$next[9:0]$1965 $3\core_spr1$next[9:0]$2083
- assign $1\core_spr1_ok$next[0:0]$1966 $3\core_spr1_ok$next[0:0]$2084
- assign $1\core_spro$next[9:0]$1967 $3\core_spro$next[9:0]$2085
- assign $1\core_spro_ok$next[0:0]$1968 $3\core_spro_ok$next[0:0]$2086
- assign $1\core_xer_in$next[2:0]$1969 $3\core_xer_in$next[2:0]$2087
- assign $1\core_xer_out$next[0:0]$1970 $3\core_xer_out$next[0:0]$2088
+ assign $1\core_asmcode$next[7:0]$1913 $3\core_asmcode$next[7:0]$2031
+ assign $1\core_core_cia$next[63:0]$1914 $3\core_core_cia$next[63:0]$2032
+ assign $1\core_core_cr_rd$next[7:0]$1915 $3\core_core_cr_rd$next[7:0]$2033
+ assign $1\core_core_cr_rd_ok$next[0:0]$1916 $3\core_core_cr_rd_ok$next[0:0]$2034
+ assign $1\core_core_cr_wr$next[7:0]$1917 $3\core_core_cr_wr$next[7:0]$2035
+ assign $1\core_core_cr_wr_ok$next[0:0]$1918 $3\core_core_cr_wr_ok$next[0:0]$2036
+ assign $1\core_core_exc_$signal$50$next[0:0]$1919 $3\core_core_exc_$signal$50$next[0:0]$2037
+ assign $1\core_core_exc_$signal$51$next[0:0]$1920 $3\core_core_exc_$signal$51$next[0:0]$2038
+ assign $1\core_core_exc_$signal$52$next[0:0]$1921 $3\core_core_exc_$signal$52$next[0:0]$2039
+ assign $1\core_core_exc_$signal$53$next[0:0]$1922 $3\core_core_exc_$signal$53$next[0:0]$2040
+ assign $1\core_core_exc_$signal$54$next[0:0]$1923 $3\core_core_exc_$signal$54$next[0:0]$2041
+ assign $1\core_core_exc_$signal$55$next[0:0]$1924 $3\core_core_exc_$signal$55$next[0:0]$2042
+ assign $1\core_core_exc_$signal$56$next[0:0]$1925 $3\core_core_exc_$signal$56$next[0:0]$2043
+ assign $1\core_core_exc_$signal$next[0:0]$1926 $3\core_core_exc_$signal$next[0:0]$2044
+ assign $1\core_core_fn_unit$next[11:0]$1927 $3\core_core_fn_unit$next[11:0]$2045
+ assign $1\core_core_input_carry$next[1:0]$1928 $3\core_core_input_carry$next[1:0]$2046
+ assign $1\core_core_insn$next[31:0]$1929 $3\core_core_insn$next[31:0]$2047
+ assign $1\core_core_insn_type$next[6:0]$1930 $3\core_core_insn_type$next[6:0]$2048
+ assign $1\core_core_is_32bit$next[0:0]$1931 $3\core_core_is_32bit$next[0:0]$2049
+ assign $1\core_core_lk$next[0:0]$1932 $3\core_core_lk$next[0:0]$2050
+ assign $1\core_core_msr$next[63:0]$1933 $3\core_core_msr$next[63:0]$2051
+ assign $1\core_core_oe$next[0:0]$1934 $3\core_core_oe$next[0:0]$2052
+ assign $1\core_core_oe_ok$next[0:0]$1935 $3\core_core_oe_ok$next[0:0]$2053
+ assign $1\core_core_rc$next[0:0]$1936 $3\core_core_rc$next[0:0]$2054
+ assign $1\core_core_rc_ok$next[0:0]$1937 $3\core_core_rc_ok$next[0:0]$2055
+ assign $1\core_core_trapaddr$next[12:0]$1938 $3\core_core_trapaddr$next[12:0]$2056
+ assign $1\core_core_traptype$next[7:0]$1939 $3\core_core_traptype$next[7:0]$2057
+ assign $1\core_cr_in1$next[2:0]$1940 $3\core_cr_in1$next[2:0]$2058
+ assign $1\core_cr_in1_ok$next[0:0]$1941 $3\core_cr_in1_ok$next[0:0]$2059
+ assign $1\core_cr_in2$48$next[2:0]$1942 $3\core_cr_in2$48$next[2:0]$2060
+ assign $1\core_cr_in2$next[2:0]$1943 $3\core_cr_in2$next[2:0]$2061
+ assign $1\core_cr_in2_ok$49$next[0:0]$1944 $3\core_cr_in2_ok$49$next[0:0]$2062
+ assign $1\core_cr_in2_ok$next[0:0]$1945 $3\core_cr_in2_ok$next[0:0]$2063
+ assign $1\core_cr_out$next[2:0]$1946 $3\core_cr_out$next[2:0]$2064
+ assign $1\core_cr_out_ok$next[0:0]$1947 $3\core_cr_out_ok$next[0:0]$2065
+ assign $1\core_ea$next[4:0]$1948 $3\core_ea$next[4:0]$2066
+ assign $1\core_ea_ok$next[0:0]$1949 $3\core_ea_ok$next[0:0]$2067
+ assign $1\core_fast1$next[2:0]$1950 $3\core_fast1$next[2:0]$2068
+ assign $1\core_fast1_ok$next[0:0]$1951 $3\core_fast1_ok$next[0:0]$2069
+ assign $1\core_fast2$next[2:0]$1952 $3\core_fast2$next[2:0]$2070
+ assign $1\core_fast2_ok$next[0:0]$1953 $3\core_fast2_ok$next[0:0]$2071
+ assign $1\core_fasto1$next[2:0]$1954 $3\core_fasto1$next[2:0]$2072
+ assign $1\core_fasto1_ok$next[0:0]$1955 $3\core_fasto1_ok$next[0:0]$2073
+ assign $1\core_fasto2$next[2:0]$1956 $3\core_fasto2$next[2:0]$2074
+ assign $1\core_fasto2_ok$next[0:0]$1957 $3\core_fasto2_ok$next[0:0]$2075
+ assign $1\core_reg1$next[4:0]$1958 $3\core_reg1$next[4:0]$2076
+ assign $1\core_reg1_ok$next[0:0]$1959 $3\core_reg1_ok$next[0:0]$2077
+ assign $1\core_reg2$next[4:0]$1960 $3\core_reg2$next[4:0]$2078
+ assign $1\core_reg2_ok$next[0:0]$1961 $3\core_reg2_ok$next[0:0]$2079
+ assign $1\core_reg3$next[4:0]$1962 $3\core_reg3$next[4:0]$2080
+ assign $1\core_reg3_ok$next[0:0]$1963 $3\core_reg3_ok$next[0:0]$2081
+ assign $1\core_rego$next[4:0]$1964 $3\core_rego$next[4:0]$2082
+ assign $1\core_rego_ok$next[0:0]$1965 $3\core_rego_ok$next[0:0]$2083
+ assign $1\core_spr1$next[9:0]$1966 $3\core_spr1$next[9:0]$2084
+ assign $1\core_spr1_ok$next[0:0]$1967 $3\core_spr1_ok$next[0:0]$2085
+ assign $1\core_spro$next[9:0]$1968 $3\core_spro$next[9:0]$2086
+ assign $1\core_spro_ok$next[0:0]$1969 $3\core_spro_ok$next[0:0]$2087
+ assign $1\core_xer_in$next[2:0]$1970 $3\core_xer_in$next[2:0]$2088
+ assign $1\core_xer_out$next[0:0]$1971 $3\core_xer_out$next[0:0]$2089
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
switch \$57
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign { $3\core_core_is_32bit$next[0:0]$2048 $3\core_core_cr_wr_ok$next[0:0]$2035 $3\core_core_cr_wr$next[7:0]$2034 $3\core_core_cr_rd_ok$next[0:0]$2033 $3\core_core_cr_rd$next[7:0]$2032 $3\core_core_trapaddr$next[12:0]$2055 $3\core_core_exc_$signal$56$next[0:0]$2042 $3\core_core_exc_$signal$55$next[0:0]$2041 $3\core_core_exc_$signal$54$next[0:0]$2040 $3\core_core_exc_$signal$53$next[0:0]$2039 $3\core_core_exc_$signal$52$next[0:0]$2038 $3\core_core_exc_$signal$51$next[0:0]$2037 $3\core_core_exc_$signal$50$next[0:0]$2036 $3\core_core_exc_$signal$next[0:0]$2043 $3\core_core_traptype$next[7:0]$2056 $3\core_core_input_carry$next[1:0]$2045 $3\core_core_oe_ok$next[0:0]$2052 $3\core_core_oe$next[0:0]$2051 $3\core_core_rc_ok$next[0:0]$2054 $3\core_core_rc$next[0:0]$2053 $3\core_core_lk$next[0:0]$2049 $3\core_core_fn_unit$next[11:0]$2044 $3\core_core_insn_type$next[6:0]$2047 $3\core_core_insn$next[31:0]$2046 $3\core_core_cia$next[63:0]$2031 $3\core_core_msr$next[63:0]$2050 $3\core_cr_out_ok$next[0:0]$2064 $3\core_cr_out$next[2:0]$2063 $3\core_cr_in2_ok$49$next[0:0]$2061 $3\core_cr_in2$48$next[2:0]$2059 $3\core_cr_in2_ok$next[0:0]$2062 $3\core_cr_in2$next[2:0]$2060 $3\core_cr_in1_ok$next[0:0]$2058 $3\core_cr_in1$next[2:0]$2057 $3\core_fasto2_ok$next[0:0]$2074 $3\core_fasto2$next[2:0]$2073 $3\core_fasto1_ok$next[0:0]$2072 $3\core_fasto1$next[2:0]$2071 $3\core_fast2_ok$next[0:0]$2070 $3\core_fast2$next[2:0]$2069 $3\core_fast1_ok$next[0:0]$2068 $3\core_fast1$next[2:0]$2067 $3\core_xer_out$next[0:0]$2088 $3\core_xer_in$next[2:0]$2087 $3\core_spr1_ok$next[0:0]$2084 $3\core_spr1$next[9:0]$2083 $3\core_spro_ok$next[0:0]$2086 $3\core_spro$next[9:0]$2085 $3\core_reg3_ok$next[0:0]$2080 $3\core_reg3$next[4:0]$2079 $3\core_reg2_ok$next[0:0]$2078 $3\core_reg2$next[4:0]$2077 $3\core_reg1_ok$next[0:0]$2076 $3\core_reg1$next[4:0]$2075 $3\core_ea_ok$next[0:0]$2066 $3\core_ea$next[4:0]$2065 $3\core_rego_ok$next[0:0]$2082 $3\core_rego$next[4:0]$2081 $3\core_asmcode$next[7:0]$2030 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign { $3\core_core_is_32bit$next[0:0]$2049 $3\core_core_cr_wr_ok$next[0:0]$2036 $3\core_core_cr_wr$next[7:0]$2035 $3\core_core_cr_rd_ok$next[0:0]$2034 $3\core_core_cr_rd$next[7:0]$2033 $3\core_core_trapaddr$next[12:0]$2056 $3\core_core_exc_$signal$56$next[0:0]$2043 $3\core_core_exc_$signal$55$next[0:0]$2042 $3\core_core_exc_$signal$54$next[0:0]$2041 $3\core_core_exc_$signal$53$next[0:0]$2040 $3\core_core_exc_$signal$52$next[0:0]$2039 $3\core_core_exc_$signal$51$next[0:0]$2038 $3\core_core_exc_$signal$50$next[0:0]$2037 $3\core_core_exc_$signal$next[0:0]$2044 $3\core_core_traptype$next[7:0]$2057 $3\core_core_input_carry$next[1:0]$2046 $3\core_core_oe_ok$next[0:0]$2053 $3\core_core_oe$next[0:0]$2052 $3\core_core_rc_ok$next[0:0]$2055 $3\core_core_rc$next[0:0]$2054 $3\core_core_lk$next[0:0]$2050 $3\core_core_fn_unit$next[11:0]$2045 $3\core_core_insn_type$next[6:0]$2048 $3\core_core_insn$next[31:0]$2047 $3\core_core_cia$next[63:0]$2032 $3\core_core_msr$next[63:0]$2051 $3\core_cr_out_ok$next[0:0]$2065 $3\core_cr_out$next[2:0]$2064 $3\core_cr_in2_ok$49$next[0:0]$2062 $3\core_cr_in2$48$next[2:0]$2060 $3\core_cr_in2_ok$next[0:0]$2063 $3\core_cr_in2$next[2:0]$2061 $3\core_cr_in1_ok$next[0:0]$2059 $3\core_cr_in1$next[2:0]$2058 $3\core_fasto2_ok$next[0:0]$2075 $3\core_fasto2$next[2:0]$2074 $3\core_fasto1_ok$next[0:0]$2073 $3\core_fasto1$next[2:0]$2072 $3\core_fast2_ok$next[0:0]$2071 $3\core_fast2$next[2:0]$2070 $3\core_fast1_ok$next[0:0]$2069 $3\core_fast1$next[2:0]$2068 $3\core_xer_out$next[0:0]$2089 $3\core_xer_in$next[2:0]$2088 $3\core_spr1_ok$next[0:0]$2085 $3\core_spr1$next[9:0]$2084 $3\core_spro_ok$next[0:0]$2087 $3\core_spro$next[9:0]$2086 $3\core_reg3_ok$next[0:0]$2081 $3\core_reg3$next[4:0]$2080 $3\core_reg2_ok$next[0:0]$2079 $3\core_reg2$next[4:0]$2078 $3\core_reg1_ok$next[0:0]$2077 $3\core_reg1$next[4:0]$2076 $3\core_ea_ok$next[0:0]$2067 $3\core_ea$next[4:0]$2066 $3\core_rego_ok$next[0:0]$2083 $3\core_rego$next[4:0]$2082 $3\core_asmcode$next[7:0]$2031 } 330'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\core_asmcode$next[7:0]$2030 \core_asmcode
- assign $3\core_core_cia$next[63:0]$2031 \core_core_cia
- assign $3\core_core_cr_rd$next[7:0]$2032 \core_core_cr_rd
- assign $3\core_core_cr_rd_ok$next[0:0]$2033 \core_core_cr_rd_ok
- assign $3\core_core_cr_wr$next[7:0]$2034 \core_core_cr_wr
- assign $3\core_core_cr_wr_ok$next[0:0]$2035 \core_core_cr_wr_ok
- assign $3\core_core_exc_$signal$50$next[0:0]$2036 \core_core_exc_$signal$50
- assign $3\core_core_exc_$signal$51$next[0:0]$2037 \core_core_exc_$signal$51
- assign $3\core_core_exc_$signal$52$next[0:0]$2038 \core_core_exc_$signal$52
- assign $3\core_core_exc_$signal$53$next[0:0]$2039 \core_core_exc_$signal$53
- assign $3\core_core_exc_$signal$54$next[0:0]$2040 \core_core_exc_$signal$54
- assign $3\core_core_exc_$signal$55$next[0:0]$2041 \core_core_exc_$signal$55
- assign $3\core_core_exc_$signal$56$next[0:0]$2042 \core_core_exc_$signal$56
- assign $3\core_core_exc_$signal$next[0:0]$2043 \core_core_exc_$signal
- assign $3\core_core_fn_unit$next[11:0]$2044 \core_core_fn_unit
- assign $3\core_core_input_carry$next[1:0]$2045 \core_core_input_carry
- assign $3\core_core_insn$next[31:0]$2046 \core_core_insn
- assign $3\core_core_insn_type$next[6:0]$2047 \core_core_insn_type
- assign $3\core_core_is_32bit$next[0:0]$2048 \core_core_is_32bit
- assign $3\core_core_lk$next[0:0]$2049 \core_core_lk
- assign $3\core_core_msr$next[63:0]$2050 \core_core_msr
- assign $3\core_core_oe$next[0:0]$2051 \core_core_oe
- assign $3\core_core_oe_ok$next[0:0]$2052 \core_core_oe_ok
- assign $3\core_core_rc$next[0:0]$2053 \core_core_rc
- assign $3\core_core_rc_ok$next[0:0]$2054 \core_core_rc_ok
- assign $3\core_core_trapaddr$next[12:0]$2055 \core_core_trapaddr
- assign $3\core_core_traptype$next[7:0]$2056 \core_core_traptype
- assign $3\core_cr_in1$next[2:0]$2057 \core_cr_in1
- assign $3\core_cr_in1_ok$next[0:0]$2058 \core_cr_in1_ok
- assign $3\core_cr_in2$48$next[2:0]$2059 \core_cr_in2$48
- assign $3\core_cr_in2$next[2:0]$2060 \core_cr_in2
- assign $3\core_cr_in2_ok$49$next[0:0]$2061 \core_cr_in2_ok$49
- assign $3\core_cr_in2_ok$next[0:0]$2062 \core_cr_in2_ok
- assign $3\core_cr_out$next[2:0]$2063 \core_cr_out
- assign $3\core_cr_out_ok$next[0:0]$2064 \core_cr_out_ok
- assign $3\core_ea$next[4:0]$2065 \core_ea
- assign $3\core_ea_ok$next[0:0]$2066 \core_ea_ok
- assign $3\core_fast1$next[2:0]$2067 \core_fast1
- assign $3\core_fast1_ok$next[0:0]$2068 \core_fast1_ok
- assign $3\core_fast2$next[2:0]$2069 \core_fast2
- assign $3\core_fast2_ok$next[0:0]$2070 \core_fast2_ok
- assign $3\core_fasto1$next[2:0]$2071 \core_fasto1
- assign $3\core_fasto1_ok$next[0:0]$2072 \core_fasto1_ok
- assign $3\core_fasto2$next[2:0]$2073 \core_fasto2
- assign $3\core_fasto2_ok$next[0:0]$2074 \core_fasto2_ok
- assign $3\core_reg1$next[4:0]$2075 \core_reg1
- assign $3\core_reg1_ok$next[0:0]$2076 \core_reg1_ok
- assign $3\core_reg2$next[4:0]$2077 \core_reg2
- assign $3\core_reg2_ok$next[0:0]$2078 \core_reg2_ok
- assign $3\core_reg3$next[4:0]$2079 \core_reg3
- assign $3\core_reg3_ok$next[0:0]$2080 \core_reg3_ok
- assign $3\core_rego$next[4:0]$2081 \core_rego
- assign $3\core_rego_ok$next[0:0]$2082 \core_rego_ok
- assign $3\core_spr1$next[9:0]$2083 \core_spr1
- assign $3\core_spr1_ok$next[0:0]$2084 \core_spr1_ok
- assign $3\core_spro$next[9:0]$2085 \core_spro
- assign $3\core_spro_ok$next[0:0]$2086 \core_spro_ok
- assign $3\core_xer_in$next[2:0]$2087 \core_xer_in
- assign $3\core_xer_out$next[0:0]$2088 \core_xer_out
+ assign $3\core_asmcode$next[7:0]$2031 \core_asmcode
+ assign $3\core_core_cia$next[63:0]$2032 \core_core_cia
+ assign $3\core_core_cr_rd$next[7:0]$2033 \core_core_cr_rd
+ assign $3\core_core_cr_rd_ok$next[0:0]$2034 \core_core_cr_rd_ok
+ assign $3\core_core_cr_wr$next[7:0]$2035 \core_core_cr_wr
+ assign $3\core_core_cr_wr_ok$next[0:0]$2036 \core_core_cr_wr_ok
+ assign $3\core_core_exc_$signal$50$next[0:0]$2037 \core_core_exc_$signal$50
+ assign $3\core_core_exc_$signal$51$next[0:0]$2038 \core_core_exc_$signal$51
+ assign $3\core_core_exc_$signal$52$next[0:0]$2039 \core_core_exc_$signal$52
+ assign $3\core_core_exc_$signal$53$next[0:0]$2040 \core_core_exc_$signal$53
+ assign $3\core_core_exc_$signal$54$next[0:0]$2041 \core_core_exc_$signal$54
+ assign $3\core_core_exc_$signal$55$next[0:0]$2042 \core_core_exc_$signal$55
+ assign $3\core_core_exc_$signal$56$next[0:0]$2043 \core_core_exc_$signal$56
+ assign $3\core_core_exc_$signal$next[0:0]$2044 \core_core_exc_$signal
+ assign $3\core_core_fn_unit$next[11:0]$2045 \core_core_fn_unit
+ assign $3\core_core_input_carry$next[1:0]$2046 \core_core_input_carry
+ assign $3\core_core_insn$next[31:0]$2047 \core_core_insn
+ assign $3\core_core_insn_type$next[6:0]$2048 \core_core_insn_type
+ assign $3\core_core_is_32bit$next[0:0]$2049 \core_core_is_32bit
+ assign $3\core_core_lk$next[0:0]$2050 \core_core_lk
+ assign $3\core_core_msr$next[63:0]$2051 \core_core_msr
+ assign $3\core_core_oe$next[0:0]$2052 \core_core_oe
+ assign $3\core_core_oe_ok$next[0:0]$2053 \core_core_oe_ok
+ assign $3\core_core_rc$next[0:0]$2054 \core_core_rc
+ assign $3\core_core_rc_ok$next[0:0]$2055 \core_core_rc_ok
+ assign $3\core_core_trapaddr$next[12:0]$2056 \core_core_trapaddr
+ assign $3\core_core_traptype$next[7:0]$2057 \core_core_traptype
+ assign $3\core_cr_in1$next[2:0]$2058 \core_cr_in1
+ assign $3\core_cr_in1_ok$next[0:0]$2059 \core_cr_in1_ok
+ assign $3\core_cr_in2$48$next[2:0]$2060 \core_cr_in2$48
+ assign $3\core_cr_in2$next[2:0]$2061 \core_cr_in2
+ assign $3\core_cr_in2_ok$49$next[0:0]$2062 \core_cr_in2_ok$49
+ assign $3\core_cr_in2_ok$next[0:0]$2063 \core_cr_in2_ok
+ assign $3\core_cr_out$next[2:0]$2064 \core_cr_out
+ assign $3\core_cr_out_ok$next[0:0]$2065 \core_cr_out_ok
+ assign $3\core_ea$next[4:0]$2066 \core_ea
+ assign $3\core_ea_ok$next[0:0]$2067 \core_ea_ok
+ assign $3\core_fast1$next[2:0]$2068 \core_fast1
+ assign $3\core_fast1_ok$next[0:0]$2069 \core_fast1_ok
+ assign $3\core_fast2$next[2:0]$2070 \core_fast2
+ assign $3\core_fast2_ok$next[0:0]$2071 \core_fast2_ok
+ assign $3\core_fasto1$next[2:0]$2072 \core_fasto1
+ assign $3\core_fasto1_ok$next[0:0]$2073 \core_fasto1_ok
+ assign $3\core_fasto2$next[2:0]$2074 \core_fasto2
+ assign $3\core_fasto2_ok$next[0:0]$2075 \core_fasto2_ok
+ assign $3\core_reg1$next[4:0]$2076 \core_reg1
+ assign $3\core_reg1_ok$next[0:0]$2077 \core_reg1_ok
+ assign $3\core_reg2$next[4:0]$2078 \core_reg2
+ assign $3\core_reg2_ok$next[0:0]$2079 \core_reg2_ok
+ assign $3\core_reg3$next[4:0]$2080 \core_reg3
+ assign $3\core_reg3_ok$next[0:0]$2081 \core_reg3_ok
+ assign $3\core_rego$next[4:0]$2082 \core_rego
+ assign $3\core_rego_ok$next[0:0]$2083 \core_rego_ok
+ assign $3\core_spr1$next[9:0]$2084 \core_spr1
+ assign $3\core_spr1_ok$next[0:0]$2085 \core_spr1_ok
+ assign $3\core_spro$next[9:0]$2086 \core_spro
+ assign $3\core_spro_ok$next[0:0]$2087 \core_spro_ok
+ assign $3\core_xer_in$next[2:0]$2088 \core_xer_in
+ assign $3\core_xer_out$next[0:0]$2089 \core_xer_out
end
case
- assign $1\core_asmcode$next[7:0]$1912 \core_asmcode
- assign $1\core_core_cia$next[63:0]$1913 \core_core_cia
- assign $1\core_core_cr_rd$next[7:0]$1914 \core_core_cr_rd
- assign $1\core_core_cr_rd_ok$next[0:0]$1915 \core_core_cr_rd_ok
- assign $1\core_core_cr_wr$next[7:0]$1916 \core_core_cr_wr
- assign $1\core_core_cr_wr_ok$next[0:0]$1917 \core_core_cr_wr_ok
- assign $1\core_core_exc_$signal$50$next[0:0]$1918 \core_core_exc_$signal$50
- assign $1\core_core_exc_$signal$51$next[0:0]$1919 \core_core_exc_$signal$51
- assign $1\core_core_exc_$signal$52$next[0:0]$1920 \core_core_exc_$signal$52
- assign $1\core_core_exc_$signal$53$next[0:0]$1921 \core_core_exc_$signal$53
- assign $1\core_core_exc_$signal$54$next[0:0]$1922 \core_core_exc_$signal$54
- assign $1\core_core_exc_$signal$55$next[0:0]$1923 \core_core_exc_$signal$55
- assign $1\core_core_exc_$signal$56$next[0:0]$1924 \core_core_exc_$signal$56
- assign $1\core_core_exc_$signal$next[0:0]$1925 \core_core_exc_$signal
- assign $1\core_core_fn_unit$next[11:0]$1926 \core_core_fn_unit
- assign $1\core_core_input_carry$next[1:0]$1927 \core_core_input_carry
- assign $1\core_core_insn$next[31:0]$1928 \core_core_insn
- assign $1\core_core_insn_type$next[6:0]$1929 \core_core_insn_type
- assign $1\core_core_is_32bit$next[0:0]$1930 \core_core_is_32bit
- assign $1\core_core_lk$next[0:0]$1931 \core_core_lk
- assign $1\core_core_msr$next[63:0]$1932 \core_core_msr
- assign $1\core_core_oe$next[0:0]$1933 \core_core_oe
- assign $1\core_core_oe_ok$next[0:0]$1934 \core_core_oe_ok
- assign $1\core_core_rc$next[0:0]$1935 \core_core_rc
- assign $1\core_core_rc_ok$next[0:0]$1936 \core_core_rc_ok
- assign $1\core_core_trapaddr$next[12:0]$1937 \core_core_trapaddr
- assign $1\core_core_traptype$next[7:0]$1938 \core_core_traptype
- assign $1\core_cr_in1$next[2:0]$1939 \core_cr_in1
- assign $1\core_cr_in1_ok$next[0:0]$1940 \core_cr_in1_ok
- assign $1\core_cr_in2$48$next[2:0]$1941 \core_cr_in2$48
- assign $1\core_cr_in2$next[2:0]$1942 \core_cr_in2
- assign $1\core_cr_in2_ok$49$next[0:0]$1943 \core_cr_in2_ok$49
- assign $1\core_cr_in2_ok$next[0:0]$1944 \core_cr_in2_ok
- assign $1\core_cr_out$next[2:0]$1945 \core_cr_out
- assign $1\core_cr_out_ok$next[0:0]$1946 \core_cr_out_ok
- assign $1\core_ea$next[4:0]$1947 \core_ea
- assign $1\core_ea_ok$next[0:0]$1948 \core_ea_ok
- assign $1\core_fast1$next[2:0]$1949 \core_fast1
- assign $1\core_fast1_ok$next[0:0]$1950 \core_fast1_ok
- assign $1\core_fast2$next[2:0]$1951 \core_fast2
- assign $1\core_fast2_ok$next[0:0]$1952 \core_fast2_ok
- assign $1\core_fasto1$next[2:0]$1953 \core_fasto1
- assign $1\core_fasto1_ok$next[0:0]$1954 \core_fasto1_ok
- assign $1\core_fasto2$next[2:0]$1955 \core_fasto2
- assign $1\core_fasto2_ok$next[0:0]$1956 \core_fasto2_ok
- assign $1\core_reg1$next[4:0]$1957 \core_reg1
- assign $1\core_reg1_ok$next[0:0]$1958 \core_reg1_ok
- assign $1\core_reg2$next[4:0]$1959 \core_reg2
- assign $1\core_reg2_ok$next[0:0]$1960 \core_reg2_ok
- assign $1\core_reg3$next[4:0]$1961 \core_reg3
- assign $1\core_reg3_ok$next[0:0]$1962 \core_reg3_ok
- assign $1\core_rego$next[4:0]$1963 \core_rego
- assign $1\core_rego_ok$next[0:0]$1964 \core_rego_ok
- assign $1\core_spr1$next[9:0]$1965 \core_spr1
- assign $1\core_spr1_ok$next[0:0]$1966 \core_spr1_ok
- assign $1\core_spro$next[9:0]$1967 \core_spro
- assign $1\core_spro_ok$next[0:0]$1968 \core_spro_ok
- assign $1\core_xer_in$next[2:0]$1969 \core_xer_in
- assign $1\core_xer_out$next[0:0]$1970 \core_xer_out
+ assign $1\core_asmcode$next[7:0]$1913 \core_asmcode
+ assign $1\core_core_cia$next[63:0]$1914 \core_core_cia
+ assign $1\core_core_cr_rd$next[7:0]$1915 \core_core_cr_rd
+ assign $1\core_core_cr_rd_ok$next[0:0]$1916 \core_core_cr_rd_ok
+ assign $1\core_core_cr_wr$next[7:0]$1917 \core_core_cr_wr
+ assign $1\core_core_cr_wr_ok$next[0:0]$1918 \core_core_cr_wr_ok
+ assign $1\core_core_exc_$signal$50$next[0:0]$1919 \core_core_exc_$signal$50
+ assign $1\core_core_exc_$signal$51$next[0:0]$1920 \core_core_exc_$signal$51
+ assign $1\core_core_exc_$signal$52$next[0:0]$1921 \core_core_exc_$signal$52
+ assign $1\core_core_exc_$signal$53$next[0:0]$1922 \core_core_exc_$signal$53
+ assign $1\core_core_exc_$signal$54$next[0:0]$1923 \core_core_exc_$signal$54
+ assign $1\core_core_exc_$signal$55$next[0:0]$1924 \core_core_exc_$signal$55
+ assign $1\core_core_exc_$signal$56$next[0:0]$1925 \core_core_exc_$signal$56
+ assign $1\core_core_exc_$signal$next[0:0]$1926 \core_core_exc_$signal
+ assign $1\core_core_fn_unit$next[11:0]$1927 \core_core_fn_unit
+ assign $1\core_core_input_carry$next[1:0]$1928 \core_core_input_carry
+ assign $1\core_core_insn$next[31:0]$1929 \core_core_insn
+ assign $1\core_core_insn_type$next[6:0]$1930 \core_core_insn_type
+ assign $1\core_core_is_32bit$next[0:0]$1931 \core_core_is_32bit
+ assign $1\core_core_lk$next[0:0]$1932 \core_core_lk
+ assign $1\core_core_msr$next[63:0]$1933 \core_core_msr
+ assign $1\core_core_oe$next[0:0]$1934 \core_core_oe
+ assign $1\core_core_oe_ok$next[0:0]$1935 \core_core_oe_ok
+ assign $1\core_core_rc$next[0:0]$1936 \core_core_rc
+ assign $1\core_core_rc_ok$next[0:0]$1937 \core_core_rc_ok
+ assign $1\core_core_trapaddr$next[12:0]$1938 \core_core_trapaddr
+ assign $1\core_core_traptype$next[7:0]$1939 \core_core_traptype
+ assign $1\core_cr_in1$next[2:0]$1940 \core_cr_in1
+ assign $1\core_cr_in1_ok$next[0:0]$1941 \core_cr_in1_ok
+ assign $1\core_cr_in2$48$next[2:0]$1942 \core_cr_in2$48
+ assign $1\core_cr_in2$next[2:0]$1943 \core_cr_in2
+ assign $1\core_cr_in2_ok$49$next[0:0]$1944 \core_cr_in2_ok$49
+ assign $1\core_cr_in2_ok$next[0:0]$1945 \core_cr_in2_ok
+ assign $1\core_cr_out$next[2:0]$1946 \core_cr_out
+ assign $1\core_cr_out_ok$next[0:0]$1947 \core_cr_out_ok
+ assign $1\core_ea$next[4:0]$1948 \core_ea
+ assign $1\core_ea_ok$next[0:0]$1949 \core_ea_ok
+ assign $1\core_fast1$next[2:0]$1950 \core_fast1
+ assign $1\core_fast1_ok$next[0:0]$1951 \core_fast1_ok
+ assign $1\core_fast2$next[2:0]$1952 \core_fast2
+ assign $1\core_fast2_ok$next[0:0]$1953 \core_fast2_ok
+ assign $1\core_fasto1$next[2:0]$1954 \core_fasto1
+ assign $1\core_fasto1_ok$next[0:0]$1955 \core_fasto1_ok
+ assign $1\core_fasto2$next[2:0]$1956 \core_fasto2
+ assign $1\core_fasto2_ok$next[0:0]$1957 \core_fasto2_ok
+ assign $1\core_reg1$next[4:0]$1958 \core_reg1
+ assign $1\core_reg1_ok$next[0:0]$1959 \core_reg1_ok
+ assign $1\core_reg2$next[4:0]$1960 \core_reg2
+ assign $1\core_reg2_ok$next[0:0]$1961 \core_reg2_ok
+ assign $1\core_reg3$next[4:0]$1962 \core_reg3
+ assign $1\core_reg3_ok$next[0:0]$1963 \core_reg3_ok
+ assign $1\core_rego$next[4:0]$1964 \core_rego
+ assign $1\core_rego_ok$next[0:0]$1965 \core_rego_ok
+ assign $1\core_spr1$next[9:0]$1966 \core_spr1
+ assign $1\core_spr1_ok$next[0:0]$1967 \core_spr1_ok
+ assign $1\core_spro$next[9:0]$1968 \core_spro
+ assign $1\core_spro_ok$next[0:0]$1969 \core_spro_ok
+ assign $1\core_xer_in$next[2:0]$1970 \core_xer_in
+ assign $1\core_xer_out$next[0:0]$1971 \core_xer_out
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $4\core_rego_ok$next[0:0]$2113 1'0
- assign $4\core_ea_ok$next[0:0]$2105 1'0
- assign $4\core_reg1_ok$next[0:0]$2110 1'0
- assign $4\core_reg2_ok$next[0:0]$2111 1'0
- assign $4\core_reg3_ok$next[0:0]$2112 1'0
- assign $4\core_spro_ok$next[0:0]$2115 1'0
- assign $4\core_spr1_ok$next[0:0]$2114 1'0
- assign $4\core_fast1_ok$next[0:0]$2106 1'0
- assign $4\core_fast2_ok$next[0:0]$2107 1'0
- assign $4\core_fasto1_ok$next[0:0]$2108 1'0
- assign $4\core_fasto2_ok$next[0:0]$2109 1'0
- assign $4\core_cr_in1_ok$next[0:0]$2101 1'0
- assign $4\core_cr_in2_ok$next[0:0]$2103 1'0
- assign $4\core_cr_in2_ok$49$next[0:0]$2102 1'0
- assign $4\core_cr_out_ok$next[0:0]$2104 1'0
- assign $4\core_core_rc_ok$next[0:0]$2100 1'0
- assign $4\core_core_oe_ok$next[0:0]$2099 1'0
- assign $4\core_core_exc_$signal$next[0:0]$2098 1'0
- assign $4\core_core_exc_$signal$50$next[0:0]$2091 1'0
- assign $4\core_core_exc_$signal$51$next[0:0]$2092 1'0
- assign $4\core_core_exc_$signal$52$next[0:0]$2093 1'0
- assign $4\core_core_exc_$signal$53$next[0:0]$2094 1'0
- assign $4\core_core_exc_$signal$54$next[0:0]$2095 1'0
- assign $4\core_core_exc_$signal$55$next[0:0]$2096 1'0
- assign $4\core_core_exc_$signal$56$next[0:0]$2097 1'0
- assign $4\core_core_cr_rd_ok$next[0:0]$2089 1'0
- assign $4\core_core_cr_wr_ok$next[0:0]$2090 1'0
+ assign $4\core_rego_ok$next[0:0]$2114 1'0
+ assign $4\core_ea_ok$next[0:0]$2106 1'0
+ assign $4\core_reg1_ok$next[0:0]$2111 1'0
+ assign $4\core_reg2_ok$next[0:0]$2112 1'0
+ assign $4\core_reg3_ok$next[0:0]$2113 1'0
+ assign $4\core_spro_ok$next[0:0]$2116 1'0
+ assign $4\core_spr1_ok$next[0:0]$2115 1'0
+ assign $4\core_fast1_ok$next[0:0]$2107 1'0
+ assign $4\core_fast2_ok$next[0:0]$2108 1'0
+ assign $4\core_fasto1_ok$next[0:0]$2109 1'0
+ assign $4\core_fasto2_ok$next[0:0]$2110 1'0
+ assign $4\core_cr_in1_ok$next[0:0]$2102 1'0
+ assign $4\core_cr_in2_ok$next[0:0]$2104 1'0
+ assign $4\core_cr_in2_ok$49$next[0:0]$2103 1'0
+ assign $4\core_cr_out_ok$next[0:0]$2105 1'0
+ assign $4\core_core_rc_ok$next[0:0]$2101 1'0
+ assign $4\core_core_oe_ok$next[0:0]$2100 1'0
+ assign $4\core_core_exc_$signal$next[0:0]$2099 1'0
+ assign $4\core_core_exc_$signal$50$next[0:0]$2092 1'0
+ assign $4\core_core_exc_$signal$51$next[0:0]$2093 1'0
+ assign $4\core_core_exc_$signal$52$next[0:0]$2094 1'0
+ assign $4\core_core_exc_$signal$53$next[0:0]$2095 1'0
+ assign $4\core_core_exc_$signal$54$next[0:0]$2096 1'0
+ assign $4\core_core_exc_$signal$55$next[0:0]$2097 1'0
+ assign $4\core_core_exc_$signal$56$next[0:0]$2098 1'0
+ assign $4\core_core_cr_rd_ok$next[0:0]$2090 1'0
+ assign $4\core_core_cr_wr_ok$next[0:0]$2091 1'0
case
- assign $4\core_core_cr_rd_ok$next[0:0]$2089 $1\core_core_cr_rd_ok$next[0:0]$1915
- assign $4\core_core_cr_wr_ok$next[0:0]$2090 $1\core_core_cr_wr_ok$next[0:0]$1917
- assign $4\core_core_exc_$signal$50$next[0:0]$2091 $1\core_core_exc_$signal$50$next[0:0]$1918
- assign $4\core_core_exc_$signal$51$next[0:0]$2092 $1\core_core_exc_$signal$51$next[0:0]$1919
- assign $4\core_core_exc_$signal$52$next[0:0]$2093 $1\core_core_exc_$signal$52$next[0:0]$1920
- assign $4\core_core_exc_$signal$53$next[0:0]$2094 $1\core_core_exc_$signal$53$next[0:0]$1921
- assign $4\core_core_exc_$signal$54$next[0:0]$2095 $1\core_core_exc_$signal$54$next[0:0]$1922
- assign $4\core_core_exc_$signal$55$next[0:0]$2096 $1\core_core_exc_$signal$55$next[0:0]$1923
- assign $4\core_core_exc_$signal$56$next[0:0]$2097 $1\core_core_exc_$signal$56$next[0:0]$1924
- assign $4\core_core_exc_$signal$next[0:0]$2098 $1\core_core_exc_$signal$next[0:0]$1925
- assign $4\core_core_oe_ok$next[0:0]$2099 $1\core_core_oe_ok$next[0:0]$1934
- assign $4\core_core_rc_ok$next[0:0]$2100 $1\core_core_rc_ok$next[0:0]$1936
- assign $4\core_cr_in1_ok$next[0:0]$2101 $1\core_cr_in1_ok$next[0:0]$1940
- assign $4\core_cr_in2_ok$49$next[0:0]$2102 $1\core_cr_in2_ok$49$next[0:0]$1943
- assign $4\core_cr_in2_ok$next[0:0]$2103 $1\core_cr_in2_ok$next[0:0]$1944
- assign $4\core_cr_out_ok$next[0:0]$2104 $1\core_cr_out_ok$next[0:0]$1946
- assign $4\core_ea_ok$next[0:0]$2105 $1\core_ea_ok$next[0:0]$1948
- assign $4\core_fast1_ok$next[0:0]$2106 $1\core_fast1_ok$next[0:0]$1950
- assign $4\core_fast2_ok$next[0:0]$2107 $1\core_fast2_ok$next[0:0]$1952
- assign $4\core_fasto1_ok$next[0:0]$2108 $1\core_fasto1_ok$next[0:0]$1954
- assign $4\core_fasto2_ok$next[0:0]$2109 $1\core_fasto2_ok$next[0:0]$1956
- assign $4\core_reg1_ok$next[0:0]$2110 $1\core_reg1_ok$next[0:0]$1958
- assign $4\core_reg2_ok$next[0:0]$2111 $1\core_reg2_ok$next[0:0]$1960
- assign $4\core_reg3_ok$next[0:0]$2112 $1\core_reg3_ok$next[0:0]$1962
- assign $4\core_rego_ok$next[0:0]$2113 $1\core_rego_ok$next[0:0]$1964
- assign $4\core_spr1_ok$next[0:0]$2114 $1\core_spr1_ok$next[0:0]$1966
- assign $4\core_spro_ok$next[0:0]$2115 $1\core_spro_ok$next[0:0]$1968
+ assign $4\core_core_cr_rd_ok$next[0:0]$2090 $1\core_core_cr_rd_ok$next[0:0]$1916
+ assign $4\core_core_cr_wr_ok$next[0:0]$2091 $1\core_core_cr_wr_ok$next[0:0]$1918
+ assign $4\core_core_exc_$signal$50$next[0:0]$2092 $1\core_core_exc_$signal$50$next[0:0]$1919
+ assign $4\core_core_exc_$signal$51$next[0:0]$2093 $1\core_core_exc_$signal$51$next[0:0]$1920
+ assign $4\core_core_exc_$signal$52$next[0:0]$2094 $1\core_core_exc_$signal$52$next[0:0]$1921
+ assign $4\core_core_exc_$signal$53$next[0:0]$2095 $1\core_core_exc_$signal$53$next[0:0]$1922
+ assign $4\core_core_exc_$signal$54$next[0:0]$2096 $1\core_core_exc_$signal$54$next[0:0]$1923
+ assign $4\core_core_exc_$signal$55$next[0:0]$2097 $1\core_core_exc_$signal$55$next[0:0]$1924
+ assign $4\core_core_exc_$signal$56$next[0:0]$2098 $1\core_core_exc_$signal$56$next[0:0]$1925
+ assign $4\core_core_exc_$signal$next[0:0]$2099 $1\core_core_exc_$signal$next[0:0]$1926
+ assign $4\core_core_oe_ok$next[0:0]$2100 $1\core_core_oe_ok$next[0:0]$1935
+ assign $4\core_core_rc_ok$next[0:0]$2101 $1\core_core_rc_ok$next[0:0]$1937
+ assign $4\core_cr_in1_ok$next[0:0]$2102 $1\core_cr_in1_ok$next[0:0]$1941
+ assign $4\core_cr_in2_ok$49$next[0:0]$2103 $1\core_cr_in2_ok$49$next[0:0]$1944
+ assign $4\core_cr_in2_ok$next[0:0]$2104 $1\core_cr_in2_ok$next[0:0]$1945
+ assign $4\core_cr_out_ok$next[0:0]$2105 $1\core_cr_out_ok$next[0:0]$1947
+ assign $4\core_ea_ok$next[0:0]$2106 $1\core_ea_ok$next[0:0]$1949
+ assign $4\core_fast1_ok$next[0:0]$2107 $1\core_fast1_ok$next[0:0]$1951
+ assign $4\core_fast2_ok$next[0:0]$2108 $1\core_fast2_ok$next[0:0]$1953
+ assign $4\core_fasto1_ok$next[0:0]$2109 $1\core_fasto1_ok$next[0:0]$1955
+ assign $4\core_fasto2_ok$next[0:0]$2110 $1\core_fasto2_ok$next[0:0]$1957
+ assign $4\core_reg1_ok$next[0:0]$2111 $1\core_reg1_ok$next[0:0]$1959
+ assign $4\core_reg2_ok$next[0:0]$2112 $1\core_reg2_ok$next[0:0]$1961
+ assign $4\core_reg3_ok$next[0:0]$2113 $1\core_reg3_ok$next[0:0]$1963
+ assign $4\core_rego_ok$next[0:0]$2114 $1\core_rego_ok$next[0:0]$1965
+ assign $4\core_spr1_ok$next[0:0]$2115 $1\core_spr1_ok$next[0:0]$1967
+ assign $4\core_spro_ok$next[0:0]$2116 $1\core_spro_ok$next[0:0]$1969
end
sync always
- update \core_asmcode$next $0\core_asmcode$next[7:0]$1853
- update \core_core_cia$next $0\core_core_cia$next[63:0]$1854
- update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1855
- update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1856
- update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1857
- update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1858
- update \core_core_exc_$signal$50$next $0\core_core_exc_$signal$50$next[0:0]$1859
- update \core_core_exc_$signal$51$next $0\core_core_exc_$signal$51$next[0:0]$1860
- update \core_core_exc_$signal$52$next $0\core_core_exc_$signal$52$next[0:0]$1861
- update \core_core_exc_$signal$53$next $0\core_core_exc_$signal$53$next[0:0]$1862
- update \core_core_exc_$signal$54$next $0\core_core_exc_$signal$54$next[0:0]$1863
- update \core_core_exc_$signal$55$next $0\core_core_exc_$signal$55$next[0:0]$1864
- update \core_core_exc_$signal$56$next $0\core_core_exc_$signal$56$next[0:0]$1865
- update \core_core_exc_$signal$next $0\core_core_exc_$signal$next[0:0]$1866
- update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1867
- update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1868
- update \core_core_insn$next $0\core_core_insn$next[31:0]$1869
- update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1870
- update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1871
- update \core_core_lk$next $0\core_core_lk$next[0:0]$1872
- update \core_core_msr$next $0\core_core_msr$next[63:0]$1873
- update \core_core_oe$next $0\core_core_oe$next[0:0]$1874
- update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1875
- update \core_core_rc$next $0\core_core_rc$next[0:0]$1876
- update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1877
- update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1878
- update \core_core_traptype$next $0\core_core_traptype$next[7:0]$1879
- update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1880
- update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1881
- update \core_cr_in2$48$next $0\core_cr_in2$48$next[2:0]$1882
- update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1883
- update \core_cr_in2_ok$49$next $0\core_cr_in2_ok$49$next[0:0]$1884
- update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1885
- update \core_cr_out$next $0\core_cr_out$next[2:0]$1886
- update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1887
- update \core_ea$next $0\core_ea$next[4:0]$1888
- update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1889
- update \core_fast1$next $0\core_fast1$next[2:0]$1890
- update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1891
- update \core_fast2$next $0\core_fast2$next[2:0]$1892
- update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1893
- update \core_fasto1$next $0\core_fasto1$next[2:0]$1894
- update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1895
- update \core_fasto2$next $0\core_fasto2$next[2:0]$1896
- update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1897
- update \core_reg1$next $0\core_reg1$next[4:0]$1898
- update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1899
- update \core_reg2$next $0\core_reg2$next[4:0]$1900
- update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1901
- update \core_reg3$next $0\core_reg3$next[4:0]$1902
- update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1903
- update \core_rego$next $0\core_rego$next[4:0]$1904
- update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1905
- update \core_spr1$next $0\core_spr1$next[9:0]$1906
- update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1907
- update \core_spro$next $0\core_spro$next[9:0]$1908
- update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1909
- update \core_xer_in$next $0\core_xer_in$next[2:0]$1910
- update \core_xer_out$next $0\core_xer_out$next[0:0]$1911
- end
- attribute \src "libresoc.v:52173.3-52181.6"
- process $proc$libresoc.v:52173$2116
- assign { } { }
- assign { } { }
- assign $0\jtag_dmi0__ack_o$next[0:0]$2117 $1\jtag_dmi0__ack_o$next[0:0]$2118
- attribute \src "libresoc.v:52174.5-52174.29"
- switch \initial
- attribute \src "libresoc.v:52174.9-52174.17"
+ update \core_asmcode$next $0\core_asmcode$next[7:0]$1854
+ update \core_core_cia$next $0\core_core_cia$next[63:0]$1855
+ update \core_core_cr_rd$next $0\core_core_cr_rd$next[7:0]$1856
+ update \core_core_cr_rd_ok$next $0\core_core_cr_rd_ok$next[0:0]$1857
+ update \core_core_cr_wr$next $0\core_core_cr_wr$next[7:0]$1858
+ update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$1859
+ update \core_core_exc_$signal$50$next $0\core_core_exc_$signal$50$next[0:0]$1860
+ update \core_core_exc_$signal$51$next $0\core_core_exc_$signal$51$next[0:0]$1861
+ update \core_core_exc_$signal$52$next $0\core_core_exc_$signal$52$next[0:0]$1862
+ update \core_core_exc_$signal$53$next $0\core_core_exc_$signal$53$next[0:0]$1863
+ update \core_core_exc_$signal$54$next $0\core_core_exc_$signal$54$next[0:0]$1864
+ update \core_core_exc_$signal$55$next $0\core_core_exc_$signal$55$next[0:0]$1865
+ update \core_core_exc_$signal$56$next $0\core_core_exc_$signal$56$next[0:0]$1866
+ update \core_core_exc_$signal$next $0\core_core_exc_$signal$next[0:0]$1867
+ update \core_core_fn_unit$next $0\core_core_fn_unit$next[11:0]$1868
+ update \core_core_input_carry$next $0\core_core_input_carry$next[1:0]$1869
+ update \core_core_insn$next $0\core_core_insn$next[31:0]$1870
+ update \core_core_insn_type$next $0\core_core_insn_type$next[6:0]$1871
+ update \core_core_is_32bit$next $0\core_core_is_32bit$next[0:0]$1872
+ update \core_core_lk$next $0\core_core_lk$next[0:0]$1873
+ update \core_core_msr$next $0\core_core_msr$next[63:0]$1874
+ update \core_core_oe$next $0\core_core_oe$next[0:0]$1875
+ update \core_core_oe_ok$next $0\core_core_oe_ok$next[0:0]$1876
+ update \core_core_rc$next $0\core_core_rc$next[0:0]$1877
+ update \core_core_rc_ok$next $0\core_core_rc_ok$next[0:0]$1878
+ update \core_core_trapaddr$next $0\core_core_trapaddr$next[12:0]$1879
+ update \core_core_traptype$next $0\core_core_traptype$next[7:0]$1880
+ update \core_cr_in1$next $0\core_cr_in1$next[2:0]$1881
+ update \core_cr_in1_ok$next $0\core_cr_in1_ok$next[0:0]$1882
+ update \core_cr_in2$48$next $0\core_cr_in2$48$next[2:0]$1883
+ update \core_cr_in2$next $0\core_cr_in2$next[2:0]$1884
+ update \core_cr_in2_ok$49$next $0\core_cr_in2_ok$49$next[0:0]$1885
+ update \core_cr_in2_ok$next $0\core_cr_in2_ok$next[0:0]$1886
+ update \core_cr_out$next $0\core_cr_out$next[2:0]$1887
+ update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$1888
+ update \core_ea$next $0\core_ea$next[4:0]$1889
+ update \core_ea_ok$next $0\core_ea_ok$next[0:0]$1890
+ update \core_fast1$next $0\core_fast1$next[2:0]$1891
+ update \core_fast1_ok$next $0\core_fast1_ok$next[0:0]$1892
+ update \core_fast2$next $0\core_fast2$next[2:0]$1893
+ update \core_fast2_ok$next $0\core_fast2_ok$next[0:0]$1894
+ update \core_fasto1$next $0\core_fasto1$next[2:0]$1895
+ update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$1896
+ update \core_fasto2$next $0\core_fasto2$next[2:0]$1897
+ update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$1898
+ update \core_reg1$next $0\core_reg1$next[4:0]$1899
+ update \core_reg1_ok$next $0\core_reg1_ok$next[0:0]$1900
+ update \core_reg2$next $0\core_reg2$next[4:0]$1901
+ update \core_reg2_ok$next $0\core_reg2_ok$next[0:0]$1902
+ update \core_reg3$next $0\core_reg3$next[4:0]$1903
+ update \core_reg3_ok$next $0\core_reg3_ok$next[0:0]$1904
+ update \core_rego$next $0\core_rego$next[4:0]$1905
+ update \core_rego_ok$next $0\core_rego_ok$next[0:0]$1906
+ update \core_spr1$next $0\core_spr1$next[9:0]$1907
+ update \core_spr1_ok$next $0\core_spr1_ok$next[0:0]$1908
+ update \core_spro$next $0\core_spro$next[9:0]$1909
+ update \core_spro_ok$next $0\core_spro_ok$next[0:0]$1910
+ update \core_xer_in$next $0\core_xer_in$next[2:0]$1911
+ update \core_xer_out$next $0\core_xer_out$next[0:0]$1912
+ end
+ attribute \src "libresoc.v:52176.3-52184.6"
+ process $proc$libresoc.v:52176$2117
+ assign { } { }
+ assign { } { }
+ assign $0\jtag_dmi0__ack_o$next[0:0]$2118 $1\jtag_dmi0__ack_o$next[0:0]$2119
+ attribute \src "libresoc.v:52177.5-52177.29"
+ switch \initial
+ attribute \src "libresoc.v:52177.9-52177.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_dmi0__ack_o$next[0:0]$2118 1'0
+ assign $1\jtag_dmi0__ack_o$next[0:0]$2119 1'0
case
- assign $1\jtag_dmi0__ack_o$next[0:0]$2118 \dbg_dmi_ack_o
+ assign $1\jtag_dmi0__ack_o$next[0:0]$2119 \dbg_dmi_ack_o
end
sync always
- update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$2117
+ update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$2118
end
- attribute \src "libresoc.v:52182.3-52190.6"
- process $proc$libresoc.v:52182$2119
+ attribute \src "libresoc.v:52185.3-52193.6"
+ process $proc$libresoc.v:52185$2120
assign { } { }
assign { } { }
- assign $0\jtag_dmi0__dout$next[63:0]$2120 $1\jtag_dmi0__dout$next[63:0]$2121
- attribute \src "libresoc.v:52183.5-52183.29"
+ assign $0\jtag_dmi0__dout$next[63:0]$2121 $1\jtag_dmi0__dout$next[63:0]$2122
+ attribute \src "libresoc.v:52186.5-52186.29"
switch \initial
- attribute \src "libresoc.v:52183.9-52183.17"
+ attribute \src "libresoc.v:52186.9-52186.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\jtag_dmi0__dout$next[63:0]$2121 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $1\jtag_dmi0__dout$next[63:0]$2122 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $1\jtag_dmi0__dout$next[63:0]$2121 \dbg_dmi_dout
+ assign $1\jtag_dmi0__dout$next[63:0]$2122 \dbg_dmi_dout
end
sync always
- update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$2120
+ update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$2121
end
- attribute \src "libresoc.v:52191.3-52199.6"
- process $proc$libresoc.v:52191$2122
+ attribute \src "libresoc.v:52194.3-52202.6"
+ process $proc$libresoc.v:52194$2123
assign { } { }
assign { } { }
- assign $0\dec2_cur_eint$next[0:0]$2123 $1\dec2_cur_eint$next[0:0]$2124
- attribute \src "libresoc.v:52192.5-52192.29"
+ assign $0\dec2_cur_eint$next[0:0]$2124 $1\dec2_cur_eint$next[0:0]$2125
+ attribute \src "libresoc.v:52195.5-52195.29"
switch \initial
- attribute \src "libresoc.v:52192.9-52192.17"
+ attribute \src "libresoc.v:52195.9-52195.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\dec2_cur_eint$next[0:0]$2124 1'0
+ assign $1\dec2_cur_eint$next[0:0]$2125 1'0
case
- assign $1\dec2_cur_eint$next[0:0]$2124 \xics_icp_core_irq_o
+ assign $1\dec2_cur_eint$next[0:0]$2125 \xics_icp_core_irq_o
end
sync always
- update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$2123
+ update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$2124
end
- attribute \src "libresoc.v:52200.3-52209.6"
- process $proc$libresoc.v:52200$2125
+ attribute \src "libresoc.v:52203.3-52212.6"
+ process $proc$libresoc.v:52203$2126
assign { } { }
assign { } { }
- assign $0\delay$next[1:0]$2126 $1\delay$next[1:0]$2127
- attribute \src "libresoc.v:52201.5-52201.29"
+ assign $0\delay$next[1:0]$2127 $1\delay$next[1:0]$2128
+ attribute \src "libresoc.v:52204.5-52204.29"
switch \initial
- attribute \src "libresoc.v:52201.9-52201.17"
+ attribute \src "libresoc.v:52204.9-52204.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\delay$next[1:0]$2127 \$12 [1:0]
+ assign $1\delay$next[1:0]$2128 \$12 [1:0]
case
- assign $1\delay$next[1:0]$2127 \delay
+ assign $1\delay$next[1:0]$2128 \delay
end
sync always
- update \delay$next $0\delay$next[1:0]$2126
+ update \delay$next $0\delay$next[1:0]$2127
end
- attribute \src "libresoc.v:52210.3-52246.6"
- process $proc$libresoc.v:52210$2128
+ attribute \src "libresoc.v:52213.3-52249.6"
+ process $proc$libresoc.v:52213$2129
assign { } { }
assign { } { }
assign { } { }
- assign $0\raw_insn_i$next[31:0]$2129 $4\raw_insn_i$next[31:0]$2133
- attribute \src "libresoc.v:52211.5-52211.29"
+ assign $0\raw_insn_i$next[31:0]$2130 $4\raw_insn_i$next[31:0]$2134
+ attribute \src "libresoc.v:52214.5-52214.29"
switch \initial
- attribute \src "libresoc.v:52211.9-52211.17"
+ attribute \src "libresoc.v:52214.9-52214.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\raw_insn_i$next[31:0]$2130 0
+ assign $1\raw_insn_i$next[31:0]$2131 0
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\raw_insn_i$next[31:0]$2130 $2\raw_insn_i$next[31:0]$2131
+ assign $1\raw_insn_i$next[31:0]$2131 $2\raw_insn_i$next[31:0]$2132
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\raw_insn_i$next[31:0]$2131 \raw_insn_i
+ assign $2\raw_insn_i$next[31:0]$2132 \raw_insn_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\raw_insn_i$next[31:0]$2131 \dec2_raw_opcode_in
+ assign $2\raw_insn_i$next[31:0]$2132 \dec2_raw_opcode_in
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\raw_insn_i$next[31:0]$2130 $3\raw_insn_i$next[31:0]$2132
+ assign $1\raw_insn_i$next[31:0]$2131 $3\raw_insn_i$next[31:0]$2133
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
switch \$59
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\raw_insn_i$next[31:0]$2132 0
+ assign $3\raw_insn_i$next[31:0]$2133 0
case
- assign $3\raw_insn_i$next[31:0]$2132 \raw_insn_i
+ assign $3\raw_insn_i$next[31:0]$2133 \raw_insn_i
end
case
- assign $1\raw_insn_i$next[31:0]$2130 \raw_insn_i
+ assign $1\raw_insn_i$next[31:0]$2131 \raw_insn_i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\raw_insn_i$next[31:0]$2133 0
+ assign $4\raw_insn_i$next[31:0]$2134 0
case
- assign $4\raw_insn_i$next[31:0]$2133 $1\raw_insn_i$next[31:0]$2130
+ assign $4\raw_insn_i$next[31:0]$2134 $1\raw_insn_i$next[31:0]$2131
end
sync always
- update \raw_insn_i$next $0\raw_insn_i$next[31:0]$2129
+ update \raw_insn_i$next $0\raw_insn_i$next[31:0]$2130
end
- attribute \src "libresoc.v:52247.3-52283.6"
- process $proc$libresoc.v:52247$2134
+ attribute \src "libresoc.v:52250.3-52286.6"
+ process $proc$libresoc.v:52250$2135
assign { } { }
assign { } { }
assign { } { }
- assign $0\bigendian_i$next[0:0]$2135 $4\bigendian_i$next[0:0]$2139
- attribute \src "libresoc.v:52248.5-52248.29"
+ assign $0\bigendian_i$next[0:0]$2136 $4\bigendian_i$next[0:0]$2140
+ attribute \src "libresoc.v:52251.5-52251.29"
switch \initial
- attribute \src "libresoc.v:52248.9-52248.17"
+ attribute \src "libresoc.v:52251.9-52251.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\bigendian_i$next[0:0]$2136 1'0
+ assign $1\bigendian_i$next[0:0]$2137 1'0
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\bigendian_i$next[0:0]$2136 $2\bigendian_i$next[0:0]$2137
+ assign $1\bigendian_i$next[0:0]$2137 $2\bigendian_i$next[0:0]$2138
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $2\bigendian_i$next[0:0]$2137 \bigendian_i
+ assign $2\bigendian_i$next[0:0]$2138 \bigendian_i
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $2\bigendian_i$next[0:0]$2137 \core_bigendian_i
+ assign $2\bigendian_i$next[0:0]$2138 \core_bigendian_i
end
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\bigendian_i$next[0:0]$2136 $3\bigendian_i$next[0:0]$2138
+ assign $1\bigendian_i$next[0:0]$2137 $3\bigendian_i$next[0:0]$2139
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
switch \$61
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\bigendian_i$next[0:0]$2138 1'0
+ assign $3\bigendian_i$next[0:0]$2139 1'0
case
- assign $3\bigendian_i$next[0:0]$2138 \bigendian_i
+ assign $3\bigendian_i$next[0:0]$2139 \bigendian_i
end
case
- assign $1\bigendian_i$next[0:0]$2136 \bigendian_i
+ assign $1\bigendian_i$next[0:0]$2137 \bigendian_i
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\bigendian_i$next[0:0]$2139 1'0
+ assign $4\bigendian_i$next[0:0]$2140 1'0
case
- assign $4\bigendian_i$next[0:0]$2139 $1\bigendian_i$next[0:0]$2136
+ assign $4\bigendian_i$next[0:0]$2140 $1\bigendian_i$next[0:0]$2137
end
sync always
- update \bigendian_i$next $0\bigendian_i$next[0:0]$2135
+ update \bigendian_i$next $0\bigendian_i$next[0:0]$2136
end
- attribute \src "libresoc.v:52284.3-52299.6"
- process $proc$libresoc.v:52284$2140
+ attribute \src "libresoc.v:52287.3-52302.6"
+ process $proc$libresoc.v:52287$2141
assign { } { }
assign { } { }
assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0]
- attribute \src "libresoc.v:52285.5-52285.29"
+ attribute \src "libresoc.v:52288.5-52288.29"
switch \initial
- attribute \src "libresoc.v:52285.9-52285.17"
+ attribute \src "libresoc.v:52288.9-52288.17"
case 1'1
case
end
sync always
update \imem_a_pc_i $0\imem_a_pc_i[47:0]
end
- attribute \src "libresoc.v:52300.3-52324.6"
- process $proc$libresoc.v:52300$2141
+ attribute \src "libresoc.v:52303.3-52327.6"
+ process $proc$libresoc.v:52303$2142
assign { } { }
assign { } { }
assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0]
- attribute \src "libresoc.v:52301.5-52301.29"
+ attribute \src "libresoc.v:52304.5-52304.29"
switch \initial
- attribute \src "libresoc.v:52301.9-52301.17"
+ attribute \src "libresoc.v:52304.9-52304.17"
case 1'1
case
end
sync always
update \imem_a_valid_i $0\imem_a_valid_i[0:0]
end
- attribute \src "libresoc.v:52325.3-52349.6"
- process $proc$libresoc.v:52325$2142
+ attribute \src "libresoc.v:52328.3-52352.6"
+ process $proc$libresoc.v:52328$2143
assign { } { }
assign { } { }
assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0]
- attribute \src "libresoc.v:52326.5-52326.29"
+ attribute \src "libresoc.v:52329.5-52329.29"
switch \initial
- attribute \src "libresoc.v:52326.9-52326.17"
+ attribute \src "libresoc.v:52329.9-52329.17"
case 1'1
case
end
sync always
update \imem_f_valid_i $0\imem_f_valid_i[0:0]
end
- attribute \src "libresoc.v:52350.3-52370.6"
- process $proc$libresoc.v:52350$2143
+ attribute \src "libresoc.v:52353.3-52373.6"
+ process $proc$libresoc.v:52353$2144
assign { } { }
assign { } { }
assign { } { }
- assign $0\dec2_cur_pc$next[63:0]$2144 $3\dec2_cur_pc$next[63:0]$2147
- attribute \src "libresoc.v:52351.5-52351.29"
+ assign $0\dec2_cur_pc$next[63:0]$2145 $3\dec2_cur_pc$next[63:0]$2148
+ attribute \src "libresoc.v:52354.5-52354.29"
switch \initial
- attribute \src "libresoc.v:52351.9-52351.17"
+ attribute \src "libresoc.v:52354.9-52354.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\dec2_cur_pc$next[63:0]$2145 $2\dec2_cur_pc$next[63:0]$2146
+ assign $1\dec2_cur_pc$next[63:0]$2146 $2\dec2_cur_pc$next[63:0]$2147
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
switch \$85
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\dec2_cur_pc$next[63:0]$2146 \pc
+ assign $2\dec2_cur_pc$next[63:0]$2147 \pc
case
- assign $2\dec2_cur_pc$next[63:0]$2146 \dec2_cur_pc
+ assign $2\dec2_cur_pc$next[63:0]$2147 \dec2_cur_pc
end
case
- assign $1\dec2_cur_pc$next[63:0]$2145 \dec2_cur_pc
+ assign $1\dec2_cur_pc$next[63:0]$2146 \dec2_cur_pc
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\dec2_cur_pc$next[63:0]$2147 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign $3\dec2_cur_pc$next[63:0]$2148 64'0000000000000000000000000000000000000000000000000000000000000000
case
- assign $3\dec2_cur_pc$next[63:0]$2147 $1\dec2_cur_pc$next[63:0]$2145
+ assign $3\dec2_cur_pc$next[63:0]$2148 $1\dec2_cur_pc$next[63:0]$2146
end
sync always
- update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$2144
+ update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$2145
end
- attribute \src "libresoc.v:52371.3-52400.6"
- process $proc$libresoc.v:52371$2148
+ attribute \src "libresoc.v:52374.3-52403.6"
+ process $proc$libresoc.v:52374$2149
assign { } { }
assign { } { }
assign { } { }
- assign $0\msr_read$next[0:0]$2149 $4\msr_read$next[0:0]$2153
- attribute \src "libresoc.v:52372.5-52372.29"
+ assign $0\msr_read$next[0:0]$2150 $4\msr_read$next[0:0]$2154
+ attribute \src "libresoc.v:52375.5-52375.29"
switch \initial
- attribute \src "libresoc.v:52372.9-52372.17"
+ attribute \src "libresoc.v:52375.9-52375.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\msr_read$next[0:0]$2150 $2\msr_read$next[0:0]$2151
+ assign $1\msr_read$next[0:0]$2151 $2\msr_read$next[0:0]$2152
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
switch \$91
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\msr_read$next[0:0]$2151 1'0
+ assign $2\msr_read$next[0:0]$2152 1'0
case
- assign $2\msr_read$next[0:0]$2151 \msr_read
+ assign $2\msr_read$next[0:0]$2152 \msr_read
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\msr_read$next[0:0]$2150 $3\msr_read$next[0:0]$2152
+ assign $1\msr_read$next[0:0]$2151 $3\msr_read$next[0:0]$2153
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275"
switch \$93
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $3\msr_read$next[0:0]$2152 1'1
+ assign $3\msr_read$next[0:0]$2153 1'1
case
- assign $3\msr_read$next[0:0]$2152 \msr_read
+ assign $3\msr_read$next[0:0]$2153 \msr_read
end
case
- assign $1\msr_read$next[0:0]$2150 \msr_read
+ assign $1\msr_read$next[0:0]$2151 \msr_read
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\msr_read$next[0:0]$2153 1'1
+ assign $4\msr_read$next[0:0]$2154 1'1
case
- assign $4\msr_read$next[0:0]$2153 $1\msr_read$next[0:0]$2150
+ assign $4\msr_read$next[0:0]$2154 $1\msr_read$next[0:0]$2151
end
sync always
- update \msr_read$next $0\msr_read$next[0:0]$2149
+ update \msr_read$next $0\msr_read$next[0:0]$2150
end
- attribute \src "libresoc.v:52401.3-52446.6"
- process $proc$libresoc.v:52401$2154
+ attribute \src "libresoc.v:52404.3-52449.6"
+ process $proc$libresoc.v:52404$2155
assign { } { }
assign { } { }
assign { } { }
- assign $0\fsm_state$next[1:0]$2155 $5\fsm_state$next[1:0]$2160
- attribute \src "libresoc.v:52402.5-52402.29"
+ assign $0\fsm_state$next[1:0]$2156 $5\fsm_state$next[1:0]$2161
+ attribute \src "libresoc.v:52405.5-52405.29"
switch \initial
- attribute \src "libresoc.v:52402.9-52402.17"
+ attribute \src "libresoc.v:52405.9-52405.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 2'00
assign { } { }
- assign $1\fsm_state$next[1:0]$2156 $2\fsm_state$next[1:0]$2157
+ assign $1\fsm_state$next[1:0]$2157 $2\fsm_state$next[1:0]$2158
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253"
switch \$99
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\fsm_state$next[1:0]$2157 2'01
+ assign $2\fsm_state$next[1:0]$2158 2'01
case
- assign $2\fsm_state$next[1:0]$2157 \fsm_state
+ assign $2\fsm_state$next[1:0]$2158 \fsm_state
end
attribute \src "libresoc.v:0.0-0.0"
case 2'01
assign { } { }
- assign $1\fsm_state$next[1:0]$2156 $3\fsm_state$next[1:0]$2158
+ assign $1\fsm_state$next[1:0]$2157 $3\fsm_state$next[1:0]$2159
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278"
switch \imem_f_busy_o
attribute \src "libresoc.v:0.0-0.0"
case 1'1
- assign $3\fsm_state$next[1:0]$2158 \fsm_state
+ assign $3\fsm_state$next[1:0]$2159 \fsm_state
attribute \src "libresoc.v:0.0-0.0"
case
assign { } { }
- assign $3\fsm_state$next[1:0]$2158 2'10
+ assign $3\fsm_state$next[1:0]$2159 2'10
end
attribute \src "libresoc.v:0.0-0.0"
case 2'10
assign { } { }
- assign $1\fsm_state$next[1:0]$2156 2'11
+ assign $1\fsm_state$next[1:0]$2157 2'11
attribute \src "libresoc.v:0.0-0.0"
case 2'11
assign { } { }
- assign $1\fsm_state$next[1:0]$2156 $4\fsm_state$next[1:0]$2159
+ assign $1\fsm_state$next[1:0]$2157 $4\fsm_state$next[1:0]$2160
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:311"
switch \$101
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\fsm_state$next[1:0]$2159 2'00
+ assign $4\fsm_state$next[1:0]$2160 2'00
case
- assign $4\fsm_state$next[1:0]$2159 \fsm_state
+ assign $4\fsm_state$next[1:0]$2160 \fsm_state
end
case
- assign $1\fsm_state$next[1:0]$2156 \fsm_state
+ assign $1\fsm_state$next[1:0]$2157 \fsm_state
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $5\fsm_state$next[1:0]$2160 2'00
+ assign $5\fsm_state$next[1:0]$2161 2'00
case
- assign $5\fsm_state$next[1:0]$2160 $1\fsm_state$next[1:0]$2156
+ assign $5\fsm_state$next[1:0]$2161 $1\fsm_state$next[1:0]$2157
end
sync always
- update \fsm_state$next $0\fsm_state$next[1:0]$2155
+ update \fsm_state$next $0\fsm_state$next[1:0]$2156
end
- attribute \src "libresoc.v:52447.3-52465.6"
- process $proc$libresoc.v:52447$2161
+ attribute \src "libresoc.v:52450.3-52468.6"
+ process $proc$libresoc.v:52450$2162
assign { } { }
assign { } { }
assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0]
- attribute \src "libresoc.v:52448.5-52448.29"
+ attribute \src "libresoc.v:52451.5-52451.29"
switch \initial
- attribute \src "libresoc.v:52448.9-52448.17"
+ attribute \src "libresoc.v:52451.9-52451.17"
case 1'1
case
end
sync always
update \core_stopped_i $0\core_stopped_i[0:0]
end
- attribute \src "libresoc.v:52466.3-52484.6"
- process $proc$libresoc.v:52466$2162
+ attribute \src "libresoc.v:52469.3-52487.6"
+ process $proc$libresoc.v:52469$2163
assign { } { }
assign { } { }
assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0]
- attribute \src "libresoc.v:52467.5-52467.29"
+ attribute \src "libresoc.v:52470.5-52470.29"
switch \initial
- attribute \src "libresoc.v:52467.9-52467.17"
+ attribute \src "libresoc.v:52470.9-52470.17"
case 1'1
case
end
sync always
update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0]
end
- connect \$99 $and$libresoc.v:50795$1605_Y
- connect \$101 $not$libresoc.v:50796$1606_Y
- connect \$103 $not$libresoc.v:50797$1607_Y
- connect \$105 $not$libresoc.v:50798$1608_Y
- connect \$107 $and$libresoc.v:50799$1609_Y
- connect \$10 $ne$libresoc.v:50800$1610_Y
- connect \$109 $not$libresoc.v:50801$1611_Y
- connect \$111 $not$libresoc.v:50802$1612_Y
- connect \$113 $and$libresoc.v:50803$1613_Y
- connect \$115 $not$libresoc.v:50804$1614_Y
- connect \$118 $mul$libresoc.v:50805$1615_Y
- connect \$117 $shr$libresoc.v:50806$1616_Y [31:0]
- connect \$122 $mul$libresoc.v:50807$1617_Y
- connect \$121 $shr$libresoc.v:50808$1618_Y [31:0]
- connect \$125 $ne$libresoc.v:50809$1619_Y
- connect \$127 $pos$libresoc.v:50810$1621_Y
- connect \$129 $pos$libresoc.v:50811$1623_Y
- connect \$133 $sub$libresoc.v:50812$1624_Y
- connect \$137 $add$libresoc.v:50813$1625_Y
- connect \$13 $sub$libresoc.v:50814$1626_Y
- connect \$15 $or$libresoc.v:50815$1627_Y
- connect \$17 $or$libresoc.v:50816$1628_Y
- connect \$19 $ne$libresoc.v:50817$1629_Y
- connect \$21 $not$libresoc.v:50818$1630_Y
- connect \$23 $and$libresoc.v:50819$1631_Y
- connect \$26 $add$libresoc.v:50820$1632_Y
- connect \$28 $not$libresoc.v:50821$1633_Y
- connect \$30 $not$libresoc.v:50822$1634_Y
- connect \$32 $not$libresoc.v:50823$1635_Y
- connect \$34 $not$libresoc.v:50824$1636_Y
- connect \$36 $not$libresoc.v:50825$1637_Y
- connect \$38 $not$libresoc.v:50826$1638_Y
- connect \$40 $not$libresoc.v:50827$1639_Y
- connect \$42 $and$libresoc.v:50828$1640_Y
- connect \$45 $and$libresoc.v:50829$1641_Y
- connect \$44 $reduce_or$libresoc.v:50830$1642_Y
- connect \$57 $not$libresoc.v:50831$1643_Y
- connect \$59 $not$libresoc.v:50832$1644_Y
- connect \$61 $not$libresoc.v:50833$1645_Y
- connect \$63 $not$libresoc.v:50834$1646_Y
- connect \$65 $not$libresoc.v:50835$1647_Y
- connect \$67 $and$libresoc.v:50836$1648_Y
- connect \$69 $not$libresoc.v:50837$1649_Y
- connect \$71 $not$libresoc.v:50838$1650_Y
- connect \$73 $and$libresoc.v:50839$1651_Y
- connect \$75 $not$libresoc.v:50840$1652_Y
- connect \$77 $not$libresoc.v:50841$1653_Y
- connect \$79 $and$libresoc.v:50842$1654_Y
- connect \$81 $not$libresoc.v:50843$1655_Y
- connect \$83 $not$libresoc.v:50844$1656_Y
- connect \$85 $and$libresoc.v:50845$1657_Y
- connect \$87 $not$libresoc.v:50846$1658_Y
- connect \$89 $not$libresoc.v:50847$1659_Y
- connect \$91 $and$libresoc.v:50848$1660_Y
- connect \$93 $not$libresoc.v:50849$1661_Y
- connect \$95 $not$libresoc.v:50850$1662_Y
- connect \$97 $not$libresoc.v:50851$1663_Y
+ connect \$99 $and$libresoc.v:50798$1606_Y
+ connect \$101 $not$libresoc.v:50799$1607_Y
+ connect \$103 $not$libresoc.v:50800$1608_Y
+ connect \$105 $not$libresoc.v:50801$1609_Y
+ connect \$107 $and$libresoc.v:50802$1610_Y
+ connect \$10 $ne$libresoc.v:50803$1611_Y
+ connect \$109 $not$libresoc.v:50804$1612_Y
+ connect \$111 $not$libresoc.v:50805$1613_Y
+ connect \$113 $and$libresoc.v:50806$1614_Y
+ connect \$115 $not$libresoc.v:50807$1615_Y
+ connect \$118 $mul$libresoc.v:50808$1616_Y
+ connect \$117 $shr$libresoc.v:50809$1617_Y [31:0]
+ connect \$122 $mul$libresoc.v:50810$1618_Y
+ connect \$121 $shr$libresoc.v:50811$1619_Y [31:0]
+ connect \$125 $ne$libresoc.v:50812$1620_Y
+ connect \$127 $pos$libresoc.v:50813$1622_Y
+ connect \$129 $pos$libresoc.v:50814$1624_Y
+ connect \$133 $sub$libresoc.v:50815$1625_Y
+ connect \$137 $add$libresoc.v:50816$1626_Y
+ connect \$13 $sub$libresoc.v:50817$1627_Y
+ connect \$15 $or$libresoc.v:50818$1628_Y
+ connect \$17 $or$libresoc.v:50819$1629_Y
+ connect \$19 $ne$libresoc.v:50820$1630_Y
+ connect \$21 $not$libresoc.v:50821$1631_Y
+ connect \$23 $and$libresoc.v:50822$1632_Y
+ connect \$26 $add$libresoc.v:50823$1633_Y
+ connect \$28 $not$libresoc.v:50824$1634_Y
+ connect \$30 $not$libresoc.v:50825$1635_Y
+ connect \$32 $not$libresoc.v:50826$1636_Y
+ connect \$34 $not$libresoc.v:50827$1637_Y
+ connect \$36 $not$libresoc.v:50828$1638_Y
+ connect \$38 $not$libresoc.v:50829$1639_Y
+ connect \$40 $not$libresoc.v:50830$1640_Y
+ connect \$42 $and$libresoc.v:50831$1641_Y
+ connect \$45 $and$libresoc.v:50832$1642_Y
+ connect \$44 $reduce_or$libresoc.v:50833$1643_Y
+ connect \$57 $not$libresoc.v:50834$1644_Y
+ connect \$59 $not$libresoc.v:50835$1645_Y
+ connect \$61 $not$libresoc.v:50836$1646_Y
+ connect \$63 $not$libresoc.v:50837$1647_Y
+ connect \$65 $not$libresoc.v:50838$1648_Y
+ connect \$67 $and$libresoc.v:50839$1649_Y
+ connect \$69 $not$libresoc.v:50840$1650_Y
+ connect \$71 $not$libresoc.v:50841$1651_Y
+ connect \$73 $and$libresoc.v:50842$1652_Y
+ connect \$75 $not$libresoc.v:50843$1653_Y
+ connect \$77 $not$libresoc.v:50844$1654_Y
+ connect \$79 $and$libresoc.v:50845$1655_Y
+ connect \$81 $not$libresoc.v:50846$1656_Y
+ connect \$83 $not$libresoc.v:50847$1657_Y
+ connect \$85 $and$libresoc.v:50848$1658_Y
+ connect \$87 $not$libresoc.v:50849$1659_Y
+ connect \$89 $not$libresoc.v:50850$1660_Y
+ connect \$91 $and$libresoc.v:50851$1661_Y
+ connect \$93 $not$libresoc.v:50852$1662_Y
+ connect \$95 $not$libresoc.v:50853$1663_Y
+ connect \$97 $not$libresoc.v:50854$1664_Y
connect \$12 \$13
connect \$25 \$26
connect \$132 \$133
connect \por_clk \clk
connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src }
end
-attribute \src "libresoc.v:52519.1-52833.10"
+attribute \src "libresoc.v:52522.1-52836.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_icp"
attribute \generator "nMigen"
module \xics_icp
- attribute \src "libresoc.v:52697.3-52725.6"
+ attribute \src "libresoc.v:52700.3-52728.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:52748.3-52756.6"
- wire $0\core_irq_o$next[0:0]$2296
- attribute \src "libresoc.v:52639.3-52640.37"
+ attribute \src "libresoc.v:52751.3-52759.6"
+ wire $0\core_irq_o$next[0:0]$2297
+ attribute \src "libresoc.v:52642.3-52643.37"
wire $0\core_irq_o[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 8 $0\cppr$10[7:0]$2300
- attribute \src "libresoc.v:52653.3-52668.6"
- wire width 8 $0\cppr$next[7:0]$2279
- attribute \src "libresoc.v:52643.3-52644.25"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 8 $0\cppr$10[7:0]$2301
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire width 8 $0\cppr$next[7:0]$2280
+ attribute \src "libresoc.v:52646.3-52647.25"
wire width 8 $0\cppr[7:0]
- attribute \src "libresoc.v:52757.3-52766.6"
+ attribute \src "libresoc.v:52760.3-52769.6"
wire width 32 $0\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:52520.7-52520.20"
+ attribute \src "libresoc.v:52523.7-52523.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire $0\irq$12[0:0]$2301
- attribute \src "libresoc.v:52653.3-52668.6"
- wire $0\irq$next[0:0]$2280
- attribute \src "libresoc.v:52647.3-52648.23"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire $0\irq$12[0:0]$2302
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire $0\irq$next[0:0]$2281
+ attribute \src "libresoc.v:52650.3-52651.23"
wire $0\irq[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 8 $0\mfrr$11[7:0]$2302
- attribute \src "libresoc.v:52653.3-52668.6"
- wire width 8 $0\mfrr$next[7:0]$2281
- attribute \src "libresoc.v:52645.3-52646.25"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 8 $0\mfrr$11[7:0]$2303
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire width 8 $0\mfrr$next[7:0]$2282
+ attribute \src "libresoc.v:52648.3-52649.25"
wire width 8 $0\mfrr[7:0]
- attribute \src "libresoc.v:52736.3-52747.6"
+ attribute \src "libresoc.v:52739.3-52750.6"
wire width 8 $0\min_pri[7:0]
- attribute \src "libresoc.v:52726.3-52735.6"
+ attribute \src "libresoc.v:52729.3-52738.6"
wire width 8 $0\pending_priority[7:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire $0\wb_ack$14[0:0]$2303
- attribute \src "libresoc.v:52653.3-52668.6"
- wire $0\wb_ack$next[0:0]$2282
- attribute \src "libresoc.v:52651.3-52652.29"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire $0\wb_ack$14[0:0]$2304
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire $0\wb_ack$next[0:0]$2283
+ attribute \src "libresoc.v:52654.3-52655.29"
wire $0\wb_ack[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 32 $0\wb_rd_data$13[31:0]$2304
- attribute \src "libresoc.v:52653.3-52668.6"
- wire width 32 $0\wb_rd_data$next[31:0]$2283
- attribute \src "libresoc.v:52649.3-52650.37"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 32 $0\wb_rd_data$13[31:0]$2305
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire width 32 $0\wb_rd_data$next[31:0]$2284
+ attribute \src "libresoc.v:52652.3-52653.37"
wire width 32 $0\wb_rd_data[31:0]
- attribute \src "libresoc.v:52669.3-52696.6"
+ attribute \src "libresoc.v:52672.3-52699.6"
wire $0\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 24 $0\xisr$9[23:0]$2305
- attribute \src "libresoc.v:52653.3-52668.6"
- wire width 24 $0\xisr$next[23:0]$2284
- attribute \src "libresoc.v:52641.3-52642.25"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 24 $0\xisr$9[23:0]$2306
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire width 24 $0\xisr$next[23:0]$2285
+ attribute \src "libresoc.v:52644.3-52645.25"
wire width 24 $0\xisr[23:0]
- attribute \src "libresoc.v:52697.3-52725.6"
+ attribute \src "libresoc.v:52700.3-52728.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:52748.3-52756.6"
- wire $1\core_irq_o$next[0:0]$2297
- attribute \src "libresoc.v:52549.7-52549.24"
+ attribute \src "libresoc.v:52751.3-52759.6"
+ wire $1\core_irq_o$next[0:0]$2298
+ attribute \src "libresoc.v:52552.7-52552.24"
wire $1\core_irq_o[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 8 $1\cppr$10[7:0]$2306
- attribute \src "libresoc.v:52653.3-52668.6"
- wire width 8 $1\cppr$next[7:0]$2285
- attribute \src "libresoc.v:52553.13-52553.25"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 8 $1\cppr$10[7:0]$2307
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire width 8 $1\cppr$next[7:0]$2286
+ attribute \src "libresoc.v:52556.13-52556.25"
wire width 8 $1\cppr[7:0]
- attribute \src "libresoc.v:52757.3-52766.6"
+ attribute \src "libresoc.v:52760.3-52769.6"
wire width 32 $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire $1\irq$12[0:0]$2316
- attribute \src "libresoc.v:52653.3-52668.6"
- wire $1\irq$next[0:0]$2286
- attribute \src "libresoc.v:52582.7-52582.17"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire $1\irq$12[0:0]$2317
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire $1\irq$next[0:0]$2287
+ attribute \src "libresoc.v:52585.7-52585.17"
wire $1\irq[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 8 $1\mfrr$11[7:0]$2307
- attribute \src "libresoc.v:52653.3-52668.6"
- wire width 8 $1\mfrr$next[7:0]$2287
- attribute \src "libresoc.v:52590.13-52590.25"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 8 $1\mfrr$11[7:0]$2308
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire width 8 $1\mfrr$next[7:0]$2288
+ attribute \src "libresoc.v:52593.13-52593.25"
wire width 8 $1\mfrr[7:0]
- attribute \src "libresoc.v:52736.3-52747.6"
+ attribute \src "libresoc.v:52739.3-52750.6"
wire width 8 $1\min_pri[7:0]
- attribute \src "libresoc.v:52726.3-52735.6"
+ attribute \src "libresoc.v:52729.3-52738.6"
wire width 8 $1\pending_priority[7:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire $1\wb_ack$14[0:0]$2308
- attribute \src "libresoc.v:52653.3-52668.6"
- wire $1\wb_ack$next[0:0]$2288
- attribute \src "libresoc.v:52604.7-52604.20"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire $1\wb_ack$14[0:0]$2309
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire $1\wb_ack$next[0:0]$2289
+ attribute \src "libresoc.v:52607.7-52607.20"
wire $1\wb_ack[0:0]
- attribute \src "libresoc.v:52653.3-52668.6"
- wire width 32 $1\wb_rd_data$next[31:0]$2289
- attribute \src "libresoc.v:52612.14-52612.32"
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire width 32 $1\wb_rd_data$next[31:0]$2290
+ attribute \src "libresoc.v:52615.14-52615.32"
wire width 32 $1\wb_rd_data[31:0]
- attribute \src "libresoc.v:52669.3-52696.6"
+ attribute \src "libresoc.v:52672.3-52699.6"
wire $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 24 $1\xisr$9[23:0]$2313
- attribute \src "libresoc.v:52653.3-52668.6"
- wire width 24 $1\xisr$next[23:0]$2290
- attribute \src "libresoc.v:52622.14-52622.31"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 24 $1\xisr$9[23:0]$2314
+ attribute \src "libresoc.v:52656.3-52671.6"
+ wire width 24 $1\xisr$next[23:0]$2291
+ attribute \src "libresoc.v:52625.14-52625.31"
wire width 24 $1\xisr[23:0]
- attribute \src "libresoc.v:52697.3-52725.6"
+ attribute \src "libresoc.v:52700.3-52728.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 8 $2\cppr$10[7:0]$2309
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 8 $2\mfrr$11[7:0]$2310
- attribute \src "libresoc.v:52669.3-52696.6"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 8 $2\cppr$10[7:0]$2310
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 8 $2\mfrr$11[7:0]$2311
+ attribute \src "libresoc.v:52672.3-52699.6"
wire $2\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 24 $2\xisr$9[23:0]$2314
- attribute \src "libresoc.v:52697.3-52725.6"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 24 $2\xisr$9[23:0]$2315
+ attribute \src "libresoc.v:52700.3-52728.6"
wire width 32 $3\be_out[31:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 8 $3\cppr$10[7:0]$2311
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 8 $3\mfrr$11[7:0]$2312
- attribute \src "libresoc.v:52669.3-52696.6"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 8 $3\cppr$10[7:0]$2312
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 8 $3\mfrr$11[7:0]$2313
+ attribute \src "libresoc.v:52672.3-52699.6"
wire $3\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52767.3-52829.6"
- wire width 8 $4\cppr$10[7:0]$2315
- attribute \src "libresoc.v:52669.3-52696.6"
+ attribute \src "libresoc.v:52770.3-52832.6"
+ wire width 8 $4\cppr$10[7:0]$2316
+ attribute \src "libresoc.v:52672.3-52699.6"
wire $4\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52629.18-52629.116"
- wire $and$libresoc.v:52629$2261_Y
- attribute \src "libresoc.v:52633.18-52633.116"
- wire $and$libresoc.v:52633$2265_Y
- attribute \src "libresoc.v:52635.18-52635.116"
- wire $and$libresoc.v:52635$2267_Y
- attribute \src "libresoc.v:52638.17-52638.109"
- wire $and$libresoc.v:52638$2270_Y
- attribute \src "libresoc.v:52634.18-52634.110"
- wire $eq$libresoc.v:52634$2266_Y
- attribute \src "libresoc.v:52631.18-52631.114"
- wire $lt$libresoc.v:52631$2263_Y
- attribute \src "libresoc.v:52632.18-52632.109"
- wire $lt$libresoc.v:52632$2264_Y
- attribute \src "libresoc.v:52637.18-52637.114"
- wire $lt$libresoc.v:52637$2269_Y
- attribute \src "libresoc.v:52630.18-52630.109"
- wire $ne$libresoc.v:52630$2262_Y
- attribute \src "libresoc.v:52636.18-52636.109"
- wire $ne$libresoc.v:52636$2268_Y
+ attribute \src "libresoc.v:52632.18-52632.116"
+ wire $and$libresoc.v:52632$2262_Y
+ attribute \src "libresoc.v:52636.18-52636.116"
+ wire $and$libresoc.v:52636$2266_Y
+ attribute \src "libresoc.v:52638.18-52638.116"
+ wire $and$libresoc.v:52638$2268_Y
+ attribute \src "libresoc.v:52641.17-52641.109"
+ wire $and$libresoc.v:52641$2271_Y
+ attribute \src "libresoc.v:52637.18-52637.110"
+ wire $eq$libresoc.v:52637$2267_Y
+ attribute \src "libresoc.v:52634.18-52634.114"
+ wire $lt$libresoc.v:52634$2264_Y
+ attribute \src "libresoc.v:52635.18-52635.109"
+ wire $lt$libresoc.v:52635$2265_Y
+ attribute \src "libresoc.v:52640.18-52640.114"
+ wire $lt$libresoc.v:52640$2270_Y
+ attribute \src "libresoc.v:52633.18-52633.109"
+ wire $ne$libresoc.v:52633$2263_Y
+ attribute \src "libresoc.v:52639.18-52639.109"
+ wire $ne$libresoc.v:52639$2269_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
wire \$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
wire width 8 input 3 \ics_i_pri
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45"
wire width 4 input 2 \ics_i_src
- attribute \src "libresoc.v:52520.7-52520.15"
+ attribute \src "libresoc.v:52523.7-52523.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64"
wire \irq
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61"
wire width 24 \xisr$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:52629$2261
+ cell $and $and$libresoc.v:52632$2262
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:52629$2261_Y
+ connect \Y $and$libresoc.v:52632$2262_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:52633$2265
+ cell $and $and$libresoc.v:52636$2266
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:52633$2265_Y
+ connect \Y $and$libresoc.v:52636$2266_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117"
- cell $and $and$libresoc.v:52635$2267
+ cell $and $and$libresoc.v:52638$2268
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__cyc
connect \B \icp_wb__stb
- connect \Y $and$libresoc.v:52635$2267_Y
+ connect \Y $and$libresoc.v:52638$2268_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96"
- cell $and $and$libresoc.v:52638$2270
+ cell $and $and$libresoc.v:52641$2271
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_ack
connect \B \icp_wb__cyc
- connect \Y $and$libresoc.v:52638$2270_Y
+ connect \Y $and$libresoc.v:52641$2271_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162"
- cell $eq $eq$libresoc.v:52634$2266
+ cell $eq $eq$libresoc.v:52637$2267
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \icp_wb__sel
connect \B 4'1111
- connect \Y $eq$libresoc.v:52634$2266_Y
+ connect \Y $eq$libresoc.v:52637$2267_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:52631$2263
+ cell $lt $lt$libresoc.v:52634$2264
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:52631$2263_Y
+ connect \Y $lt$libresoc.v:52634$2264_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
- cell $lt $lt$libresoc.v:52632$2264
+ cell $lt $lt$libresoc.v:52635$2265
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \min_pri
connect \B \cppr$10
- connect \Y $lt$libresoc.v:52632$2264_Y
+ connect \Y $lt$libresoc.v:52635$2265_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
- cell $lt $lt$libresoc.v:52637$2269
+ cell $lt $lt$libresoc.v:52640$2270
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \mfrr
connect \B \pending_priority
- connect \Y $lt$libresoc.v:52637$2269_Y
+ connect \Y $lt$libresoc.v:52640$2270_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:52630$2262
+ cell $ne $ne$libresoc.v:52633$2263
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:52630$2262_Y
+ connect \Y $ne$libresoc.v:52633$2263_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
- cell $ne $ne$libresoc.v:52636$2268
+ cell $ne $ne$libresoc.v:52639$2269
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_i_pri
connect \B 8'11111111
- connect \Y $ne$libresoc.v:52636$2268_Y
+ connect \Y $ne$libresoc.v:52639$2269_Y
end
- attribute \src "libresoc.v:52520.7-52520.20"
- process $proc$libresoc.v:52520$2317
+ attribute \src "libresoc.v:52523.7-52523.20"
+ process $proc$libresoc.v:52523$2318
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:52549.7-52549.24"
- process $proc$libresoc.v:52549$2318
+ attribute \src "libresoc.v:52552.7-52552.24"
+ process $proc$libresoc.v:52552$2319
assign { } { }
assign $1\core_irq_o[0:0] 1'0
sync always
sync init
update \core_irq_o $1\core_irq_o[0:0]
end
- attribute \src "libresoc.v:52553.13-52553.25"
- process $proc$libresoc.v:52553$2319
+ attribute \src "libresoc.v:52556.13-52556.25"
+ process $proc$libresoc.v:52556$2320
assign { } { }
assign $1\cppr[7:0] 8'00000000
sync always
sync init
update \cppr $1\cppr[7:0]
end
- attribute \src "libresoc.v:52582.7-52582.17"
- process $proc$libresoc.v:52582$2320
+ attribute \src "libresoc.v:52585.7-52585.17"
+ process $proc$libresoc.v:52585$2321
assign { } { }
assign $1\irq[0:0] 1'0
sync always
sync init
update \irq $1\irq[0:0]
end
- attribute \src "libresoc.v:52590.13-52590.25"
- process $proc$libresoc.v:52590$2321
+ attribute \src "libresoc.v:52593.13-52593.25"
+ process $proc$libresoc.v:52593$2322
assign { } { }
assign $1\mfrr[7:0] 8'11111111
sync always
sync init
update \mfrr $1\mfrr[7:0]
end
- attribute \src "libresoc.v:52604.7-52604.20"
- process $proc$libresoc.v:52604$2322
+ attribute \src "libresoc.v:52607.7-52607.20"
+ process $proc$libresoc.v:52607$2323
assign { } { }
assign $1\wb_ack[0:0] 1'0
sync always
sync init
update \wb_ack $1\wb_ack[0:0]
end
- attribute \src "libresoc.v:52612.14-52612.32"
- process $proc$libresoc.v:52612$2323
+ attribute \src "libresoc.v:52615.14-52615.32"
+ process $proc$libresoc.v:52615$2324
assign { } { }
assign $1\wb_rd_data[31:0] 0
sync always
sync init
update \wb_rd_data $1\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:52622.14-52622.31"
- process $proc$libresoc.v:52622$2324
+ attribute \src "libresoc.v:52625.14-52625.31"
+ process $proc$libresoc.v:52625$2325
assign { } { }
assign $1\xisr[23:0] 24'000000000000000000000000
sync always
sync init
update \xisr $1\xisr[23:0]
end
- attribute \src "libresoc.v:52639.3-52640.37"
- process $proc$libresoc.v:52639$2271
+ attribute \src "libresoc.v:52642.3-52643.37"
+ process $proc$libresoc.v:52642$2272
assign { } { }
assign $0\core_irq_o[0:0] \core_irq_o$next
sync posedge \clk
update \core_irq_o $0\core_irq_o[0:0]
end
- attribute \src "libresoc.v:52641.3-52642.25"
- process $proc$libresoc.v:52641$2272
+ attribute \src "libresoc.v:52644.3-52645.25"
+ process $proc$libresoc.v:52644$2273
assign { } { }
assign $0\xisr[23:0] \xisr$next
sync posedge \clk
update \xisr $0\xisr[23:0]
end
- attribute \src "libresoc.v:52643.3-52644.25"
- process $proc$libresoc.v:52643$2273
+ attribute \src "libresoc.v:52646.3-52647.25"
+ process $proc$libresoc.v:52646$2274
assign { } { }
assign $0\cppr[7:0] \cppr$next
sync posedge \clk
update \cppr $0\cppr[7:0]
end
- attribute \src "libresoc.v:52645.3-52646.25"
- process $proc$libresoc.v:52645$2274
+ attribute \src "libresoc.v:52648.3-52649.25"
+ process $proc$libresoc.v:52648$2275
assign { } { }
assign $0\mfrr[7:0] \mfrr$next
sync posedge \clk
update \mfrr $0\mfrr[7:0]
end
- attribute \src "libresoc.v:52647.3-52648.23"
- process $proc$libresoc.v:52647$2275
+ attribute \src "libresoc.v:52650.3-52651.23"
+ process $proc$libresoc.v:52650$2276
assign { } { }
assign $0\irq[0:0] \irq$next
sync posedge \clk
update \irq $0\irq[0:0]
end
- attribute \src "libresoc.v:52649.3-52650.37"
- process $proc$libresoc.v:52649$2276
+ attribute \src "libresoc.v:52652.3-52653.37"
+ process $proc$libresoc.v:52652$2277
assign { } { }
assign $0\wb_rd_data[31:0] \wb_rd_data$next
sync posedge \clk
update \wb_rd_data $0\wb_rd_data[31:0]
end
- attribute \src "libresoc.v:52651.3-52652.29"
- process $proc$libresoc.v:52651$2277
+ attribute \src "libresoc.v:52654.3-52655.29"
+ process $proc$libresoc.v:52654$2278
assign { } { }
assign $0\wb_ack[0:0] \wb_ack$next
sync posedge \clk
update \wb_ack $0\wb_ack[0:0]
end
- attribute \src "libresoc.v:52653.3-52668.6"
- process $proc$libresoc.v:52653$2278
+ attribute \src "libresoc.v:52656.3-52671.6"
+ process $proc$libresoc.v:52656$2279
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\cppr$next[7:0]$2279 $1\cppr$next[7:0]$2285
- assign $0\irq$next[0:0]$2280 $1\irq$next[0:0]$2286
- assign $0\mfrr$next[7:0]$2281 $1\mfrr$next[7:0]$2287
- assign $0\wb_ack$next[0:0]$2282 $1\wb_ack$next[0:0]$2288
- assign $0\wb_rd_data$next[31:0]$2283 $1\wb_rd_data$next[31:0]$2289
- assign $0\xisr$next[23:0]$2284 $1\xisr$next[23:0]$2290
- attribute \src "libresoc.v:52654.5-52654.29"
+ assign $0\cppr$next[7:0]$2280 $1\cppr$next[7:0]$2286
+ assign $0\irq$next[0:0]$2281 $1\irq$next[0:0]$2287
+ assign $0\mfrr$next[7:0]$2282 $1\mfrr$next[7:0]$2288
+ assign $0\wb_ack$next[0:0]$2283 $1\wb_ack$next[0:0]$2289
+ assign $0\wb_rd_data$next[31:0]$2284 $1\wb_rd_data$next[31:0]$2290
+ assign $0\xisr$next[23:0]$2285 $1\xisr$next[23:0]$2291
+ attribute \src "libresoc.v:52657.5-52657.29"
switch \initial
- attribute \src "libresoc.v:52654.9-52654.17"
+ attribute \src "libresoc.v:52657.9-52657.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\xisr$next[23:0]$2290 24'000000000000000000000000
- assign $1\cppr$next[7:0]$2285 8'00000000
- assign $1\mfrr$next[7:0]$2287 8'11111111
- assign $1\irq$next[0:0]$2286 1'0
- assign $1\wb_rd_data$next[31:0]$2289 0
- assign $1\wb_ack$next[0:0]$2288 1'0
+ assign $1\xisr$next[23:0]$2291 24'000000000000000000000000
+ assign $1\cppr$next[7:0]$2286 8'00000000
+ assign $1\mfrr$next[7:0]$2288 8'11111111
+ assign $1\irq$next[0:0]$2287 1'0
+ assign $1\wb_rd_data$next[31:0]$2290 0
+ assign $1\wb_ack$next[0:0]$2289 1'0
case
- assign $1\cppr$next[7:0]$2285 \cppr$2
- assign $1\irq$next[0:0]$2286 \irq$4
- assign $1\mfrr$next[7:0]$2287 \mfrr$3
- assign $1\wb_ack$next[0:0]$2288 \wb_ack$6
- assign $1\wb_rd_data$next[31:0]$2289 \wb_rd_data$5
- assign $1\xisr$next[23:0]$2290 \xisr$1
+ assign $1\cppr$next[7:0]$2286 \cppr$2
+ assign $1\irq$next[0:0]$2287 \irq$4
+ assign $1\mfrr$next[7:0]$2288 \mfrr$3
+ assign $1\wb_ack$next[0:0]$2289 \wb_ack$6
+ assign $1\wb_rd_data$next[31:0]$2290 \wb_rd_data$5
+ assign $1\xisr$next[23:0]$2291 \xisr$1
end
sync always
- update \cppr$next $0\cppr$next[7:0]$2279
- update \irq$next $0\irq$next[0:0]$2280
- update \mfrr$next $0\mfrr$next[7:0]$2281
- update \wb_ack$next $0\wb_ack$next[0:0]$2282
- update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2283
- update \xisr$next $0\xisr$next[23:0]$2284
+ update \cppr$next $0\cppr$next[7:0]$2280
+ update \irq$next $0\irq$next[0:0]$2281
+ update \mfrr$next $0\mfrr$next[7:0]$2282
+ update \wb_ack$next $0\wb_ack$next[0:0]$2283
+ update \wb_rd_data$next $0\wb_rd_data$next[31:0]$2284
+ update \xisr$next $0\xisr$next[23:0]$2285
end
- attribute \src "libresoc.v:52669.3-52696.6"
- process $proc$libresoc.v:52669$2291
+ attribute \src "libresoc.v:52672.3-52699.6"
+ process $proc$libresoc.v:52672$2292
assign { } { }
assign { } { }
assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0]
- attribute \src "libresoc.v:52670.5-52670.29"
+ attribute \src "libresoc.v:52673.5-52673.29"
switch \initial
- attribute \src "libresoc.v:52670.9-52670.17"
+ attribute \src "libresoc.v:52673.9-52673.17"
case 1'1
case
end
sync always
update \xirr_accept_rd $0\xirr_accept_rd[0:0]
end
- attribute \src "libresoc.v:52697.3-52725.6"
- process $proc$libresoc.v:52697$2292
+ attribute \src "libresoc.v:52700.3-52728.6"
+ process $proc$libresoc.v:52700$2293
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:52698.5-52698.29"
+ attribute \src "libresoc.v:52701.5-52701.29"
switch \initial
- attribute \src "libresoc.v:52698.9-52698.17"
+ attribute \src "libresoc.v:52701.9-52701.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:52726.3-52735.6"
- process $proc$libresoc.v:52726$2293
+ attribute \src "libresoc.v:52729.3-52738.6"
+ process $proc$libresoc.v:52729$2294
assign { } { }
assign { } { }
assign $0\pending_priority[7:0] $1\pending_priority[7:0]
- attribute \src "libresoc.v:52727.5-52727.29"
+ attribute \src "libresoc.v:52730.5-52730.29"
switch \initial
- attribute \src "libresoc.v:52727.9-52727.17"
+ attribute \src "libresoc.v:52730.9-52730.17"
case 1'1
case
end
sync always
update \pending_priority $0\pending_priority[7:0]
end
- attribute \src "libresoc.v:52736.3-52747.6"
- process $proc$libresoc.v:52736$2294
+ attribute \src "libresoc.v:52739.3-52750.6"
+ process $proc$libresoc.v:52739$2295
assign { } { }
assign $0\min_pri[7:0] $1\min_pri[7:0]
- attribute \src "libresoc.v:52737.5-52737.29"
+ attribute \src "libresoc.v:52740.5-52740.29"
switch \initial
- attribute \src "libresoc.v:52737.9-52737.17"
+ attribute \src "libresoc.v:52740.9-52740.17"
case 1'1
case
end
sync always
update \min_pri $0\min_pri[7:0]
end
- attribute \src "libresoc.v:52748.3-52756.6"
- process $proc$libresoc.v:52748$2295
+ attribute \src "libresoc.v:52751.3-52759.6"
+ process $proc$libresoc.v:52751$2296
assign { } { }
assign { } { }
- assign $0\core_irq_o$next[0:0]$2296 $1\core_irq_o$next[0:0]$2297
- attribute \src "libresoc.v:52749.5-52749.29"
+ assign $0\core_irq_o$next[0:0]$2297 $1\core_irq_o$next[0:0]$2298
+ attribute \src "libresoc.v:52752.5-52752.29"
switch \initial
- attribute \src "libresoc.v:52749.9-52749.17"
+ attribute \src "libresoc.v:52752.9-52752.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\core_irq_o$next[0:0]$2297 1'0
+ assign $1\core_irq_o$next[0:0]$2298 1'0
case
- assign $1\core_irq_o$next[0:0]$2297 \irq
+ assign $1\core_irq_o$next[0:0]$2298 \irq
end
sync always
- update \core_irq_o$next $0\core_irq_o$next[0:0]$2296
+ update \core_irq_o$next $0\core_irq_o$next[0:0]$2297
end
- attribute \src "libresoc.v:52757.3-52766.6"
- process $proc$libresoc.v:52757$2298
+ attribute \src "libresoc.v:52760.3-52769.6"
+ process $proc$libresoc.v:52760$2299
assign { } { }
assign { } { }
assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0]
- attribute \src "libresoc.v:52758.5-52758.29"
+ attribute \src "libresoc.v:52761.5-52761.29"
switch \initial
- attribute \src "libresoc.v:52758.9-52758.17"
+ attribute \src "libresoc.v:52761.9-52761.17"
case 1'1
case
end
sync always
update \icp_wb__dat_r $0\icp_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:52767.3-52829.6"
- process $proc$libresoc.v:52767$2299
+ attribute \src "libresoc.v:52770.3-52832.6"
+ process $proc$libresoc.v:52770$2300
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\mfrr$11[7:0]$2302 $1\mfrr$11[7:0]$2307
- assign $0\wb_ack$14[0:0]$2303 $1\wb_ack$14[0:0]$2308
+ assign $0\mfrr$11[7:0]$2303 $1\mfrr$11[7:0]$2308
+ assign $0\wb_ack$14[0:0]$2304 $1\wb_ack$14[0:0]$2309
assign { } { }
assign { } { }
assign { } { }
- assign $0\xisr$9[23:0]$2305 $2\xisr$9[23:0]$2314
- assign $0\cppr$10[7:0]$2300 $4\cppr$10[7:0]$2315
- assign $0\wb_rd_data$13[31:0]$2304 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
- assign $0\irq$12[0:0]$2301 $1\irq$12[0:0]$2316
- attribute \src "libresoc.v:52768.5-52768.29"
+ assign $0\xisr$9[23:0]$2306 $2\xisr$9[23:0]$2315
+ assign $0\cppr$10[7:0]$2301 $4\cppr$10[7:0]$2316
+ assign $0\wb_rd_data$13[31:0]$2305 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $0\irq$12[0:0]$2302 $1\irq$12[0:0]$2317
+ attribute \src "libresoc.v:52771.5-52771.29"
switch \initial
- attribute \src "libresoc.v:52768.9-52768.17"
+ attribute \src "libresoc.v:52771.9-52771.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\wb_ack$14[0:0]$2308 1'1
- assign $1\cppr$10[7:0]$2306 $2\cppr$10[7:0]$2309
- assign $1\mfrr$11[7:0]$2307 $2\mfrr$11[7:0]$2310
+ assign $1\wb_ack$14[0:0]$2309 1'1
+ assign $1\cppr$10[7:0]$2307 $2\cppr$10[7:0]$2310
+ assign $1\mfrr$11[7:0]$2308 $2\mfrr$11[7:0]$2311
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119"
switch \icp_wb__we
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
assign { } { }
- assign $2\cppr$10[7:0]$2309 $3\cppr$10[7:0]$2311
- assign $2\mfrr$11[7:0]$2310 $3\mfrr$11[7:0]$2312
+ assign $2\cppr$10[7:0]$2310 $3\cppr$10[7:0]$2312
+ assign $2\mfrr$11[7:0]$2311 $3\mfrr$11[7:0]$2313
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121"
switch \icp_wb__adr [5:0]
attribute \src "libresoc.v:0.0-0.0"
case 6'000000
assign { } { }
- assign $3\mfrr$11[7:0]$2312 \mfrr
- assign $3\cppr$10[7:0]$2311 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$2313 \mfrr
+ assign $3\cppr$10[7:0]$2312 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000001
assign { } { }
- assign $3\mfrr$11[7:0]$2312 \mfrr
- assign $3\cppr$10[7:0]$2311 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$2313 \mfrr
+ assign $3\cppr$10[7:0]$2312 \be_in [31:24]
attribute \src "libresoc.v:0.0-0.0"
case 6'000011
- assign $3\cppr$10[7:0]$2311 \cppr
+ assign $3\cppr$10[7:0]$2312 \cppr
assign { } { }
- assign $3\mfrr$11[7:0]$2312 \be_in [31:24]
+ assign $3\mfrr$11[7:0]$2313 \be_in [31:24]
case
- assign $3\cppr$10[7:0]$2311 \cppr
- assign $3\mfrr$11[7:0]$2312 \mfrr
+ assign $3\cppr$10[7:0]$2312 \cppr
+ assign $3\mfrr$11[7:0]$2313 \mfrr
end
case
- assign $2\cppr$10[7:0]$2309 \cppr
- assign $2\mfrr$11[7:0]$2310 \mfrr
+ assign $2\cppr$10[7:0]$2310 \cppr
+ assign $2\mfrr$11[7:0]$2311 \mfrr
end
case
- assign $1\cppr$10[7:0]$2306 \cppr
- assign $1\mfrr$11[7:0]$2307 \mfrr
- assign $1\wb_ack$14[0:0]$2308 1'0
+ assign $1\cppr$10[7:0]$2307 \cppr
+ assign $1\mfrr$11[7:0]$2308 \mfrr
+ assign $1\wb_ack$14[0:0]$2309 1'0
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173"
switch \$17
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\xisr$9[23:0]$2313 { 20'00000000000000000001 \ics_i_src }
+ assign $1\xisr$9[23:0]$2314 { 20'00000000000000000001 \ics_i_src }
case
- assign $1\xisr$9[23:0]$2313 24'000000000000000000000000
+ assign $1\xisr$9[23:0]$2314 24'000000000000000000000000
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178"
switch \$19
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $2\xisr$9[23:0]$2314 24'000000000000000000000010
+ assign $2\xisr$9[23:0]$2315 24'000000000000000000000010
case
- assign $2\xisr$9[23:0]$2314 $1\xisr$9[23:0]$2313
+ assign $2\xisr$9[23:0]$2315 $1\xisr$9[23:0]$2314
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185"
switch \xirr_accept_rd
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $4\cppr$10[7:0]$2315 \min_pri
+ assign $4\cppr$10[7:0]$2316 \min_pri
case
- assign $4\cppr$10[7:0]$2315 $1\cppr$10[7:0]$2306
+ assign $4\cppr$10[7:0]$2316 $1\cppr$10[7:0]$2307
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195"
switch { \irq \$21 }
attribute \src "libresoc.v:0.0-0.0"
case 2'-1
assign { } { }
- assign $1\irq$12[0:0]$2316 1'1
+ assign $1\irq$12[0:0]$2317 1'1
case
- assign $1\irq$12[0:0]$2316 1'0
+ assign $1\irq$12[0:0]$2317 1'0
end
sync always
- update \cppr$10 $0\cppr$10[7:0]$2300
- update \irq$12 $0\irq$12[0:0]$2301
- update \mfrr$11 $0\mfrr$11[7:0]$2302
- update \wb_ack$14 $0\wb_ack$14[0:0]$2303
- update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2304
- update \xisr$9 $0\xisr$9[23:0]$2305
+ update \cppr$10 $0\cppr$10[7:0]$2301
+ update \irq$12 $0\irq$12[0:0]$2302
+ update \mfrr$11 $0\mfrr$11[7:0]$2303
+ update \wb_ack$14 $0\wb_ack$14[0:0]$2304
+ update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$2305
+ update \xisr$9 $0\xisr$9[23:0]$2306
end
- connect \$15 $and$libresoc.v:52629$2261_Y
- connect \$17 $ne$libresoc.v:52630$2262_Y
- connect \$19 $lt$libresoc.v:52631$2263_Y
- connect \$21 $lt$libresoc.v:52632$2264_Y
- connect \$23 $and$libresoc.v:52633$2265_Y
- connect \$25 $eq$libresoc.v:52634$2266_Y
- connect \$27 $and$libresoc.v:52635$2267_Y
- connect \$29 $ne$libresoc.v:52636$2268_Y
- connect \$31 $lt$libresoc.v:52637$2269_Y
- connect \$7 $and$libresoc.v:52638$2270_Y
+ connect \$15 $and$libresoc.v:52632$2262_Y
+ connect \$17 $ne$libresoc.v:52633$2263_Y
+ connect \$19 $lt$libresoc.v:52634$2264_Y
+ connect \$21 $lt$libresoc.v:52635$2265_Y
+ connect \$23 $and$libresoc.v:52636$2266_Y
+ connect \$25 $eq$libresoc.v:52637$2267_Y
+ connect \$27 $and$libresoc.v:52638$2268_Y
+ connect \$29 $ne$libresoc.v:52639$2269_Y
+ connect \$31 $lt$libresoc.v:52640$2270_Y
+ connect \$7 $and$libresoc.v:52641$2271_Y
connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 }
connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] }
connect \icp_wb__ack \$7
end
-attribute \src "libresoc.v:52837.1-53886.10"
+attribute \src "libresoc.v:52840.1-53889.10"
attribute \cells_not_processed 1
attribute \nmigen.hierarchy "test_issuer.ti.xics_ics"
attribute \generator "nMigen"
module \xics_ics
- attribute \src "libresoc.v:53767.3-53816.6"
+ attribute \src "libresoc.v:53770.3-53819.6"
wire width 32 $0\be_out[31:0]
- attribute \src "libresoc.v:53478.3-53487.6"
+ attribute \src "libresoc.v:53481.3-53490.6"
wire width 4 $0\cur_idx0[3:0]
- attribute \src "libresoc.v:53687.3-53696.6"
+ attribute \src "libresoc.v:53690.3-53699.6"
wire width 4 $0\cur_idx10[3:0]
- attribute \src "libresoc.v:53707.3-53716.6"
+ attribute \src "libresoc.v:53710.3-53719.6"
wire width 4 $0\cur_idx11[3:0]
- attribute \src "libresoc.v:53727.3-53736.6"
+ attribute \src "libresoc.v:53730.3-53739.6"
wire width 4 $0\cur_idx12[3:0]
- attribute \src "libresoc.v:53747.3-53756.6"
+ attribute \src "libresoc.v:53750.3-53759.6"
wire width 4 $0\cur_idx13[3:0]
- attribute \src "libresoc.v:53817.3-53826.6"
+ attribute \src "libresoc.v:53820.3-53829.6"
wire width 4 $0\cur_idx14[3:0]
- attribute \src "libresoc.v:53837.3-53846.6"
+ attribute \src "libresoc.v:53840.3-53849.6"
wire width 4 $0\cur_idx15[3:0]
- attribute \src "libresoc.v:53498.3-53507.6"
+ attribute \src "libresoc.v:53501.3-53510.6"
wire width 4 $0\cur_idx1[3:0]
- attribute \src "libresoc.v:53518.3-53527.6"
+ attribute \src "libresoc.v:53521.3-53530.6"
wire width 4 $0\cur_idx2[3:0]
- attribute \src "libresoc.v:53538.3-53547.6"
+ attribute \src "libresoc.v:53541.3-53550.6"
wire width 4 $0\cur_idx3[3:0]
- attribute \src "libresoc.v:53567.3-53576.6"
+ attribute \src "libresoc.v:53570.3-53579.6"
wire width 4 $0\cur_idx4[3:0]
- attribute \src "libresoc.v:53587.3-53596.6"
+ attribute \src "libresoc.v:53590.3-53599.6"
wire width 4 $0\cur_idx5[3:0]
- attribute \src "libresoc.v:53607.3-53616.6"
+ attribute \src "libresoc.v:53610.3-53619.6"
wire width 4 $0\cur_idx6[3:0]
- attribute \src "libresoc.v:53627.3-53636.6"
+ attribute \src "libresoc.v:53630.3-53639.6"
wire width 4 $0\cur_idx7[3:0]
- attribute \src "libresoc.v:53647.3-53656.6"
+ attribute \src "libresoc.v:53650.3-53659.6"
wire width 4 $0\cur_idx8[3:0]
- attribute \src "libresoc.v:53667.3-53676.6"
+ attribute \src "libresoc.v:53670.3-53679.6"
wire width 4 $0\cur_idx9[3:0]
- attribute \src "libresoc.v:53468.3-53477.6"
+ attribute \src "libresoc.v:53471.3-53480.6"
wire width 8 $0\cur_pri0[7:0]
- attribute \src "libresoc.v:53677.3-53686.6"
+ attribute \src "libresoc.v:53680.3-53689.6"
wire width 8 $0\cur_pri10[7:0]
- attribute \src "libresoc.v:53697.3-53706.6"
+ attribute \src "libresoc.v:53700.3-53709.6"
wire width 8 $0\cur_pri11[7:0]
- attribute \src "libresoc.v:53717.3-53726.6"
+ attribute \src "libresoc.v:53720.3-53729.6"
wire width 8 $0\cur_pri12[7:0]
- attribute \src "libresoc.v:53737.3-53746.6"
+ attribute \src "libresoc.v:53740.3-53749.6"
wire width 8 $0\cur_pri13[7:0]
- attribute \src "libresoc.v:53757.3-53766.6"
+ attribute \src "libresoc.v:53760.3-53769.6"
wire width 8 $0\cur_pri14[7:0]
- attribute \src "libresoc.v:53827.3-53836.6"
+ attribute \src "libresoc.v:53830.3-53839.6"
wire width 8 $0\cur_pri15[7:0]
- attribute \src "libresoc.v:53488.3-53497.6"
+ attribute \src "libresoc.v:53491.3-53500.6"
wire width 8 $0\cur_pri1[7:0]
- attribute \src "libresoc.v:53508.3-53517.6"
+ attribute \src "libresoc.v:53511.3-53520.6"
wire width 8 $0\cur_pri2[7:0]
- attribute \src "libresoc.v:53528.3-53537.6"
+ attribute \src "libresoc.v:53531.3-53540.6"
wire width 8 $0\cur_pri3[7:0]
- attribute \src "libresoc.v:53548.3-53557.6"
+ attribute \src "libresoc.v:53551.3-53560.6"
wire width 8 $0\cur_pri4[7:0]
- attribute \src "libresoc.v:53577.3-53586.6"
+ attribute \src "libresoc.v:53580.3-53589.6"
wire width 8 $0\cur_pri5[7:0]
- attribute \src "libresoc.v:53597.3-53606.6"
+ attribute \src "libresoc.v:53600.3-53609.6"
wire width 8 $0\cur_pri6[7:0]
- attribute \src "libresoc.v:53617.3-53626.6"
+ attribute \src "libresoc.v:53620.3-53629.6"
wire width 8 $0\cur_pri7[7:0]
- attribute \src "libresoc.v:53637.3-53646.6"
+ attribute \src "libresoc.v:53640.3-53649.6"
wire width 8 $0\cur_pri8[7:0]
- attribute \src "libresoc.v:53657.3-53666.6"
+ attribute \src "libresoc.v:53660.3-53669.6"
wire width 8 $0\cur_pri9[7:0]
- attribute \src "libresoc.v:53847.3-53856.6"
+ attribute \src "libresoc.v:53850.3-53859.6"
wire $0\ibit[0:0]
- attribute \src "libresoc.v:53358.3-53359.25"
+ attribute \src "libresoc.v:53361.3-53362.25"
wire width 8 $0\icp_o_pri[7:0]
- attribute \src "libresoc.v:53356.3-53357.28"
+ attribute \src "libresoc.v:53359.3-53360.28"
wire width 4 $0\icp_o_src[3:0]
- attribute \src "libresoc.v:53866.3-53874.6"
- wire $0\ics_wb__ack$next[0:0]$2571
- attribute \src "libresoc.v:53350.3-53351.39"
+ attribute \src "libresoc.v:53869.3-53877.6"
+ wire $0\ics_wb__ack$next[0:0]$2572
+ attribute \src "libresoc.v:53353.3-53354.39"
wire $0\ics_wb__ack[0:0]
- attribute \src "libresoc.v:53857.3-53865.6"
- wire width 32 $0\ics_wb__dat_r$next[31:0]$2568
- attribute \src "libresoc.v:53352.3-53353.43"
+ attribute \src "libresoc.v:53860.3-53868.6"
+ wire width 32 $0\ics_wb__dat_r$next[31:0]$2569
+ attribute \src "libresoc.v:53355.3-53356.43"
wire width 32 $0\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:52838.7-52838.20"
+ attribute \src "libresoc.v:52841.7-52841.20"
wire $0\initial[0:0]
- attribute \src "libresoc.v:53558.3-53566.6"
- wire width 16 $0\int_level_l$next[15:0]$2540
- attribute \src "libresoc.v:53354.3-53355.39"
+ attribute \src "libresoc.v:53561.3-53569.6"
+ wire width 16 $0\int_level_l$next[15:0]$2541
+ attribute \src "libresoc.v:53357.3-53358.39"
wire width 16 $0\int_level_l[15:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive0_pri$next[7:0]$2450
- attribute \src "libresoc.v:53360.3-53361.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive0_pri$next[7:0]$2451
+ attribute \src "libresoc.v:53363.3-53364.35"
wire width 8 $0\xive0_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive10_pri$next[7:0]$2451
- attribute \src "libresoc.v:53380.3-53381.37"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive10_pri$next[7:0]$2452
+ attribute \src "libresoc.v:53383.3-53384.37"
wire width 8 $0\xive10_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive11_pri$next[7:0]$2452
- attribute \src "libresoc.v:53340.3-53341.37"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive11_pri$next[7:0]$2453
+ attribute \src "libresoc.v:53343.3-53344.37"
wire width 8 $0\xive11_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive12_pri$next[7:0]$2453
- attribute \src "libresoc.v:53342.3-53343.37"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive12_pri$next[7:0]$2454
+ attribute \src "libresoc.v:53345.3-53346.37"
wire width 8 $0\xive12_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive13_pri$next[7:0]$2454
- attribute \src "libresoc.v:53344.3-53345.37"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive13_pri$next[7:0]$2455
+ attribute \src "libresoc.v:53347.3-53348.37"
wire width 8 $0\xive13_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive14_pri$next[7:0]$2455
- attribute \src "libresoc.v:53346.3-53347.37"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive14_pri$next[7:0]$2456
+ attribute \src "libresoc.v:53349.3-53350.37"
wire width 8 $0\xive14_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive15_pri$next[7:0]$2456
- attribute \src "libresoc.v:53348.3-53349.37"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive15_pri$next[7:0]$2457
+ attribute \src "libresoc.v:53351.3-53352.37"
wire width 8 $0\xive15_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive1_pri$next[7:0]$2457
- attribute \src "libresoc.v:53362.3-53363.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive1_pri$next[7:0]$2458
+ attribute \src "libresoc.v:53365.3-53366.35"
wire width 8 $0\xive1_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive2_pri$next[7:0]$2458
- attribute \src "libresoc.v:53364.3-53365.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive2_pri$next[7:0]$2459
+ attribute \src "libresoc.v:53367.3-53368.35"
wire width 8 $0\xive2_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive3_pri$next[7:0]$2459
- attribute \src "libresoc.v:53366.3-53367.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive3_pri$next[7:0]$2460
+ attribute \src "libresoc.v:53369.3-53370.35"
wire width 8 $0\xive3_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive4_pri$next[7:0]$2460
- attribute \src "libresoc.v:53368.3-53369.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive4_pri$next[7:0]$2461
+ attribute \src "libresoc.v:53371.3-53372.35"
wire width 8 $0\xive4_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive5_pri$next[7:0]$2461
- attribute \src "libresoc.v:53370.3-53371.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive5_pri$next[7:0]$2462
+ attribute \src "libresoc.v:53373.3-53374.35"
wire width 8 $0\xive5_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive6_pri$next[7:0]$2462
- attribute \src "libresoc.v:53372.3-53373.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive6_pri$next[7:0]$2463
+ attribute \src "libresoc.v:53375.3-53376.35"
wire width 8 $0\xive6_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive7_pri$next[7:0]$2463
- attribute \src "libresoc.v:53374.3-53375.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive7_pri$next[7:0]$2464
+ attribute \src "libresoc.v:53377.3-53378.35"
wire width 8 $0\xive7_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive8_pri$next[7:0]$2464
- attribute \src "libresoc.v:53376.3-53377.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive8_pri$next[7:0]$2465
+ attribute \src "libresoc.v:53379.3-53380.35"
wire width 8 $0\xive8_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $0\xive9_pri$next[7:0]$2465
- attribute \src "libresoc.v:53378.3-53379.35"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $0\xive9_pri$next[7:0]$2466
+ attribute \src "libresoc.v:53381.3-53382.35"
wire width 8 $0\xive9_pri[7:0]
- attribute \src "libresoc.v:53767.3-53816.6"
+ attribute \src "libresoc.v:53770.3-53819.6"
wire width 32 $1\be_out[31:0]
- attribute \src "libresoc.v:53478.3-53487.6"
+ attribute \src "libresoc.v:53481.3-53490.6"
wire width 4 $1\cur_idx0[3:0]
- attribute \src "libresoc.v:53687.3-53696.6"
+ attribute \src "libresoc.v:53690.3-53699.6"
wire width 4 $1\cur_idx10[3:0]
- attribute \src "libresoc.v:53707.3-53716.6"
+ attribute \src "libresoc.v:53710.3-53719.6"
wire width 4 $1\cur_idx11[3:0]
- attribute \src "libresoc.v:53727.3-53736.6"
+ attribute \src "libresoc.v:53730.3-53739.6"
wire width 4 $1\cur_idx12[3:0]
- attribute \src "libresoc.v:53747.3-53756.6"
+ attribute \src "libresoc.v:53750.3-53759.6"
wire width 4 $1\cur_idx13[3:0]
- attribute \src "libresoc.v:53817.3-53826.6"
+ attribute \src "libresoc.v:53820.3-53829.6"
wire width 4 $1\cur_idx14[3:0]
- attribute \src "libresoc.v:53837.3-53846.6"
+ attribute \src "libresoc.v:53840.3-53849.6"
wire width 4 $1\cur_idx15[3:0]
- attribute \src "libresoc.v:53498.3-53507.6"
+ attribute \src "libresoc.v:53501.3-53510.6"
wire width 4 $1\cur_idx1[3:0]
- attribute \src "libresoc.v:53518.3-53527.6"
+ attribute \src "libresoc.v:53521.3-53530.6"
wire width 4 $1\cur_idx2[3:0]
- attribute \src "libresoc.v:53538.3-53547.6"
+ attribute \src "libresoc.v:53541.3-53550.6"
wire width 4 $1\cur_idx3[3:0]
- attribute \src "libresoc.v:53567.3-53576.6"
+ attribute \src "libresoc.v:53570.3-53579.6"
wire width 4 $1\cur_idx4[3:0]
- attribute \src "libresoc.v:53587.3-53596.6"
+ attribute \src "libresoc.v:53590.3-53599.6"
wire width 4 $1\cur_idx5[3:0]
- attribute \src "libresoc.v:53607.3-53616.6"
+ attribute \src "libresoc.v:53610.3-53619.6"
wire width 4 $1\cur_idx6[3:0]
- attribute \src "libresoc.v:53627.3-53636.6"
+ attribute \src "libresoc.v:53630.3-53639.6"
wire width 4 $1\cur_idx7[3:0]
- attribute \src "libresoc.v:53647.3-53656.6"
+ attribute \src "libresoc.v:53650.3-53659.6"
wire width 4 $1\cur_idx8[3:0]
- attribute \src "libresoc.v:53667.3-53676.6"
+ attribute \src "libresoc.v:53670.3-53679.6"
wire width 4 $1\cur_idx9[3:0]
- attribute \src "libresoc.v:53468.3-53477.6"
+ attribute \src "libresoc.v:53471.3-53480.6"
wire width 8 $1\cur_pri0[7:0]
- attribute \src "libresoc.v:53677.3-53686.6"
+ attribute \src "libresoc.v:53680.3-53689.6"
wire width 8 $1\cur_pri10[7:0]
- attribute \src "libresoc.v:53697.3-53706.6"
+ attribute \src "libresoc.v:53700.3-53709.6"
wire width 8 $1\cur_pri11[7:0]
- attribute \src "libresoc.v:53717.3-53726.6"
+ attribute \src "libresoc.v:53720.3-53729.6"
wire width 8 $1\cur_pri12[7:0]
- attribute \src "libresoc.v:53737.3-53746.6"
+ attribute \src "libresoc.v:53740.3-53749.6"
wire width 8 $1\cur_pri13[7:0]
- attribute \src "libresoc.v:53757.3-53766.6"
+ attribute \src "libresoc.v:53760.3-53769.6"
wire width 8 $1\cur_pri14[7:0]
- attribute \src "libresoc.v:53827.3-53836.6"
+ attribute \src "libresoc.v:53830.3-53839.6"
wire width 8 $1\cur_pri15[7:0]
- attribute \src "libresoc.v:53488.3-53497.6"
+ attribute \src "libresoc.v:53491.3-53500.6"
wire width 8 $1\cur_pri1[7:0]
- attribute \src "libresoc.v:53508.3-53517.6"
+ attribute \src "libresoc.v:53511.3-53520.6"
wire width 8 $1\cur_pri2[7:0]
- attribute \src "libresoc.v:53528.3-53537.6"
+ attribute \src "libresoc.v:53531.3-53540.6"
wire width 8 $1\cur_pri3[7:0]
- attribute \src "libresoc.v:53548.3-53557.6"
+ attribute \src "libresoc.v:53551.3-53560.6"
wire width 8 $1\cur_pri4[7:0]
- attribute \src "libresoc.v:53577.3-53586.6"
+ attribute \src "libresoc.v:53580.3-53589.6"
wire width 8 $1\cur_pri5[7:0]
- attribute \src "libresoc.v:53597.3-53606.6"
+ attribute \src "libresoc.v:53600.3-53609.6"
wire width 8 $1\cur_pri6[7:0]
- attribute \src "libresoc.v:53617.3-53626.6"
+ attribute \src "libresoc.v:53620.3-53629.6"
wire width 8 $1\cur_pri7[7:0]
- attribute \src "libresoc.v:53637.3-53646.6"
+ attribute \src "libresoc.v:53640.3-53649.6"
wire width 8 $1\cur_pri8[7:0]
- attribute \src "libresoc.v:53657.3-53666.6"
+ attribute \src "libresoc.v:53660.3-53669.6"
wire width 8 $1\cur_pri9[7:0]
- attribute \src "libresoc.v:53847.3-53856.6"
+ attribute \src "libresoc.v:53850.3-53859.6"
wire $1\ibit[0:0]
- attribute \src "libresoc.v:53119.13-53119.30"
+ attribute \src "libresoc.v:53122.13-53122.30"
wire width 8 $1\icp_o_pri[7:0]
- attribute \src "libresoc.v:53124.13-53124.29"
+ attribute \src "libresoc.v:53127.13-53127.29"
wire width 4 $1\icp_o_src[3:0]
- attribute \src "libresoc.v:53866.3-53874.6"
- wire $1\ics_wb__ack$next[0:0]$2572
- attribute \src "libresoc.v:53133.7-53133.25"
+ attribute \src "libresoc.v:53869.3-53877.6"
+ wire $1\ics_wb__ack$next[0:0]$2573
+ attribute \src "libresoc.v:53136.7-53136.25"
wire $1\ics_wb__ack[0:0]
- attribute \src "libresoc.v:53857.3-53865.6"
- wire width 32 $1\ics_wb__dat_r$next[31:0]$2569
- attribute \src "libresoc.v:53142.14-53142.35"
+ attribute \src "libresoc.v:53860.3-53868.6"
+ wire width 32 $1\ics_wb__dat_r$next[31:0]$2570
+ attribute \src "libresoc.v:53145.14-53145.35"
wire width 32 $1\ics_wb__dat_r[31:0]
- attribute \src "libresoc.v:53558.3-53566.6"
- wire width 16 $1\int_level_l$next[15:0]$2541
- attribute \src "libresoc.v:53154.14-53154.36"
+ attribute \src "libresoc.v:53561.3-53569.6"
+ wire width 16 $1\int_level_l$next[15:0]$2542
+ attribute \src "libresoc.v:53157.14-53157.36"
wire width 16 $1\int_level_l[15:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive0_pri$next[7:0]$2466
- attribute \src "libresoc.v:53174.13-53174.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive0_pri$next[7:0]$2467
+ attribute \src "libresoc.v:53177.13-53177.30"
wire width 8 $1\xive0_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive10_pri$next[7:0]$2467
- attribute \src "libresoc.v:53178.13-53178.31"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive10_pri$next[7:0]$2468
+ attribute \src "libresoc.v:53181.13-53181.31"
wire width 8 $1\xive10_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive11_pri$next[7:0]$2468
- attribute \src "libresoc.v:53182.13-53182.31"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive11_pri$next[7:0]$2469
+ attribute \src "libresoc.v:53185.13-53185.31"
wire width 8 $1\xive11_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive12_pri$next[7:0]$2469
- attribute \src "libresoc.v:53186.13-53186.31"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive12_pri$next[7:0]$2470
+ attribute \src "libresoc.v:53189.13-53189.31"
wire width 8 $1\xive12_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive13_pri$next[7:0]$2470
- attribute \src "libresoc.v:53190.13-53190.31"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive13_pri$next[7:0]$2471
+ attribute \src "libresoc.v:53193.13-53193.31"
wire width 8 $1\xive13_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive14_pri$next[7:0]$2471
- attribute \src "libresoc.v:53194.13-53194.31"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive14_pri$next[7:0]$2472
+ attribute \src "libresoc.v:53197.13-53197.31"
wire width 8 $1\xive14_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive15_pri$next[7:0]$2472
- attribute \src "libresoc.v:53198.13-53198.31"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive15_pri$next[7:0]$2473
+ attribute \src "libresoc.v:53201.13-53201.31"
wire width 8 $1\xive15_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive1_pri$next[7:0]$2473
- attribute \src "libresoc.v:53202.13-53202.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive1_pri$next[7:0]$2474
+ attribute \src "libresoc.v:53205.13-53205.30"
wire width 8 $1\xive1_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive2_pri$next[7:0]$2474
- attribute \src "libresoc.v:53206.13-53206.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive2_pri$next[7:0]$2475
+ attribute \src "libresoc.v:53209.13-53209.30"
wire width 8 $1\xive2_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive3_pri$next[7:0]$2475
- attribute \src "libresoc.v:53210.13-53210.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive3_pri$next[7:0]$2476
+ attribute \src "libresoc.v:53213.13-53213.30"
wire width 8 $1\xive3_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive4_pri$next[7:0]$2476
- attribute \src "libresoc.v:53214.13-53214.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive4_pri$next[7:0]$2477
+ attribute \src "libresoc.v:53217.13-53217.30"
wire width 8 $1\xive4_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive5_pri$next[7:0]$2477
- attribute \src "libresoc.v:53218.13-53218.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive5_pri$next[7:0]$2478
+ attribute \src "libresoc.v:53221.13-53221.30"
wire width 8 $1\xive5_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive6_pri$next[7:0]$2478
- attribute \src "libresoc.v:53222.13-53222.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive6_pri$next[7:0]$2479
+ attribute \src "libresoc.v:53225.13-53225.30"
wire width 8 $1\xive6_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive7_pri$next[7:0]$2479
- attribute \src "libresoc.v:53226.13-53226.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive7_pri$next[7:0]$2480
+ attribute \src "libresoc.v:53229.13-53229.30"
wire width 8 $1\xive7_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive8_pri$next[7:0]$2480
- attribute \src "libresoc.v:53230.13-53230.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive8_pri$next[7:0]$2481
+ attribute \src "libresoc.v:53233.13-53233.30"
wire width 8 $1\xive8_pri[7:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $1\xive9_pri$next[7:0]$2481
- attribute \src "libresoc.v:53234.13-53234.30"
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $1\xive9_pri$next[7:0]$2482
+ attribute \src "libresoc.v:53237.13-53237.30"
wire width 8 $1\xive9_pri[7:0]
- attribute \src "libresoc.v:53767.3-53816.6"
+ attribute \src "libresoc.v:53770.3-53819.6"
wire width 32 $2\be_out[31:0]
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive0_pri$next[7:0]$2482
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive10_pri$next[7:0]$2483
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive11_pri$next[7:0]$2484
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive12_pri$next[7:0]$2485
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive13_pri$next[7:0]$2486
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive14_pri$next[7:0]$2487
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive15_pri$next[7:0]$2488
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive1_pri$next[7:0]$2489
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive2_pri$next[7:0]$2490
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive3_pri$next[7:0]$2491
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive4_pri$next[7:0]$2492
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive5_pri$next[7:0]$2493
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive6_pri$next[7:0]$2494
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive7_pri$next[7:0]$2495
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive8_pri$next[7:0]$2496
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $2\xive9_pri$next[7:0]$2497
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive0_pri$next[7:0]$2498
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive10_pri$next[7:0]$2499
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive11_pri$next[7:0]$2500
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive12_pri$next[7:0]$2501
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive13_pri$next[7:0]$2502
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive14_pri$next[7:0]$2503
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive15_pri$next[7:0]$2504
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive1_pri$next[7:0]$2505
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive2_pri$next[7:0]$2506
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive3_pri$next[7:0]$2507
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive4_pri$next[7:0]$2508
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive5_pri$next[7:0]$2509
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive6_pri$next[7:0]$2510
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive7_pri$next[7:0]$2511
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive8_pri$next[7:0]$2512
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $3\xive9_pri$next[7:0]$2513
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive0_pri$next[7:0]$2514
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive10_pri$next[7:0]$2515
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive11_pri$next[7:0]$2516
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive12_pri$next[7:0]$2517
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive13_pri$next[7:0]$2518
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive14_pri$next[7:0]$2519
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive15_pri$next[7:0]$2520
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive1_pri$next[7:0]$2521
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive2_pri$next[7:0]$2522
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive3_pri$next[7:0]$2523
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive4_pri$next[7:0]$2524
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive5_pri$next[7:0]$2525
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive6_pri$next[7:0]$2526
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive7_pri$next[7:0]$2527
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive8_pri$next[7:0]$2528
- attribute \src "libresoc.v:53382.3-53467.6"
- wire width 8 $4\xive9_pri$next[7:0]$2529
- attribute \src "libresoc.v:53239.19-53239.113"
- wire $and$libresoc.v:53239$2327_Y
- attribute \src "libresoc.v:53241.19-53241.114"
- wire $and$libresoc.v:53241$2329_Y
- attribute \src "libresoc.v:53243.19-53243.114"
- wire $and$libresoc.v:53243$2331_Y
- attribute \src "libresoc.v:53245.19-53245.114"
- wire $and$libresoc.v:53245$2333_Y
- attribute \src "libresoc.v:53247.19-53247.114"
- wire $and$libresoc.v:53247$2335_Y
- attribute \src "libresoc.v:53249.19-53249.114"
- wire $and$libresoc.v:53249$2337_Y
- attribute \src "libresoc.v:53251.19-53251.114"
- wire $and$libresoc.v:53251$2339_Y
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive0_pri$next[7:0]$2483
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive10_pri$next[7:0]$2484
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive11_pri$next[7:0]$2485
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive12_pri$next[7:0]$2486
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive13_pri$next[7:0]$2487
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive14_pri$next[7:0]$2488
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive15_pri$next[7:0]$2489
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive1_pri$next[7:0]$2490
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive2_pri$next[7:0]$2491
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive3_pri$next[7:0]$2492
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive4_pri$next[7:0]$2493
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive5_pri$next[7:0]$2494
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive6_pri$next[7:0]$2495
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive7_pri$next[7:0]$2496
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive8_pri$next[7:0]$2497
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $2\xive9_pri$next[7:0]$2498
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive0_pri$next[7:0]$2499
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive10_pri$next[7:0]$2500
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive11_pri$next[7:0]$2501
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive12_pri$next[7:0]$2502
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive13_pri$next[7:0]$2503
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive14_pri$next[7:0]$2504
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive15_pri$next[7:0]$2505
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive1_pri$next[7:0]$2506
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive2_pri$next[7:0]$2507
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive3_pri$next[7:0]$2508
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive4_pri$next[7:0]$2509
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive5_pri$next[7:0]$2510
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive6_pri$next[7:0]$2511
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive7_pri$next[7:0]$2512
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive8_pri$next[7:0]$2513
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $3\xive9_pri$next[7:0]$2514
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $4\xive0_pri$next[7:0]$2515
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $4\xive10_pri$next[7:0]$2516
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $4\xive11_pri$next[7:0]$2517
+ attribute \src "libresoc.v:53385.3-53470.6"
+ wire width 8 $4\xive12_pri$next[7:0]$2518
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attribute \src "libresoc.v:53309.18-53309.116"
- wire width 8 $ternary$libresoc.v:53309$2397_Y
- attribute \src "libresoc.v:53311.18-53311.116"
- wire width 8 $ternary$libresoc.v:53311$2399_Y
- attribute \src "libresoc.v:53313.18-53313.117"
- wire width 8 $ternary$libresoc.v:53313$2401_Y
- attribute \src "libresoc.v:53315.18-53315.117"
- wire width 8 $ternary$libresoc.v:53315$2403_Y
- attribute \src "libresoc.v:53317.18-53317.117"
- wire width 8 $ternary$libresoc.v:53317$2405_Y
+ wire width 8 $ternary$libresoc.v:53309$2395_Y
+ attribute \src "libresoc.v:53312.18-53312.116"
+ wire width 8 $ternary$libresoc.v:53312$2398_Y
+ attribute \src "libresoc.v:53314.18-53314.116"
+ wire width 8 $ternary$libresoc.v:53314$2400_Y
+ attribute \src "libresoc.v:53316.18-53316.117"
+ wire width 8 $ternary$libresoc.v:53316$2402_Y
+ attribute \src "libresoc.v:53318.18-53318.117"
+ wire width 8 $ternary$libresoc.v:53318$2404_Y
attribute \src "libresoc.v:53320.18-53320.117"
- wire width 8 $ternary$libresoc.v:53320$2408_Y
- attribute \src "libresoc.v:53322.18-53322.117"
- wire width 8 $ternary$libresoc.v:53322$2410_Y
- attribute \src "libresoc.v:53324.18-53324.117"
- wire width 8 $ternary$libresoc.v:53324$2412_Y
+ wire width 8 $ternary$libresoc.v:53320$2406_Y
+ attribute \src "libresoc.v:53323.18-53323.117"
+ wire width 8 $ternary$libresoc.v:53323$2409_Y
+ attribute \src "libresoc.v:53325.18-53325.117"
+ wire width 8 $ternary$libresoc.v:53325$2411_Y
+ attribute \src "libresoc.v:53327.18-53327.117"
+ wire width 8 $ternary$libresoc.v:53327$2413_Y
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
wire \$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
wire input 7 \ics_wb__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235"
wire input 11 \ics_wb__we
- attribute \src "libresoc.v:52838.7-52838.15"
+ attribute \src "libresoc.v:52841.7-52841.15"
wire \initial
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237"
wire width 16 input 5 \int_level_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221"
wire width 8 \xive9_pri$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53239$2327
+ cell $and $and$libresoc.v:53242$2328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$99
- connect \Y $and$libresoc.v:53239$2327_Y
+ connect \Y $and$libresoc.v:53242$2328_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53241$2329
+ cell $and $and$libresoc.v:53244$2330
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [3]
connect \B \$103
- connect \Y $and$libresoc.v:53241$2329_Y
+ connect \Y $and$libresoc.v:53244$2330_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53243$2331
+ cell $and $and$libresoc.v:53246$2332
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$107
- connect \Y $and$libresoc.v:53243$2331_Y
+ connect \Y $and$libresoc.v:53246$2332_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53245$2333
+ cell $and $and$libresoc.v:53248$2334
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [4]
connect \B \$111
- connect \Y $and$libresoc.v:53245$2333_Y
+ connect \Y $and$libresoc.v:53248$2334_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53247$2335
+ cell $and $and$libresoc.v:53250$2336
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$115
- connect \Y $and$libresoc.v:53247$2335_Y
+ connect \Y $and$libresoc.v:53250$2336_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53249$2337
+ cell $and $and$libresoc.v:53252$2338
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [5]
connect \B \$119
- connect \Y $and$libresoc.v:53249$2337_Y
+ connect \Y $and$libresoc.v:53252$2338_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53251$2339
+ cell $and $and$libresoc.v:53254$2340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$123
- connect \Y $and$libresoc.v:53251$2339_Y
+ connect \Y $and$libresoc.v:53254$2340_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53254$2342
+ cell $and $and$libresoc.v:53257$2343
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [6]
connect \B \$127
- connect \Y $and$libresoc.v:53254$2342_Y
+ connect \Y $and$libresoc.v:53257$2343_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53256$2344
+ cell $and $and$libresoc.v:53259$2345
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$131
- connect \Y $and$libresoc.v:53256$2344_Y
+ connect \Y $and$libresoc.v:53259$2345_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53258$2346
+ cell $and $and$libresoc.v:53261$2347
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [7]
connect \B \$135
- connect \Y $and$libresoc.v:53258$2346_Y
+ connect \Y $and$libresoc.v:53261$2347_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53261$2349
+ cell $and $and$libresoc.v:53264$2350
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$139
- connect \Y $and$libresoc.v:53261$2349_Y
+ connect \Y $and$libresoc.v:53264$2350_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53263$2351
+ cell $and $and$libresoc.v:53266$2352
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [8]
connect \B \$143
- connect \Y $and$libresoc.v:53263$2351_Y
+ connect \Y $and$libresoc.v:53266$2352_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53265$2353
+ cell $and $and$libresoc.v:53268$2354
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$147
- connect \Y $and$libresoc.v:53265$2353_Y
+ connect \Y $and$libresoc.v:53268$2354_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53267$2355
+ cell $and $and$libresoc.v:53270$2356
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [9]
connect \B \$151
- connect \Y $and$libresoc.v:53267$2355_Y
+ connect \Y $and$libresoc.v:53270$2356_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53269$2357
+ cell $and $and$libresoc.v:53272$2358
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$155
- connect \Y $and$libresoc.v:53269$2357_Y
+ connect \Y $and$libresoc.v:53272$2358_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53271$2359
+ cell $and $and$libresoc.v:53274$2360
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [10]
connect \B \$159
- connect \Y $and$libresoc.v:53271$2359_Y
+ connect \Y $and$libresoc.v:53274$2360_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53273$2361
+ cell $and $and$libresoc.v:53276$2362
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$163
- connect \Y $and$libresoc.v:53273$2361_Y
+ connect \Y $and$libresoc.v:53276$2362_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53276$2364
+ cell $and $and$libresoc.v:53279$2365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [11]
connect \B \$167
- connect \Y $and$libresoc.v:53276$2364_Y
+ connect \Y $and$libresoc.v:53279$2365_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53278$2366
+ cell $and $and$libresoc.v:53281$2367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$171
- connect \Y $and$libresoc.v:53278$2366_Y
+ connect \Y $and$libresoc.v:53281$2367_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53280$2368
+ cell $and $and$libresoc.v:53283$2369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [12]
connect \B \$175
- connect \Y $and$libresoc.v:53280$2368_Y
+ connect \Y $and$libresoc.v:53283$2369_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53283$2371
+ cell $and $and$libresoc.v:53286$2372
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$179
- connect \Y $and$libresoc.v:53283$2371_Y
+ connect \Y $and$libresoc.v:53286$2372_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53285$2373
+ cell $and $and$libresoc.v:53288$2374
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [13]
connect \B \$183
- connect \Y $and$libresoc.v:53285$2373_Y
+ connect \Y $and$libresoc.v:53288$2374_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53287$2375
+ cell $and $and$libresoc.v:53290$2376
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$187
- connect \Y $and$libresoc.v:53287$2375_Y
+ connect \Y $and$libresoc.v:53290$2376_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53289$2377
+ cell $and $and$libresoc.v:53292$2378
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [14]
connect \B \$191
- connect \Y $and$libresoc.v:53289$2377_Y
+ connect \Y $and$libresoc.v:53292$2378_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53291$2379
+ cell $and $and$libresoc.v:53294$2380
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$195
- connect \Y $and$libresoc.v:53291$2379_Y
+ connect \Y $and$libresoc.v:53294$2380_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53294$2382
+ cell $and $and$libresoc.v:53297$2383
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [15]
connect \B \$199
- connect \Y $and$libresoc.v:53294$2382_Y
+ connect \Y $and$libresoc.v:53297$2383_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304"
- cell $and $and$libresoc.v:53318$2406
+ cell $and $and$libresoc.v:53321$2407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__cyc
connect \B \ics_wb__stb
- connect \Y $and$libresoc.v:53318$2406_Y
+ connect \Y $and$libresoc.v:53321$2407_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341"
- cell $and $and$libresoc.v:53326$2414
+ cell $and $and$libresoc.v:53329$2415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wb_valid
connect \B \ics_wb__we
- connect \Y $and$libresoc.v:53326$2414_Y
+ connect \Y $and$libresoc.v:53329$2415_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53328$2416
+ cell $and $and$libresoc.v:53331$2417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$75
- connect \Y $and$libresoc.v:53328$2416_Y
+ connect \Y $and$libresoc.v:53331$2417_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53330$2418
+ cell $and $and$libresoc.v:53333$2419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [0]
connect \B \$79
- connect \Y $and$libresoc.v:53330$2418_Y
+ connect \Y $and$libresoc.v:53333$2419_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53332$2420
+ cell $and $and$libresoc.v:53335$2421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$83
- connect \Y $and$libresoc.v:53332$2420_Y
+ connect \Y $and$libresoc.v:53335$2421_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53335$2423
+ cell $and $and$libresoc.v:53338$2424
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [1]
connect \B \$87
- connect \Y $and$libresoc.v:53335$2423_Y
+ connect \Y $and$libresoc.v:53338$2424_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53337$2425
+ cell $and $and$libresoc.v:53340$2426
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$91
- connect \Y $and$libresoc.v:53337$2425_Y
+ connect \Y $and$libresoc.v:53340$2426_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369"
- cell $and $and$libresoc.v:53339$2427
+ cell $and $and$libresoc.v:53342$2428
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \int_level_l [2]
connect \B \$95
- connect \Y $and$libresoc.v:53339$2427_Y
+ connect \Y $and$libresoc.v:53342$2428_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53253$2341
+ cell $eq $eq$libresoc.v:53256$2342
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53253$2341_Y
+ connect \Y $eq$libresoc.v:53256$2342_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53275$2363
+ cell $eq $eq$libresoc.v:53278$2364
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53275$2363_Y
+ connect \Y $eq$libresoc.v:53278$2364_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293"
- cell $eq $eq$libresoc.v:53292$2380
+ cell $eq $eq$libresoc.v:53295$2381
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 1'0
- connect \Y $eq$libresoc.v:53292$2380_Y
+ connect \Y $eq$libresoc.v:53295$2381_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53295$2383
+ cell $eq $eq$libresoc.v:53298$2384
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cur_pri15
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53295$2383_Y
+ connect \Y $eq$libresoc.v:53298$2384_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53297$2385
+ cell $eq $eq$libresoc.v:53300$2386
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53297$2385_Y
+ connect \Y $eq$libresoc.v:53300$2386_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53299$2387
+ cell $eq $eq$libresoc.v:53302$2388
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53299$2387_Y
+ connect \Y $eq$libresoc.v:53302$2388_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53301$2389
+ cell $eq $eq$libresoc.v:53304$2390
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53301$2389_Y
+ connect \Y $eq$libresoc.v:53304$2390_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53303$2391
+ cell $eq $eq$libresoc.v:53306$2392
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53303$2391_Y
+ connect \Y $eq$libresoc.v:53306$2392_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53305$2393
+ cell $eq $eq$libresoc.v:53308$2394
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53305$2393_Y
+ connect \Y $eq$libresoc.v:53308$2394_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294"
- cell $eq $eq$libresoc.v:53307$2395
+ cell $eq $eq$libresoc.v:53310$2396
parameter \A_SIGNED 0
parameter \A_WIDTH 10
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ics_wb__adr [9:0]
connect \B 3'100
- connect \Y $eq$libresoc.v:53307$2395_Y
+ connect \Y $eq$libresoc.v:53310$2396_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53308$2396
+ cell $eq $eq$libresoc.v:53311$2397
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53308$2396_Y
+ connect \Y $eq$libresoc.v:53311$2397_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53310$2398
+ cell $eq $eq$libresoc.v:53313$2399
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53310$2398_Y
+ connect \Y $eq$libresoc.v:53313$2399_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53312$2400
+ cell $eq $eq$libresoc.v:53315$2401
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53312$2400_Y
+ connect \Y $eq$libresoc.v:53315$2401_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53314$2402
+ cell $eq $eq$libresoc.v:53317$2403
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53314$2402_Y
+ connect \Y $eq$libresoc.v:53317$2403_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53316$2404
+ cell $eq $eq$libresoc.v:53319$2405
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53316$2404_Y
+ connect \Y $eq$libresoc.v:53319$2405_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53319$2407
+ cell $eq $eq$libresoc.v:53322$2408
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53319$2407_Y
+ connect \Y $eq$libresoc.v:53322$2408_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53321$2409
+ cell $eq $eq$libresoc.v:53324$2410
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53321$2409_Y
+ connect \Y $eq$libresoc.v:53324$2410_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53323$2411
+ cell $eq $eq$libresoc.v:53326$2412
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53323$2411_Y
+ connect \Y $eq$libresoc.v:53326$2412_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $eq $eq$libresoc.v:53334$2422
+ cell $eq $eq$libresoc.v:53337$2423
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B 8'11111111
- connect \Y $eq$libresoc.v:53334$2422_Y
+ connect \Y $eq$libresoc.v:53337$2423_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53238$2326
+ cell $lt $lt$libresoc.v:53241$2327
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:53238$2326_Y
+ connect \Y $lt$libresoc.v:53241$2327_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53240$2328
+ cell $lt $lt$libresoc.v:53243$2329
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive3_pri
connect \B \cur_pri2
- connect \Y $lt$libresoc.v:53240$2328_Y
+ connect \Y $lt$libresoc.v:53243$2329_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53242$2330
+ cell $lt $lt$libresoc.v:53245$2331
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:53242$2330_Y
+ connect \Y $lt$libresoc.v:53245$2331_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53244$2332
+ cell $lt $lt$libresoc.v:53247$2333
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive4_pri
connect \B \cur_pri3
- connect \Y $lt$libresoc.v:53244$2332_Y
+ connect \Y $lt$libresoc.v:53247$2333_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53246$2334
+ cell $lt $lt$libresoc.v:53249$2335
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:53246$2334_Y
+ connect \Y $lt$libresoc.v:53249$2335_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53248$2336
+ cell $lt $lt$libresoc.v:53251$2337
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive5_pri
connect \B \cur_pri4
- connect \Y $lt$libresoc.v:53248$2336_Y
+ connect \Y $lt$libresoc.v:53251$2337_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53250$2338
+ cell $lt $lt$libresoc.v:53253$2339
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:53250$2338_Y
+ connect \Y $lt$libresoc.v:53253$2339_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53252$2340
+ cell $lt $lt$libresoc.v:53255$2341
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive6_pri
connect \B \cur_pri5
- connect \Y $lt$libresoc.v:53252$2340_Y
+ connect \Y $lt$libresoc.v:53255$2341_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53255$2343
+ cell $lt $lt$libresoc.v:53258$2344
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:53255$2343_Y
+ connect \Y $lt$libresoc.v:53258$2344_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53257$2345
+ cell $lt $lt$libresoc.v:53260$2346
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive7_pri
connect \B \cur_pri6
- connect \Y $lt$libresoc.v:53257$2345_Y
+ connect \Y $lt$libresoc.v:53260$2346_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53260$2348
+ cell $lt $lt$libresoc.v:53263$2349
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:53260$2348_Y
+ connect \Y $lt$libresoc.v:53263$2349_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53262$2350
+ cell $lt $lt$libresoc.v:53265$2351
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive8_pri
connect \B \cur_pri7
- connect \Y $lt$libresoc.v:53262$2350_Y
+ connect \Y $lt$libresoc.v:53265$2351_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53264$2352
+ cell $lt $lt$libresoc.v:53267$2353
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:53264$2352_Y
+ connect \Y $lt$libresoc.v:53267$2353_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53266$2354
+ cell $lt $lt$libresoc.v:53269$2355
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive9_pri
connect \B \cur_pri8
- connect \Y $lt$libresoc.v:53266$2354_Y
+ connect \Y $lt$libresoc.v:53269$2355_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53268$2356
+ cell $lt $lt$libresoc.v:53271$2357
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:53268$2356_Y
+ connect \Y $lt$libresoc.v:53271$2357_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53270$2358
+ cell $lt $lt$libresoc.v:53273$2359
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive10_pri
connect \B \cur_pri9
- connect \Y $lt$libresoc.v:53270$2358_Y
+ connect \Y $lt$libresoc.v:53273$2359_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53272$2360
+ cell $lt $lt$libresoc.v:53275$2361
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:53272$2360_Y
+ connect \Y $lt$libresoc.v:53275$2361_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53274$2362
+ cell $lt $lt$libresoc.v:53277$2363
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive11_pri
connect \B \cur_pri10
- connect \Y $lt$libresoc.v:53274$2362_Y
+ connect \Y $lt$libresoc.v:53277$2363_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53277$2365
+ cell $lt $lt$libresoc.v:53280$2366
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:53277$2365_Y
+ connect \Y $lt$libresoc.v:53280$2366_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53279$2367
+ cell $lt $lt$libresoc.v:53282$2368
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive12_pri
connect \B \cur_pri11
- connect \Y $lt$libresoc.v:53279$2367_Y
+ connect \Y $lt$libresoc.v:53282$2368_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53282$2370
+ cell $lt $lt$libresoc.v:53285$2371
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:53282$2370_Y
+ connect \Y $lt$libresoc.v:53285$2371_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53284$2372
+ cell $lt $lt$libresoc.v:53287$2373
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive13_pri
connect \B \cur_pri12
- connect \Y $lt$libresoc.v:53284$2372_Y
+ connect \Y $lt$libresoc.v:53287$2373_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53286$2374
+ cell $lt $lt$libresoc.v:53289$2375
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:53286$2374_Y
+ connect \Y $lt$libresoc.v:53289$2375_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53288$2376
+ cell $lt $lt$libresoc.v:53291$2377
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive14_pri
connect \B \cur_pri13
- connect \Y $lt$libresoc.v:53288$2376_Y
+ connect \Y $lt$libresoc.v:53291$2377_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53290$2378
+ cell $lt $lt$libresoc.v:53293$2379
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:53290$2378_Y
+ connect \Y $lt$libresoc.v:53293$2379_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53293$2381
+ cell $lt $lt$libresoc.v:53296$2382
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive15_pri
connect \B \cur_pri14
- connect \Y $lt$libresoc.v:53293$2381_Y
+ connect \Y $lt$libresoc.v:53296$2382_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53327$2415
+ cell $lt $lt$libresoc.v:53330$2416
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:53327$2415_Y
+ connect \Y $lt$libresoc.v:53330$2416_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53329$2417
+ cell $lt $lt$libresoc.v:53332$2418
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive0_pri
connect \B \max_pri
- connect \Y $lt$libresoc.v:53329$2417_Y
+ connect \Y $lt$libresoc.v:53332$2418_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53331$2419
+ cell $lt $lt$libresoc.v:53334$2420
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:53331$2419_Y
+ connect \Y $lt$libresoc.v:53334$2420_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53333$2421
+ cell $lt $lt$libresoc.v:53336$2422
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive1_pri
connect \B \cur_pri0
- connect \Y $lt$libresoc.v:53333$2421_Y
+ connect \Y $lt$libresoc.v:53336$2422_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53336$2424
+ cell $lt $lt$libresoc.v:53339$2425
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:53336$2424_Y
+ connect \Y $lt$libresoc.v:53339$2425_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251"
- cell $lt $lt$libresoc.v:53338$2426
+ cell $lt $lt$libresoc.v:53341$2427
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \xive2_pri
connect \B \cur_pri1
- connect \Y $lt$libresoc.v:53338$2426_Y
+ connect \Y $lt$libresoc.v:53341$2427_Y
end
- attribute \src "libresoc.v:53325.18-53325.40"
- cell $shr $shr$libresoc.v:53325$2413
+ attribute \src "libresoc.v:53328.18-53328.40"
+ cell $shr $shr$libresoc.v:53328$2414
parameter \A_SIGNED 0
parameter \A_WIDTH 16
parameter \B_SIGNED 0
parameter \Y_WIDTH 16
connect \A \int_level_l
connect \B \reg_idx
- connect \Y $shr$libresoc.v:53325$2413_Y
+ connect \Y $shr$libresoc.v:53328$2414_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53237$2325
+ cell $mux $ternary$libresoc.v:53240$2326
parameter \WIDTH 8
connect \A \xive0_pri
connect \B 8'11111111
connect \S \$8
- connect \Y $ternary$libresoc.v:53237$2325_Y
+ connect \Y $ternary$libresoc.v:53240$2326_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53259$2347
+ cell $mux $ternary$libresoc.v:53262$2348
parameter \WIDTH 8
connect \A \xive1_pri
connect \B 8'11111111
connect \S \$12
- connect \Y $ternary$libresoc.v:53259$2347_Y
+ connect \Y $ternary$libresoc.v:53262$2348_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53281$2369
+ cell $mux $ternary$libresoc.v:53284$2370
parameter \WIDTH 8
connect \A \xive2_pri
connect \B 8'11111111
connect \S \$16
- connect \Y $ternary$libresoc.v:53281$2369_Y
+ connect \Y $ternary$libresoc.v:53284$2370_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53296$2384
+ cell $mux $ternary$libresoc.v:53299$2385
parameter \WIDTH 8
connect \A \cur_pri15
connect \B 8'11111111
connect \S \$204
- connect \Y $ternary$libresoc.v:53296$2384_Y
+ connect \Y $ternary$libresoc.v:53299$2385_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53298$2386
+ cell $mux $ternary$libresoc.v:53301$2387
parameter \WIDTH 8
connect \A \xive3_pri
connect \B 8'11111111
connect \S \$20
- connect \Y $ternary$libresoc.v:53298$2386_Y
+ connect \Y $ternary$libresoc.v:53301$2387_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53300$2388
+ cell $mux $ternary$libresoc.v:53303$2389
parameter \WIDTH 8
connect \A \xive4_pri
connect \B 8'11111111
connect \S \$24
- connect \Y $ternary$libresoc.v:53300$2388_Y
+ connect \Y $ternary$libresoc.v:53303$2389_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53302$2390
+ cell $mux $ternary$libresoc.v:53305$2391
parameter \WIDTH 8
connect \A \xive5_pri
connect \B 8'11111111
connect \S \$28
- connect \Y $ternary$libresoc.v:53302$2390_Y
+ connect \Y $ternary$libresoc.v:53305$2391_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53304$2392
+ cell $mux $ternary$libresoc.v:53307$2393
parameter \WIDTH 8
connect \A \xive6_pri
connect \B 8'11111111
connect \S \$32
- connect \Y $ternary$libresoc.v:53304$2392_Y
+ connect \Y $ternary$libresoc.v:53307$2393_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53306$2394
+ cell $mux $ternary$libresoc.v:53309$2395
parameter \WIDTH 8
connect \A \xive7_pri
connect \B 8'11111111
connect \S \$36
- connect \Y $ternary$libresoc.v:53306$2394_Y
+ connect \Y $ternary$libresoc.v:53309$2395_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53309$2397
+ cell $mux $ternary$libresoc.v:53312$2398
parameter \WIDTH 8
connect \A \xive8_pri
connect \B 8'11111111
connect \S \$40
- connect \Y $ternary$libresoc.v:53309$2397_Y
+ connect \Y $ternary$libresoc.v:53312$2398_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53311$2399
+ cell $mux $ternary$libresoc.v:53314$2400
parameter \WIDTH 8
connect \A \xive9_pri
connect \B 8'11111111
connect \S \$44
- connect \Y $ternary$libresoc.v:53311$2399_Y
+ connect \Y $ternary$libresoc.v:53314$2400_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53313$2401
+ cell $mux $ternary$libresoc.v:53316$2402
parameter \WIDTH 8
connect \A \xive10_pri
connect \B 8'11111111
connect \S \$48
- connect \Y $ternary$libresoc.v:53313$2401_Y
+ connect \Y $ternary$libresoc.v:53316$2402_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53315$2403
+ cell $mux $ternary$libresoc.v:53318$2404
parameter \WIDTH 8
connect \A \xive11_pri
connect \B 8'11111111
connect \S \$52
- connect \Y $ternary$libresoc.v:53315$2403_Y
+ connect \Y $ternary$libresoc.v:53318$2404_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53317$2405
+ cell $mux $ternary$libresoc.v:53320$2406
parameter \WIDTH 8
connect \A \xive12_pri
connect \B 8'11111111
connect \S \$56
- connect \Y $ternary$libresoc.v:53317$2405_Y
+ connect \Y $ternary$libresoc.v:53320$2406_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53320$2408
+ cell $mux $ternary$libresoc.v:53323$2409
parameter \WIDTH 8
connect \A \xive13_pri
connect \B 8'11111111
connect \S \$60
- connect \Y $ternary$libresoc.v:53320$2408_Y
+ connect \Y $ternary$libresoc.v:53323$2409_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53322$2410
+ cell $mux $ternary$libresoc.v:53325$2411
parameter \WIDTH 8
connect \A \xive14_pri
connect \B 8'11111111
connect \S \$64
- connect \Y $ternary$libresoc.v:53322$2410_Y
+ connect \Y $ternary$libresoc.v:53325$2411_Y
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244"
- cell $mux $ternary$libresoc.v:53324$2412
+ cell $mux $ternary$libresoc.v:53327$2413
parameter \WIDTH 8
connect \A \xive15_pri
connect \B 8'11111111
connect \S \$68
- connect \Y $ternary$libresoc.v:53324$2412_Y
+ connect \Y $ternary$libresoc.v:53327$2413_Y
end
- attribute \src "libresoc.v:52838.7-52838.20"
- process $proc$libresoc.v:52838$2573
+ attribute \src "libresoc.v:52841.7-52841.20"
+ process $proc$libresoc.v:52841$2574
assign { } { }
assign $0\initial[0:0] 1'0
sync always
update \initial $0\initial[0:0]
sync init
end
- attribute \src "libresoc.v:53119.13-53119.30"
- process $proc$libresoc.v:53119$2574
+ attribute \src "libresoc.v:53122.13-53122.30"
+ process $proc$libresoc.v:53122$2575
assign { } { }
assign $1\icp_o_pri[7:0] 8'00000000
sync always
sync init
update \icp_o_pri $1\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:53124.13-53124.29"
- process $proc$libresoc.v:53124$2575
+ attribute \src "libresoc.v:53127.13-53127.29"
+ process $proc$libresoc.v:53127$2576
assign { } { }
assign $1\icp_o_src[3:0] 4'0000
sync always
sync init
update \icp_o_src $1\icp_o_src[3:0]
end
- attribute \src "libresoc.v:53133.7-53133.25"
- process $proc$libresoc.v:53133$2576
+ attribute \src "libresoc.v:53136.7-53136.25"
+ process $proc$libresoc.v:53136$2577
assign { } { }
assign $1\ics_wb__ack[0:0] 1'0
sync always
sync init
update \ics_wb__ack $1\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:53142.14-53142.35"
- process $proc$libresoc.v:53142$2577
+ attribute \src "libresoc.v:53145.14-53145.35"
+ process $proc$libresoc.v:53145$2578
assign { } { }
assign $1\ics_wb__dat_r[31:0] 0
sync always
sync init
update \ics_wb__dat_r $1\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:53154.14-53154.36"
- process $proc$libresoc.v:53154$2578
+ attribute \src "libresoc.v:53157.14-53157.36"
+ process $proc$libresoc.v:53157$2579
assign { } { }
assign $1\int_level_l[15:0] 16'0000000000000000
sync always
sync init
update \int_level_l $1\int_level_l[15:0]
end
- attribute \src "libresoc.v:53174.13-53174.30"
- process $proc$libresoc.v:53174$2579
+ attribute \src "libresoc.v:53177.13-53177.30"
+ process $proc$libresoc.v:53177$2580
assign { } { }
assign $1\xive0_pri[7:0] 8'11111111
sync always
sync init
update \xive0_pri $1\xive0_pri[7:0]
end
- attribute \src "libresoc.v:53178.13-53178.31"
- process $proc$libresoc.v:53178$2580
+ attribute \src "libresoc.v:53181.13-53181.31"
+ process $proc$libresoc.v:53181$2581
assign { } { }
assign $1\xive10_pri[7:0] 8'11111111
sync always
sync init
update \xive10_pri $1\xive10_pri[7:0]
end
- attribute \src "libresoc.v:53182.13-53182.31"
- process $proc$libresoc.v:53182$2581
+ attribute \src "libresoc.v:53185.13-53185.31"
+ process $proc$libresoc.v:53185$2582
assign { } { }
assign $1\xive11_pri[7:0] 8'11111111
sync always
sync init
update \xive11_pri $1\xive11_pri[7:0]
end
- attribute \src "libresoc.v:53186.13-53186.31"
- process $proc$libresoc.v:53186$2582
+ attribute \src "libresoc.v:53189.13-53189.31"
+ process $proc$libresoc.v:53189$2583
assign { } { }
assign $1\xive12_pri[7:0] 8'11111111
sync always
sync init
update \xive12_pri $1\xive12_pri[7:0]
end
- attribute \src "libresoc.v:53190.13-53190.31"
- process $proc$libresoc.v:53190$2583
+ attribute \src "libresoc.v:53193.13-53193.31"
+ process $proc$libresoc.v:53193$2584
assign { } { }
assign $1\xive13_pri[7:0] 8'11111111
sync always
sync init
update \xive13_pri $1\xive13_pri[7:0]
end
- attribute \src "libresoc.v:53194.13-53194.31"
- process $proc$libresoc.v:53194$2584
+ attribute \src "libresoc.v:53197.13-53197.31"
+ process $proc$libresoc.v:53197$2585
assign { } { }
assign $1\xive14_pri[7:0] 8'11111111
sync always
sync init
update \xive14_pri $1\xive14_pri[7:0]
end
- attribute \src "libresoc.v:53198.13-53198.31"
- process $proc$libresoc.v:53198$2585
+ attribute \src "libresoc.v:53201.13-53201.31"
+ process $proc$libresoc.v:53201$2586
assign { } { }
assign $1\xive15_pri[7:0] 8'11111111
sync always
sync init
update \xive15_pri $1\xive15_pri[7:0]
end
- attribute \src "libresoc.v:53202.13-53202.30"
- process $proc$libresoc.v:53202$2586
+ attribute \src "libresoc.v:53205.13-53205.30"
+ process $proc$libresoc.v:53205$2587
assign { } { }
assign $1\xive1_pri[7:0] 8'11111111
sync always
sync init
update \xive1_pri $1\xive1_pri[7:0]
end
- attribute \src "libresoc.v:53206.13-53206.30"
- process $proc$libresoc.v:53206$2587
+ attribute \src "libresoc.v:53209.13-53209.30"
+ process $proc$libresoc.v:53209$2588
assign { } { }
assign $1\xive2_pri[7:0] 8'11111111
sync always
sync init
update \xive2_pri $1\xive2_pri[7:0]
end
- attribute \src "libresoc.v:53210.13-53210.30"
- process $proc$libresoc.v:53210$2588
+ attribute \src "libresoc.v:53213.13-53213.30"
+ process $proc$libresoc.v:53213$2589
assign { } { }
assign $1\xive3_pri[7:0] 8'11111111
sync always
sync init
update \xive3_pri $1\xive3_pri[7:0]
end
- attribute \src "libresoc.v:53214.13-53214.30"
- process $proc$libresoc.v:53214$2589
+ attribute \src "libresoc.v:53217.13-53217.30"
+ process $proc$libresoc.v:53217$2590
assign { } { }
assign $1\xive4_pri[7:0] 8'11111111
sync always
sync init
update \xive4_pri $1\xive4_pri[7:0]
end
- attribute \src "libresoc.v:53218.13-53218.30"
- process $proc$libresoc.v:53218$2590
+ attribute \src "libresoc.v:53221.13-53221.30"
+ process $proc$libresoc.v:53221$2591
assign { } { }
assign $1\xive5_pri[7:0] 8'11111111
sync always
sync init
update \xive5_pri $1\xive5_pri[7:0]
end
- attribute \src "libresoc.v:53222.13-53222.30"
- process $proc$libresoc.v:53222$2591
+ attribute \src "libresoc.v:53225.13-53225.30"
+ process $proc$libresoc.v:53225$2592
assign { } { }
assign $1\xive6_pri[7:0] 8'11111111
sync always
sync init
update \xive6_pri $1\xive6_pri[7:0]
end
- attribute \src "libresoc.v:53226.13-53226.30"
- process $proc$libresoc.v:53226$2592
+ attribute \src "libresoc.v:53229.13-53229.30"
+ process $proc$libresoc.v:53229$2593
assign { } { }
assign $1\xive7_pri[7:0] 8'11111111
sync always
sync init
update \xive7_pri $1\xive7_pri[7:0]
end
- attribute \src "libresoc.v:53230.13-53230.30"
- process $proc$libresoc.v:53230$2593
+ attribute \src "libresoc.v:53233.13-53233.30"
+ process $proc$libresoc.v:53233$2594
assign { } { }
assign $1\xive8_pri[7:0] 8'11111111
sync always
sync init
update \xive8_pri $1\xive8_pri[7:0]
end
- attribute \src "libresoc.v:53234.13-53234.30"
- process $proc$libresoc.v:53234$2594
+ attribute \src "libresoc.v:53237.13-53237.30"
+ process $proc$libresoc.v:53237$2595
assign { } { }
assign $1\xive9_pri[7:0] 8'11111111
sync always
sync init
update \xive9_pri $1\xive9_pri[7:0]
end
- attribute \src "libresoc.v:53340.3-53341.37"
- process $proc$libresoc.v:53340$2428
+ attribute \src "libresoc.v:53343.3-53344.37"
+ process $proc$libresoc.v:53343$2429
assign { } { }
assign $0\xive11_pri[7:0] \xive11_pri$next
sync posedge \clk
update \xive11_pri $0\xive11_pri[7:0]
end
- attribute \src "libresoc.v:53342.3-53343.37"
- process $proc$libresoc.v:53342$2429
+ attribute \src "libresoc.v:53345.3-53346.37"
+ process $proc$libresoc.v:53345$2430
assign { } { }
assign $0\xive12_pri[7:0] \xive12_pri$next
sync posedge \clk
update \xive12_pri $0\xive12_pri[7:0]
end
- attribute \src "libresoc.v:53344.3-53345.37"
- process $proc$libresoc.v:53344$2430
+ attribute \src "libresoc.v:53347.3-53348.37"
+ process $proc$libresoc.v:53347$2431
assign { } { }
assign $0\xive13_pri[7:0] \xive13_pri$next
sync posedge \clk
update \xive13_pri $0\xive13_pri[7:0]
end
- attribute \src "libresoc.v:53346.3-53347.37"
- process $proc$libresoc.v:53346$2431
+ attribute \src "libresoc.v:53349.3-53350.37"
+ process $proc$libresoc.v:53349$2432
assign { } { }
assign $0\xive14_pri[7:0] \xive14_pri$next
sync posedge \clk
update \xive14_pri $0\xive14_pri[7:0]
end
- attribute \src "libresoc.v:53348.3-53349.37"
- process $proc$libresoc.v:53348$2432
+ attribute \src "libresoc.v:53351.3-53352.37"
+ process $proc$libresoc.v:53351$2433
assign { } { }
assign $0\xive15_pri[7:0] \xive15_pri$next
sync posedge \clk
update \xive15_pri $0\xive15_pri[7:0]
end
- attribute \src "libresoc.v:53350.3-53351.39"
- process $proc$libresoc.v:53350$2433
+ attribute \src "libresoc.v:53353.3-53354.39"
+ process $proc$libresoc.v:53353$2434
assign { } { }
assign $0\ics_wb__ack[0:0] \ics_wb__ack$next
sync posedge \clk
update \ics_wb__ack $0\ics_wb__ack[0:0]
end
- attribute \src "libresoc.v:53352.3-53353.43"
- process $proc$libresoc.v:53352$2434
+ attribute \src "libresoc.v:53355.3-53356.43"
+ process $proc$libresoc.v:53355$2435
assign { } { }
assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next
sync posedge \clk
update \ics_wb__dat_r $0\ics_wb__dat_r[31:0]
end
- attribute \src "libresoc.v:53354.3-53355.39"
- process $proc$libresoc.v:53354$2435
+ attribute \src "libresoc.v:53357.3-53358.39"
+ process $proc$libresoc.v:53357$2436
assign { } { }
assign $0\int_level_l[15:0] \int_level_l$next
sync posedge \clk
update \int_level_l $0\int_level_l[15:0]
end
- attribute \src "libresoc.v:53356.3-53357.28"
- process $proc$libresoc.v:53356$2436
+ attribute \src "libresoc.v:53359.3-53360.28"
+ process $proc$libresoc.v:53359$2437
assign { } { }
assign $0\icp_o_src[3:0] \cur_idx15
sync posedge \clk
update \icp_o_src $0\icp_o_src[3:0]
end
- attribute \src "libresoc.v:53358.3-53359.25"
- process $proc$libresoc.v:53358$2437
+ attribute \src "libresoc.v:53361.3-53362.25"
+ process $proc$libresoc.v:53361$2438
assign { } { }
assign $0\icp_o_pri[7:0] \$203
sync posedge \clk
update \icp_o_pri $0\icp_o_pri[7:0]
end
- attribute \src "libresoc.v:53360.3-53361.35"
- process $proc$libresoc.v:53360$2438
+ attribute \src "libresoc.v:53363.3-53364.35"
+ process $proc$libresoc.v:53363$2439
assign { } { }
assign $0\xive0_pri[7:0] \xive0_pri$next
sync posedge \clk
update \xive0_pri $0\xive0_pri[7:0]
end
- attribute \src "libresoc.v:53362.3-53363.35"
- process $proc$libresoc.v:53362$2439
+ attribute \src "libresoc.v:53365.3-53366.35"
+ process $proc$libresoc.v:53365$2440
assign { } { }
assign $0\xive1_pri[7:0] \xive1_pri$next
sync posedge \clk
update \xive1_pri $0\xive1_pri[7:0]
end
- attribute \src "libresoc.v:53364.3-53365.35"
- process $proc$libresoc.v:53364$2440
+ attribute \src "libresoc.v:53367.3-53368.35"
+ process $proc$libresoc.v:53367$2441
assign { } { }
assign $0\xive2_pri[7:0] \xive2_pri$next
sync posedge \clk
update \xive2_pri $0\xive2_pri[7:0]
end
- attribute \src "libresoc.v:53366.3-53367.35"
- process $proc$libresoc.v:53366$2441
+ attribute \src "libresoc.v:53369.3-53370.35"
+ process $proc$libresoc.v:53369$2442
assign { } { }
assign $0\xive3_pri[7:0] \xive3_pri$next
sync posedge \clk
update \xive3_pri $0\xive3_pri[7:0]
end
- attribute \src "libresoc.v:53368.3-53369.35"
- process $proc$libresoc.v:53368$2442
+ attribute \src "libresoc.v:53371.3-53372.35"
+ process $proc$libresoc.v:53371$2443
assign { } { }
assign $0\xive4_pri[7:0] \xive4_pri$next
sync posedge \clk
update \xive4_pri $0\xive4_pri[7:0]
end
- attribute \src "libresoc.v:53370.3-53371.35"
- process $proc$libresoc.v:53370$2443
+ attribute \src "libresoc.v:53373.3-53374.35"
+ process $proc$libresoc.v:53373$2444
assign { } { }
assign $0\xive5_pri[7:0] \xive5_pri$next
sync posedge \clk
update \xive5_pri $0\xive5_pri[7:0]
end
- attribute \src "libresoc.v:53372.3-53373.35"
- process $proc$libresoc.v:53372$2444
+ attribute \src "libresoc.v:53375.3-53376.35"
+ process $proc$libresoc.v:53375$2445
assign { } { }
assign $0\xive6_pri[7:0] \xive6_pri$next
sync posedge \clk
update \xive6_pri $0\xive6_pri[7:0]
end
- attribute \src "libresoc.v:53374.3-53375.35"
- process $proc$libresoc.v:53374$2445
+ attribute \src "libresoc.v:53377.3-53378.35"
+ process $proc$libresoc.v:53377$2446
assign { } { }
assign $0\xive7_pri[7:0] \xive7_pri$next
sync posedge \clk
update \xive7_pri $0\xive7_pri[7:0]
end
- attribute \src "libresoc.v:53376.3-53377.35"
- process $proc$libresoc.v:53376$2446
+ attribute \src "libresoc.v:53379.3-53380.35"
+ process $proc$libresoc.v:53379$2447
assign { } { }
assign $0\xive8_pri[7:0] \xive8_pri$next
sync posedge \clk
update \xive8_pri $0\xive8_pri[7:0]
end
- attribute \src "libresoc.v:53378.3-53379.35"
- process $proc$libresoc.v:53378$2447
+ attribute \src "libresoc.v:53381.3-53382.35"
+ process $proc$libresoc.v:53381$2448
assign { } { }
assign $0\xive9_pri[7:0] \xive9_pri$next
sync posedge \clk
update \xive9_pri $0\xive9_pri[7:0]
end
- attribute \src "libresoc.v:53380.3-53381.37"
- process $proc$libresoc.v:53380$2448
+ attribute \src "libresoc.v:53383.3-53384.37"
+ process $proc$libresoc.v:53383$2449
assign { } { }
assign $0\xive10_pri[7:0] \xive10_pri$next
sync posedge \clk
update \xive10_pri $0\xive10_pri[7:0]
end
- attribute \src "libresoc.v:53382.3-53467.6"
- process $proc$libresoc.v:53382$2449
+ attribute \src "libresoc.v:53385.3-53470.6"
+ process $proc$libresoc.v:53385$2450
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
assign { } { }
- assign $0\xive0_pri$next[7:0]$2450 $4\xive0_pri$next[7:0]$2514
- assign $0\xive10_pri$next[7:0]$2451 $4\xive10_pri$next[7:0]$2515
- assign $0\xive11_pri$next[7:0]$2452 $4\xive11_pri$next[7:0]$2516
- assign $0\xive12_pri$next[7:0]$2453 $4\xive12_pri$next[7:0]$2517
- assign $0\xive13_pri$next[7:0]$2454 $4\xive13_pri$next[7:0]$2518
- assign $0\xive14_pri$next[7:0]$2455 $4\xive14_pri$next[7:0]$2519
- assign $0\xive15_pri$next[7:0]$2456 $4\xive15_pri$next[7:0]$2520
- assign $0\xive1_pri$next[7:0]$2457 $4\xive1_pri$next[7:0]$2521
- assign $0\xive2_pri$next[7:0]$2458 $4\xive2_pri$next[7:0]$2522
- assign $0\xive3_pri$next[7:0]$2459 $4\xive3_pri$next[7:0]$2523
- assign $0\xive4_pri$next[7:0]$2460 $4\xive4_pri$next[7:0]$2524
- assign $0\xive5_pri$next[7:0]$2461 $4\xive5_pri$next[7:0]$2525
- assign $0\xive6_pri$next[7:0]$2462 $4\xive6_pri$next[7:0]$2526
- assign $0\xive7_pri$next[7:0]$2463 $4\xive7_pri$next[7:0]$2527
- assign $0\xive8_pri$next[7:0]$2464 $4\xive8_pri$next[7:0]$2528
- assign $0\xive9_pri$next[7:0]$2465 $4\xive9_pri$next[7:0]$2529
- attribute \src "libresoc.v:53383.5-53383.29"
+ assign $0\xive0_pri$next[7:0]$2451 $4\xive0_pri$next[7:0]$2515
+ assign $0\xive10_pri$next[7:0]$2452 $4\xive10_pri$next[7:0]$2516
+ assign $0\xive11_pri$next[7:0]$2453 $4\xive11_pri$next[7:0]$2517
+ assign $0\xive12_pri$next[7:0]$2454 $4\xive12_pri$next[7:0]$2518
+ assign $0\xive13_pri$next[7:0]$2455 $4\xive13_pri$next[7:0]$2519
+ assign $0\xive14_pri$next[7:0]$2456 $4\xive14_pri$next[7:0]$2520
+ assign $0\xive15_pri$next[7:0]$2457 $4\xive15_pri$next[7:0]$2521
+ assign $0\xive1_pri$next[7:0]$2458 $4\xive1_pri$next[7:0]$2522
+ assign $0\xive2_pri$next[7:0]$2459 $4\xive2_pri$next[7:0]$2523
+ assign $0\xive3_pri$next[7:0]$2460 $4\xive3_pri$next[7:0]$2524
+ assign $0\xive4_pri$next[7:0]$2461 $4\xive4_pri$next[7:0]$2525
+ assign $0\xive5_pri$next[7:0]$2462 $4\xive5_pri$next[7:0]$2526
+ assign $0\xive6_pri$next[7:0]$2463 $4\xive6_pri$next[7:0]$2527
+ assign $0\xive7_pri$next[7:0]$2464 $4\xive7_pri$next[7:0]$2528
+ assign $0\xive8_pri$next[7:0]$2465 $4\xive8_pri$next[7:0]$2529
+ assign $0\xive9_pri$next[7:0]$2466 $4\xive9_pri$next[7:0]$2530
+ attribute \src "libresoc.v:53386.5-53386.29"
switch \initial
- attribute \src "libresoc.v:53383.9-53383.17"
+ attribute \src "libresoc.v:53386.9-53386.17"
case 1'1
case
end
assign { } { }
assign { } { }
assign { } { }
- assign $1\xive0_pri$next[7:0]$2466 $2\xive0_pri$next[7:0]$2482
- assign $1\xive10_pri$next[7:0]$2467 $2\xive10_pri$next[7:0]$2483
- assign $1\xive11_pri$next[7:0]$2468 $2\xive11_pri$next[7:0]$2484
- assign $1\xive12_pri$next[7:0]$2469 $2\xive12_pri$next[7:0]$2485
- assign $1\xive13_pri$next[7:0]$2470 $2\xive13_pri$next[7:0]$2486
- assign $1\xive14_pri$next[7:0]$2471 $2\xive14_pri$next[7:0]$2487
- assign $1\xive15_pri$next[7:0]$2472 $2\xive15_pri$next[7:0]$2488
- assign $1\xive1_pri$next[7:0]$2473 $2\xive1_pri$next[7:0]$2489
- assign $1\xive2_pri$next[7:0]$2474 $2\xive2_pri$next[7:0]$2490
- assign $1\xive3_pri$next[7:0]$2475 $2\xive3_pri$next[7:0]$2491
- assign $1\xive4_pri$next[7:0]$2476 $2\xive4_pri$next[7:0]$2492
- assign $1\xive5_pri$next[7:0]$2477 $2\xive5_pri$next[7:0]$2493
- assign $1\xive6_pri$next[7:0]$2478 $2\xive6_pri$next[7:0]$2494
- assign $1\xive7_pri$next[7:0]$2479 $2\xive7_pri$next[7:0]$2495
- assign $1\xive8_pri$next[7:0]$2480 $2\xive8_pri$next[7:0]$2496
- assign $1\xive9_pri$next[7:0]$2481 $2\xive9_pri$next[7:0]$2497
+ assign $1\xive0_pri$next[7:0]$2467 $2\xive0_pri$next[7:0]$2483
+ assign $1\xive10_pri$next[7:0]$2468 $2\xive10_pri$next[7:0]$2484
+ assign $1\xive11_pri$next[7:0]$2469 $2\xive11_pri$next[7:0]$2485
+ assign $1\xive12_pri$next[7:0]$2470 $2\xive12_pri$next[7:0]$2486
+ assign $1\xive13_pri$next[7:0]$2471 $2\xive13_pri$next[7:0]$2487
+ assign $1\xive14_pri$next[7:0]$2472 $2\xive14_pri$next[7:0]$2488
+ assign $1\xive15_pri$next[7:0]$2473 $2\xive15_pri$next[7:0]$2489
+ assign $1\xive1_pri$next[7:0]$2474 $2\xive1_pri$next[7:0]$2490
+ assign $1\xive2_pri$next[7:0]$2475 $2\xive2_pri$next[7:0]$2491
+ assign $1\xive3_pri$next[7:0]$2476 $2\xive3_pri$next[7:0]$2492
+ assign $1\xive4_pri$next[7:0]$2477 $2\xive4_pri$next[7:0]$2493
+ assign $1\xive5_pri$next[7:0]$2478 $2\xive5_pri$next[7:0]$2494
+ assign $1\xive6_pri$next[7:0]$2479 $2\xive6_pri$next[7:0]$2495
+ assign $1\xive7_pri$next[7:0]$2480 $2\xive7_pri$next[7:0]$2496
+ assign $1\xive8_pri$next[7:0]$2481 $2\xive8_pri$next[7:0]$2497
+ assign $1\xive9_pri$next[7:0]$2482 $2\xive9_pri$next[7:0]$2498
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342"
switch \reg_is_xive
attribute \src "libresoc.v:0.0-0.0"
assign { } { }
assign { } { }
assign { } { }
- assign $2\xive0_pri$next[7:0]$2482 $3\xive0_pri$next[7:0]$2498
- assign $2\xive10_pri$next[7:0]$2483 $3\xive10_pri$next[7:0]$2499
- assign $2\xive11_pri$next[7:0]$2484 $3\xive11_pri$next[7:0]$2500
- assign $2\xive12_pri$next[7:0]$2485 $3\xive12_pri$next[7:0]$2501
- assign $2\xive13_pri$next[7:0]$2486 $3\xive13_pri$next[7:0]$2502
- assign $2\xive14_pri$next[7:0]$2487 $3\xive14_pri$next[7:0]$2503
- assign $2\xive15_pri$next[7:0]$2488 $3\xive15_pri$next[7:0]$2504
- assign $2\xive1_pri$next[7:0]$2489 $3\xive1_pri$next[7:0]$2505
- assign $2\xive2_pri$next[7:0]$2490 $3\xive2_pri$next[7:0]$2506
- assign $2\xive3_pri$next[7:0]$2491 $3\xive3_pri$next[7:0]$2507
- assign $2\xive4_pri$next[7:0]$2492 $3\xive4_pri$next[7:0]$2508
- assign $2\xive5_pri$next[7:0]$2493 $3\xive5_pri$next[7:0]$2509
- assign $2\xive6_pri$next[7:0]$2494 $3\xive6_pri$next[7:0]$2510
- assign $2\xive7_pri$next[7:0]$2495 $3\xive7_pri$next[7:0]$2511
- assign $2\xive8_pri$next[7:0]$2496 $3\xive8_pri$next[7:0]$2512
- assign $2\xive9_pri$next[7:0]$2497 $3\xive9_pri$next[7:0]$2513
+ assign $2\xive0_pri$next[7:0]$2483 $3\xive0_pri$next[7:0]$2499
+ assign $2\xive10_pri$next[7:0]$2484 $3\xive10_pri$next[7:0]$2500
+ assign $2\xive11_pri$next[7:0]$2485 $3\xive11_pri$next[7:0]$2501
+ assign $2\xive12_pri$next[7:0]$2486 $3\xive12_pri$next[7:0]$2502
+ assign $2\xive13_pri$next[7:0]$2487 $3\xive13_pri$next[7:0]$2503
+ assign $2\xive14_pri$next[7:0]$2488 $3\xive14_pri$next[7:0]$2504
+ assign $2\xive15_pri$next[7:0]$2489 $3\xive15_pri$next[7:0]$2505
+ assign $2\xive1_pri$next[7:0]$2490 $3\xive1_pri$next[7:0]$2506
+ assign $2\xive2_pri$next[7:0]$2491 $3\xive2_pri$next[7:0]$2507
+ assign $2\xive3_pri$next[7:0]$2492 $3\xive3_pri$next[7:0]$2508
+ assign $2\xive4_pri$next[7:0]$2493 $3\xive4_pri$next[7:0]$2509
+ assign $2\xive5_pri$next[7:0]$2494 $3\xive5_pri$next[7:0]$2510
+ assign $2\xive6_pri$next[7:0]$2495 $3\xive6_pri$next[7:0]$2511
+ assign $2\xive7_pri$next[7:0]$2496 $3\xive7_pri$next[7:0]$2512
+ assign $2\xive8_pri$next[7:0]$2497 $3\xive8_pri$next[7:0]$2513
+ assign $2\xive9_pri$next[7:0]$2498 $3\xive9_pri$next[7:0]$2514
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345"
switch \reg_idx
attribute \src "libresoc.v:0.0-0.0"
case 4'0000
assign { } { }
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive0_pri$next[7:0]$2498 \be_in [7:0]
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$2499 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0001
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
assign { } { }
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive1_pri$next[7:0]$2505 \be_in [7:0]
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive1_pri$next[7:0]$2506 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0010
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
assign { } { }
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive2_pri$next[7:0]$2506 \be_in [7:0]
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive2_pri$next[7:0]$2507 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0011
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
assign { } { }
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive3_pri$next[7:0]$2507 \be_in [7:0]
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive3_pri$next[7:0]$2508 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0100
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
assign { } { }
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive4_pri$next[7:0]$2508 \be_in [7:0]
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive4_pri$next[7:0]$2509 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0101
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
assign { } { }
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive5_pri$next[7:0]$2509 \be_in [7:0]
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive5_pri$next[7:0]$2510 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0110
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
assign { } { }
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive6_pri$next[7:0]$2510 \be_in [7:0]
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive6_pri$next[7:0]$2511 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'0111
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
assign { } { }
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive7_pri$next[7:0]$2511 \be_in [7:0]
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive7_pri$next[7:0]$2512 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1000
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive8_pri$next[7:0]$2512 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive8_pri$next[7:0]$2513 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1001
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
assign { } { }
- assign $3\xive9_pri$next[7:0]$2513 \be_in [7:0]
+ assign $3\xive9_pri$next[7:0]$2514 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1010
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
assign { } { }
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive10_pri$next[7:0]$2499 \be_in [7:0]
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive10_pri$next[7:0]$2500 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1011
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
assign { } { }
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive11_pri$next[7:0]$2500 \be_in [7:0]
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive11_pri$next[7:0]$2501 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1100
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
assign { } { }
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive12_pri$next[7:0]$2501 \be_in [7:0]
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive12_pri$next[7:0]$2502 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1101
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
assign { } { }
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive13_pri$next[7:0]$2502 \be_in [7:0]
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive13_pri$next[7:0]$2503 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'1110
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
assign { } { }
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive14_pri$next[7:0]$2503 \be_in [7:0]
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive14_pri$next[7:0]$2504 \be_in [7:0]
attribute \src "libresoc.v:0.0-0.0"
case 4'----
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
assign { } { }
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
- assign $3\xive15_pri$next[7:0]$2504 \be_in [7:0]
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
+ assign $3\xive15_pri$next[7:0]$2505 \be_in [7:0]
case
- assign $3\xive0_pri$next[7:0]$2498 \xive0_pri
- assign $3\xive10_pri$next[7:0]$2499 \xive10_pri
- assign $3\xive11_pri$next[7:0]$2500 \xive11_pri
- assign $3\xive12_pri$next[7:0]$2501 \xive12_pri
- assign $3\xive13_pri$next[7:0]$2502 \xive13_pri
- assign $3\xive14_pri$next[7:0]$2503 \xive14_pri
- assign $3\xive15_pri$next[7:0]$2504 \xive15_pri
- assign $3\xive1_pri$next[7:0]$2505 \xive1_pri
- assign $3\xive2_pri$next[7:0]$2506 \xive2_pri
- assign $3\xive3_pri$next[7:0]$2507 \xive3_pri
- assign $3\xive4_pri$next[7:0]$2508 \xive4_pri
- assign $3\xive5_pri$next[7:0]$2509 \xive5_pri
- assign $3\xive6_pri$next[7:0]$2510 \xive6_pri
- assign $3\xive7_pri$next[7:0]$2511 \xive7_pri
- assign $3\xive8_pri$next[7:0]$2512 \xive8_pri
- assign $3\xive9_pri$next[7:0]$2513 \xive9_pri
+ assign $3\xive0_pri$next[7:0]$2499 \xive0_pri
+ assign $3\xive10_pri$next[7:0]$2500 \xive10_pri
+ assign $3\xive11_pri$next[7:0]$2501 \xive11_pri
+ assign $3\xive12_pri$next[7:0]$2502 \xive12_pri
+ assign $3\xive13_pri$next[7:0]$2503 \xive13_pri
+ assign $3\xive14_pri$next[7:0]$2504 \xive14_pri
+ assign $3\xive15_pri$next[7:0]$2505 \xive15_pri
+ assign $3\xive1_pri$next[7:0]$2506 \xive1_pri
+ assign $3\xive2_pri$next[7:0]$2507 \xive2_pri
+ assign $3\xive3_pri$next[7:0]$2508 \xive3_pri
+ assign $3\xive4_pri$next[7:0]$2509 \xive4_pri
+ assign $3\xive5_pri$next[7:0]$2510 \xive5_pri
+ assign $3\xive6_pri$next[7:0]$2511 \xive6_pri
+ assign $3\xive7_pri$next[7:0]$2512 \xive7_pri
+ assign $3\xive8_pri$next[7:0]$2513 \xive8_pri
+ assign $3\xive9_pri$next[7:0]$2514 \xive9_pri
end
case
- assign $2\xive0_pri$next[7:0]$2482 \xive0_pri
- assign $2\xive10_pri$next[7:0]$2483 \xive10_pri
- assign $2\xive11_pri$next[7:0]$2484 \xive11_pri
- assign $2\xive12_pri$next[7:0]$2485 \xive12_pri
- assign $2\xive13_pri$next[7:0]$2486 \xive13_pri
- assign $2\xive14_pri$next[7:0]$2487 \xive14_pri
- assign $2\xive15_pri$next[7:0]$2488 \xive15_pri
- assign $2\xive1_pri$next[7:0]$2489 \xive1_pri
- assign $2\xive2_pri$next[7:0]$2490 \xive2_pri
- assign $2\xive3_pri$next[7:0]$2491 \xive3_pri
- assign $2\xive4_pri$next[7:0]$2492 \xive4_pri
- assign $2\xive5_pri$next[7:0]$2493 \xive5_pri
- assign $2\xive6_pri$next[7:0]$2494 \xive6_pri
- assign $2\xive7_pri$next[7:0]$2495 \xive7_pri
- assign $2\xive8_pri$next[7:0]$2496 \xive8_pri
- assign $2\xive9_pri$next[7:0]$2497 \xive9_pri
+ assign $2\xive0_pri$next[7:0]$2483 \xive0_pri
+ assign $2\xive10_pri$next[7:0]$2484 \xive10_pri
+ assign $2\xive11_pri$next[7:0]$2485 \xive11_pri
+ assign $2\xive12_pri$next[7:0]$2486 \xive12_pri
+ assign $2\xive13_pri$next[7:0]$2487 \xive13_pri
+ assign $2\xive14_pri$next[7:0]$2488 \xive14_pri
+ assign $2\xive15_pri$next[7:0]$2489 \xive15_pri
+ assign $2\xive1_pri$next[7:0]$2490 \xive1_pri
+ assign $2\xive2_pri$next[7:0]$2491 \xive2_pri
+ assign $2\xive3_pri$next[7:0]$2492 \xive3_pri
+ assign $2\xive4_pri$next[7:0]$2493 \xive4_pri
+ assign $2\xive5_pri$next[7:0]$2494 \xive5_pri
+ assign $2\xive6_pri$next[7:0]$2495 \xive6_pri
+ assign $2\xive7_pri$next[7:0]$2496 \xive7_pri
+ assign $2\xive8_pri$next[7:0]$2497 \xive8_pri
+ assign $2\xive9_pri$next[7:0]$2498 \xive9_pri
end
case
- assign $1\xive0_pri$next[7:0]$2466 \xive0_pri
- assign $1\xive10_pri$next[7:0]$2467 \xive10_pri
- assign $1\xive11_pri$next[7:0]$2468 \xive11_pri
- assign $1\xive12_pri$next[7:0]$2469 \xive12_pri
- assign $1\xive13_pri$next[7:0]$2470 \xive13_pri
- assign $1\xive14_pri$next[7:0]$2471 \xive14_pri
- assign $1\xive15_pri$next[7:0]$2472 \xive15_pri
- assign $1\xive1_pri$next[7:0]$2473 \xive1_pri
- assign $1\xive2_pri$next[7:0]$2474 \xive2_pri
- assign $1\xive3_pri$next[7:0]$2475 \xive3_pri
- assign $1\xive4_pri$next[7:0]$2476 \xive4_pri
- assign $1\xive5_pri$next[7:0]$2477 \xive5_pri
- assign $1\xive6_pri$next[7:0]$2478 \xive6_pri
- assign $1\xive7_pri$next[7:0]$2479 \xive7_pri
- assign $1\xive8_pri$next[7:0]$2480 \xive8_pri
- assign $1\xive9_pri$next[7:0]$2481 \xive9_pri
+ assign $1\xive0_pri$next[7:0]$2467 \xive0_pri
+ assign $1\xive10_pri$next[7:0]$2468 \xive10_pri
+ assign $1\xive11_pri$next[7:0]$2469 \xive11_pri
+ assign $1\xive12_pri$next[7:0]$2470 \xive12_pri
+ assign $1\xive13_pri$next[7:0]$2471 \xive13_pri
+ assign $1\xive14_pri$next[7:0]$2472 \xive14_pri
+ assign $1\xive15_pri$next[7:0]$2473 \xive15_pri
+ assign $1\xive1_pri$next[7:0]$2474 \xive1_pri
+ assign $1\xive2_pri$next[7:0]$2475 \xive2_pri
+ assign $1\xive3_pri$next[7:0]$2476 \xive3_pri
+ assign $1\xive4_pri$next[7:0]$2477 \xive4_pri
+ assign $1\xive5_pri$next[7:0]$2478 \xive5_pri
+ assign $1\xive6_pri$next[7:0]$2479 \xive6_pri
+ assign $1\xive7_pri$next[7:0]$2480 \xive7_pri
+ assign $1\xive8_pri$next[7:0]$2481 \xive8_pri
+ assign $1\xive9_pri$next[7:0]$2482 \xive9_pri
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532"
switch \rst
assign { } { }
assign { } { }
assign { } { }
- assign $4\xive0_pri$next[7:0]$2514 8'11111111
- assign $4\xive1_pri$next[7:0]$2521 8'11111111
- assign $4\xive2_pri$next[7:0]$2522 8'11111111
- assign $4\xive3_pri$next[7:0]$2523 8'11111111
- assign $4\xive4_pri$next[7:0]$2524 8'11111111
- assign $4\xive5_pri$next[7:0]$2525 8'11111111
- assign $4\xive6_pri$next[7:0]$2526 8'11111111
- assign $4\xive7_pri$next[7:0]$2527 8'11111111
- assign $4\xive8_pri$next[7:0]$2528 8'11111111
- assign $4\xive9_pri$next[7:0]$2529 8'11111111
- assign $4\xive10_pri$next[7:0]$2515 8'11111111
- assign $4\xive11_pri$next[7:0]$2516 8'11111111
- assign $4\xive12_pri$next[7:0]$2517 8'11111111
- assign $4\xive13_pri$next[7:0]$2518 8'11111111
- assign $4\xive14_pri$next[7:0]$2519 8'11111111
- assign $4\xive15_pri$next[7:0]$2520 8'11111111
+ assign $4\xive0_pri$next[7:0]$2515 8'11111111
+ assign $4\xive1_pri$next[7:0]$2522 8'11111111
+ assign $4\xive2_pri$next[7:0]$2523 8'11111111
+ assign $4\xive3_pri$next[7:0]$2524 8'11111111
+ assign $4\xive4_pri$next[7:0]$2525 8'11111111
+ assign $4\xive5_pri$next[7:0]$2526 8'11111111
+ assign $4\xive6_pri$next[7:0]$2527 8'11111111
+ assign $4\xive7_pri$next[7:0]$2528 8'11111111
+ assign $4\xive8_pri$next[7:0]$2529 8'11111111
+ assign $4\xive9_pri$next[7:0]$2530 8'11111111
+ assign $4\xive10_pri$next[7:0]$2516 8'11111111
+ assign $4\xive11_pri$next[7:0]$2517 8'11111111
+ assign $4\xive12_pri$next[7:0]$2518 8'11111111
+ assign $4\xive13_pri$next[7:0]$2519 8'11111111
+ assign $4\xive14_pri$next[7:0]$2520 8'11111111
+ assign $4\xive15_pri$next[7:0]$2521 8'11111111
case
- assign $4\xive0_pri$next[7:0]$2514 $1\xive0_pri$next[7:0]$2466
- assign $4\xive10_pri$next[7:0]$2515 $1\xive10_pri$next[7:0]$2467
- assign $4\xive11_pri$next[7:0]$2516 $1\xive11_pri$next[7:0]$2468
- assign $4\xive12_pri$next[7:0]$2517 $1\xive12_pri$next[7:0]$2469
- assign $4\xive13_pri$next[7:0]$2518 $1\xive13_pri$next[7:0]$2470
- assign $4\xive14_pri$next[7:0]$2519 $1\xive14_pri$next[7:0]$2471
- assign $4\xive15_pri$next[7:0]$2520 $1\xive15_pri$next[7:0]$2472
- assign $4\xive1_pri$next[7:0]$2521 $1\xive1_pri$next[7:0]$2473
- assign $4\xive2_pri$next[7:0]$2522 $1\xive2_pri$next[7:0]$2474
- assign $4\xive3_pri$next[7:0]$2523 $1\xive3_pri$next[7:0]$2475
- assign $4\xive4_pri$next[7:0]$2524 $1\xive4_pri$next[7:0]$2476
- assign $4\xive5_pri$next[7:0]$2525 $1\xive5_pri$next[7:0]$2477
- assign $4\xive6_pri$next[7:0]$2526 $1\xive6_pri$next[7:0]$2478
- assign $4\xive7_pri$next[7:0]$2527 $1\xive7_pri$next[7:0]$2479
- assign $4\xive8_pri$next[7:0]$2528 $1\xive8_pri$next[7:0]$2480
- assign $4\xive9_pri$next[7:0]$2529 $1\xive9_pri$next[7:0]$2481
+ assign $4\xive0_pri$next[7:0]$2515 $1\xive0_pri$next[7:0]$2467
+ assign $4\xive10_pri$next[7:0]$2516 $1\xive10_pri$next[7:0]$2468
+ assign $4\xive11_pri$next[7:0]$2517 $1\xive11_pri$next[7:0]$2469
+ assign $4\xive12_pri$next[7:0]$2518 $1\xive12_pri$next[7:0]$2470
+ assign $4\xive13_pri$next[7:0]$2519 $1\xive13_pri$next[7:0]$2471
+ assign $4\xive14_pri$next[7:0]$2520 $1\xive14_pri$next[7:0]$2472
+ assign $4\xive15_pri$next[7:0]$2521 $1\xive15_pri$next[7:0]$2473
+ assign $4\xive1_pri$next[7:0]$2522 $1\xive1_pri$next[7:0]$2474
+ assign $4\xive2_pri$next[7:0]$2523 $1\xive2_pri$next[7:0]$2475
+ assign $4\xive3_pri$next[7:0]$2524 $1\xive3_pri$next[7:0]$2476
+ assign $4\xive4_pri$next[7:0]$2525 $1\xive4_pri$next[7:0]$2477
+ assign $4\xive5_pri$next[7:0]$2526 $1\xive5_pri$next[7:0]$2478
+ assign $4\xive6_pri$next[7:0]$2527 $1\xive6_pri$next[7:0]$2479
+ assign $4\xive7_pri$next[7:0]$2528 $1\xive7_pri$next[7:0]$2480
+ assign $4\xive8_pri$next[7:0]$2529 $1\xive8_pri$next[7:0]$2481
+ assign $4\xive9_pri$next[7:0]$2530 $1\xive9_pri$next[7:0]$2482
end
sync always
- update \xive0_pri$next $0\xive0_pri$next[7:0]$2450
- update \xive10_pri$next $0\xive10_pri$next[7:0]$2451
- update \xive11_pri$next $0\xive11_pri$next[7:0]$2452
- update \xive12_pri$next $0\xive12_pri$next[7:0]$2453
- update \xive13_pri$next $0\xive13_pri$next[7:0]$2454
- update \xive14_pri$next $0\xive14_pri$next[7:0]$2455
- update \xive15_pri$next $0\xive15_pri$next[7:0]$2456
- update \xive1_pri$next $0\xive1_pri$next[7:0]$2457
- update \xive2_pri$next $0\xive2_pri$next[7:0]$2458
- update \xive3_pri$next $0\xive3_pri$next[7:0]$2459
- update \xive4_pri$next $0\xive4_pri$next[7:0]$2460
- update \xive5_pri$next $0\xive5_pri$next[7:0]$2461
- update \xive6_pri$next $0\xive6_pri$next[7:0]$2462
- update \xive7_pri$next $0\xive7_pri$next[7:0]$2463
- update \xive8_pri$next $0\xive8_pri$next[7:0]$2464
- update \xive9_pri$next $0\xive9_pri$next[7:0]$2465
+ update \xive0_pri$next $0\xive0_pri$next[7:0]$2451
+ update \xive10_pri$next $0\xive10_pri$next[7:0]$2452
+ update \xive11_pri$next $0\xive11_pri$next[7:0]$2453
+ update \xive12_pri$next $0\xive12_pri$next[7:0]$2454
+ update \xive13_pri$next $0\xive13_pri$next[7:0]$2455
+ update \xive14_pri$next $0\xive14_pri$next[7:0]$2456
+ update \xive15_pri$next $0\xive15_pri$next[7:0]$2457
+ update \xive1_pri$next $0\xive1_pri$next[7:0]$2458
+ update \xive2_pri$next $0\xive2_pri$next[7:0]$2459
+ update \xive3_pri$next $0\xive3_pri$next[7:0]$2460
+ update \xive4_pri$next $0\xive4_pri$next[7:0]$2461
+ update \xive5_pri$next $0\xive5_pri$next[7:0]$2462
+ update \xive6_pri$next $0\xive6_pri$next[7:0]$2463
+ update \xive7_pri$next $0\xive7_pri$next[7:0]$2464
+ update \xive8_pri$next $0\xive8_pri$next[7:0]$2465
+ update \xive9_pri$next $0\xive9_pri$next[7:0]$2466
end
- attribute \src "libresoc.v:53468.3-53477.6"
- process $proc$libresoc.v:53468$2530
+ attribute \src "libresoc.v:53471.3-53480.6"
+ process $proc$libresoc.v:53471$2531
assign { } { }
assign { } { }
assign $0\cur_pri0[7:0] $1\cur_pri0[7:0]
- attribute \src "libresoc.v:53469.5-53469.29"
+ attribute \src "libresoc.v:53472.5-53472.29"
switch \initial
- attribute \src "libresoc.v:53469.9-53469.17"
+ attribute \src "libresoc.v:53472.9-53472.17"
case 1'1
case
end
sync always
update \cur_pri0 $0\cur_pri0[7:0]
end
- attribute \src "libresoc.v:53478.3-53487.6"
- process $proc$libresoc.v:53478$2531
+ attribute \src "libresoc.v:53481.3-53490.6"
+ process $proc$libresoc.v:53481$2532
assign { } { }
assign { } { }
assign $0\cur_idx0[3:0] $1\cur_idx0[3:0]
- attribute \src "libresoc.v:53479.5-53479.29"
+ attribute \src "libresoc.v:53482.5-53482.29"
switch \initial
- attribute \src "libresoc.v:53479.9-53479.17"
+ attribute \src "libresoc.v:53482.9-53482.17"
case 1'1
case
end
sync always
update \cur_idx0 $0\cur_idx0[3:0]
end
- attribute \src "libresoc.v:53488.3-53497.6"
- process $proc$libresoc.v:53488$2532
+ attribute \src "libresoc.v:53491.3-53500.6"
+ process $proc$libresoc.v:53491$2533
assign { } { }
assign { } { }
assign $0\cur_pri1[7:0] $1\cur_pri1[7:0]
- attribute \src "libresoc.v:53489.5-53489.29"
+ attribute \src "libresoc.v:53492.5-53492.29"
switch \initial
- attribute \src "libresoc.v:53489.9-53489.17"
+ attribute \src "libresoc.v:53492.9-53492.17"
case 1'1
case
end
sync always
update \cur_pri1 $0\cur_pri1[7:0]
end
- attribute \src "libresoc.v:53498.3-53507.6"
- process $proc$libresoc.v:53498$2533
+ attribute \src "libresoc.v:53501.3-53510.6"
+ process $proc$libresoc.v:53501$2534
assign { } { }
assign { } { }
assign $0\cur_idx1[3:0] $1\cur_idx1[3:0]
- attribute \src "libresoc.v:53499.5-53499.29"
+ attribute \src "libresoc.v:53502.5-53502.29"
switch \initial
- attribute \src "libresoc.v:53499.9-53499.17"
+ attribute \src "libresoc.v:53502.9-53502.17"
case 1'1
case
end
sync always
update \cur_idx1 $0\cur_idx1[3:0]
end
- attribute \src "libresoc.v:53508.3-53517.6"
- process $proc$libresoc.v:53508$2534
+ attribute \src "libresoc.v:53511.3-53520.6"
+ process $proc$libresoc.v:53511$2535
assign { } { }
assign { } { }
assign $0\cur_pri2[7:0] $1\cur_pri2[7:0]
- attribute \src "libresoc.v:53509.5-53509.29"
+ attribute \src "libresoc.v:53512.5-53512.29"
switch \initial
- attribute \src "libresoc.v:53509.9-53509.17"
+ attribute \src "libresoc.v:53512.9-53512.17"
case 1'1
case
end
sync always
update \cur_pri2 $0\cur_pri2[7:0]
end
- attribute \src "libresoc.v:53518.3-53527.6"
- process $proc$libresoc.v:53518$2535
+ attribute \src "libresoc.v:53521.3-53530.6"
+ process $proc$libresoc.v:53521$2536
assign { } { }
assign { } { }
assign $0\cur_idx2[3:0] $1\cur_idx2[3:0]
- attribute \src "libresoc.v:53519.5-53519.29"
+ attribute \src "libresoc.v:53522.5-53522.29"
switch \initial
- attribute \src "libresoc.v:53519.9-53519.17"
+ attribute \src "libresoc.v:53522.9-53522.17"
case 1'1
case
end
sync always
update \cur_idx2 $0\cur_idx2[3:0]
end
- attribute \src "libresoc.v:53528.3-53537.6"
- process $proc$libresoc.v:53528$2536
+ attribute \src "libresoc.v:53531.3-53540.6"
+ process $proc$libresoc.v:53531$2537
assign { } { }
assign { } { }
assign $0\cur_pri3[7:0] $1\cur_pri3[7:0]
- attribute \src "libresoc.v:53529.5-53529.29"
+ attribute \src "libresoc.v:53532.5-53532.29"
switch \initial
- attribute \src "libresoc.v:53529.9-53529.17"
+ attribute \src "libresoc.v:53532.9-53532.17"
case 1'1
case
end
sync always
update \cur_pri3 $0\cur_pri3[7:0]
end
- attribute \src "libresoc.v:53538.3-53547.6"
- process $proc$libresoc.v:53538$2537
+ attribute \src "libresoc.v:53541.3-53550.6"
+ process $proc$libresoc.v:53541$2538
assign { } { }
assign { } { }
assign $0\cur_idx3[3:0] $1\cur_idx3[3:0]
- attribute \src "libresoc.v:53539.5-53539.29"
+ attribute \src "libresoc.v:53542.5-53542.29"
switch \initial
- attribute \src "libresoc.v:53539.9-53539.17"
+ attribute \src "libresoc.v:53542.9-53542.17"
case 1'1
case
end
sync always
update \cur_idx3 $0\cur_idx3[3:0]
end
- attribute \src "libresoc.v:53548.3-53557.6"
- process $proc$libresoc.v:53548$2538
+ attribute \src "libresoc.v:53551.3-53560.6"
+ process $proc$libresoc.v:53551$2539
assign { } { }
assign { } { }
assign $0\cur_pri4[7:0] $1\cur_pri4[7:0]
- attribute \src "libresoc.v:53549.5-53549.29"
+ attribute \src "libresoc.v:53552.5-53552.29"
switch \initial
- attribute \src "libresoc.v:53549.9-53549.17"
+ attribute \src "libresoc.v:53552.9-53552.17"
case 1'1
case
end
sync always
update \cur_pri4 $0\cur_pri4[7:0]
end
- attribute \src "libresoc.v:53558.3-53566.6"
- process $proc$libresoc.v:53558$2539
+ attribute \src "libresoc.v:53561.3-53569.6"
+ process $proc$libresoc.v:53561$2540
assign { } { }
assign { } { }
- assign $0\int_level_l$next[15:0]$2540 $1\int_level_l$next[15:0]$2541
- attribute \src "libresoc.v:53559.5-53559.29"
+ assign $0\int_level_l$next[15:0]$2541 $1\int_level_l$next[15:0]$2542
+ attribute \src "libresoc.v:53562.5-53562.29"
switch \initial
- attribute \src "libresoc.v:53559.9-53559.17"
+ attribute \src "libresoc.v:53562.9-53562.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\int_level_l$next[15:0]$2541 16'0000000000000000
+ assign $1\int_level_l$next[15:0]$2542 16'0000000000000000
case
- assign $1\int_level_l$next[15:0]$2541 \int_level_i
+ assign $1\int_level_l$next[15:0]$2542 \int_level_i
end
sync always
- update \int_level_l$next $0\int_level_l$next[15:0]$2540
+ update \int_level_l$next $0\int_level_l$next[15:0]$2541
end
- attribute \src "libresoc.v:53567.3-53576.6"
- process $proc$libresoc.v:53567$2542
+ attribute \src "libresoc.v:53570.3-53579.6"
+ process $proc$libresoc.v:53570$2543
assign { } { }
assign { } { }
assign $0\cur_idx4[3:0] $1\cur_idx4[3:0]
- attribute \src "libresoc.v:53568.5-53568.29"
+ attribute \src "libresoc.v:53571.5-53571.29"
switch \initial
- attribute \src "libresoc.v:53568.9-53568.17"
+ attribute \src "libresoc.v:53571.9-53571.17"
case 1'1
case
end
sync always
update \cur_idx4 $0\cur_idx4[3:0]
end
- attribute \src "libresoc.v:53577.3-53586.6"
- process $proc$libresoc.v:53577$2543
+ attribute \src "libresoc.v:53580.3-53589.6"
+ process $proc$libresoc.v:53580$2544
assign { } { }
assign { } { }
assign $0\cur_pri5[7:0] $1\cur_pri5[7:0]
- attribute \src "libresoc.v:53578.5-53578.29"
+ attribute \src "libresoc.v:53581.5-53581.29"
switch \initial
- attribute \src "libresoc.v:53578.9-53578.17"
+ attribute \src "libresoc.v:53581.9-53581.17"
case 1'1
case
end
sync always
update \cur_pri5 $0\cur_pri5[7:0]
end
- attribute \src "libresoc.v:53587.3-53596.6"
- process $proc$libresoc.v:53587$2544
+ attribute \src "libresoc.v:53590.3-53599.6"
+ process $proc$libresoc.v:53590$2545
assign { } { }
assign { } { }
assign $0\cur_idx5[3:0] $1\cur_idx5[3:0]
- attribute \src "libresoc.v:53588.5-53588.29"
+ attribute \src "libresoc.v:53591.5-53591.29"
switch \initial
- attribute \src "libresoc.v:53588.9-53588.17"
+ attribute \src "libresoc.v:53591.9-53591.17"
case 1'1
case
end
sync always
update \cur_idx5 $0\cur_idx5[3:0]
end
- attribute \src "libresoc.v:53597.3-53606.6"
- process $proc$libresoc.v:53597$2545
+ attribute \src "libresoc.v:53600.3-53609.6"
+ process $proc$libresoc.v:53600$2546
assign { } { }
assign { } { }
assign $0\cur_pri6[7:0] $1\cur_pri6[7:0]
- attribute \src "libresoc.v:53598.5-53598.29"
+ attribute \src "libresoc.v:53601.5-53601.29"
switch \initial
- attribute \src "libresoc.v:53598.9-53598.17"
+ attribute \src "libresoc.v:53601.9-53601.17"
case 1'1
case
end
sync always
update \cur_pri6 $0\cur_pri6[7:0]
end
- attribute \src "libresoc.v:53607.3-53616.6"
- process $proc$libresoc.v:53607$2546
+ attribute \src "libresoc.v:53610.3-53619.6"
+ process $proc$libresoc.v:53610$2547
assign { } { }
assign { } { }
assign $0\cur_idx6[3:0] $1\cur_idx6[3:0]
- attribute \src "libresoc.v:53608.5-53608.29"
+ attribute \src "libresoc.v:53611.5-53611.29"
switch \initial
- attribute \src "libresoc.v:53608.9-53608.17"
+ attribute \src "libresoc.v:53611.9-53611.17"
case 1'1
case
end
sync always
update \cur_idx6 $0\cur_idx6[3:0]
end
- attribute \src "libresoc.v:53617.3-53626.6"
- process $proc$libresoc.v:53617$2547
+ attribute \src "libresoc.v:53620.3-53629.6"
+ process $proc$libresoc.v:53620$2548
assign { } { }
assign { } { }
assign $0\cur_pri7[7:0] $1\cur_pri7[7:0]
- attribute \src "libresoc.v:53618.5-53618.29"
+ attribute \src "libresoc.v:53621.5-53621.29"
switch \initial
- attribute \src "libresoc.v:53618.9-53618.17"
+ attribute \src "libresoc.v:53621.9-53621.17"
case 1'1
case
end
sync always
update \cur_pri7 $0\cur_pri7[7:0]
end
- attribute \src "libresoc.v:53627.3-53636.6"
- process $proc$libresoc.v:53627$2548
+ attribute \src "libresoc.v:53630.3-53639.6"
+ process $proc$libresoc.v:53630$2549
assign { } { }
assign { } { }
assign $0\cur_idx7[3:0] $1\cur_idx7[3:0]
- attribute \src "libresoc.v:53628.5-53628.29"
+ attribute \src "libresoc.v:53631.5-53631.29"
switch \initial
- attribute \src "libresoc.v:53628.9-53628.17"
+ attribute \src "libresoc.v:53631.9-53631.17"
case 1'1
case
end
sync always
update \cur_idx7 $0\cur_idx7[3:0]
end
- attribute \src "libresoc.v:53637.3-53646.6"
- process $proc$libresoc.v:53637$2549
+ attribute \src "libresoc.v:53640.3-53649.6"
+ process $proc$libresoc.v:53640$2550
assign { } { }
assign { } { }
assign $0\cur_pri8[7:0] $1\cur_pri8[7:0]
- attribute \src "libresoc.v:53638.5-53638.29"
+ attribute \src "libresoc.v:53641.5-53641.29"
switch \initial
- attribute \src "libresoc.v:53638.9-53638.17"
+ attribute \src "libresoc.v:53641.9-53641.17"
case 1'1
case
end
sync always
update \cur_pri8 $0\cur_pri8[7:0]
end
- attribute \src "libresoc.v:53647.3-53656.6"
- process $proc$libresoc.v:53647$2550
+ attribute \src "libresoc.v:53650.3-53659.6"
+ process $proc$libresoc.v:53650$2551
assign { } { }
assign { } { }
assign $0\cur_idx8[3:0] $1\cur_idx8[3:0]
- attribute \src "libresoc.v:53648.5-53648.29"
+ attribute \src "libresoc.v:53651.5-53651.29"
switch \initial
- attribute \src "libresoc.v:53648.9-53648.17"
+ attribute \src "libresoc.v:53651.9-53651.17"
case 1'1
case
end
sync always
update \cur_idx8 $0\cur_idx8[3:0]
end
- attribute \src "libresoc.v:53657.3-53666.6"
- process $proc$libresoc.v:53657$2551
+ attribute \src "libresoc.v:53660.3-53669.6"
+ process $proc$libresoc.v:53660$2552
assign { } { }
assign { } { }
assign $0\cur_pri9[7:0] $1\cur_pri9[7:0]
- attribute \src "libresoc.v:53658.5-53658.29"
+ attribute \src "libresoc.v:53661.5-53661.29"
switch \initial
- attribute \src "libresoc.v:53658.9-53658.17"
+ attribute \src "libresoc.v:53661.9-53661.17"
case 1'1
case
end
sync always
update \cur_pri9 $0\cur_pri9[7:0]
end
- attribute \src "libresoc.v:53667.3-53676.6"
- process $proc$libresoc.v:53667$2552
+ attribute \src "libresoc.v:53670.3-53679.6"
+ process $proc$libresoc.v:53670$2553
assign { } { }
assign { } { }
assign $0\cur_idx9[3:0] $1\cur_idx9[3:0]
- attribute \src "libresoc.v:53668.5-53668.29"
+ attribute \src "libresoc.v:53671.5-53671.29"
switch \initial
- attribute \src "libresoc.v:53668.9-53668.17"
+ attribute \src "libresoc.v:53671.9-53671.17"
case 1'1
case
end
sync always
update \cur_idx9 $0\cur_idx9[3:0]
end
- attribute \src "libresoc.v:53677.3-53686.6"
- process $proc$libresoc.v:53677$2553
+ attribute \src "libresoc.v:53680.3-53689.6"
+ process $proc$libresoc.v:53680$2554
assign { } { }
assign { } { }
assign $0\cur_pri10[7:0] $1\cur_pri10[7:0]
- attribute \src "libresoc.v:53678.5-53678.29"
+ attribute \src "libresoc.v:53681.5-53681.29"
switch \initial
- attribute \src "libresoc.v:53678.9-53678.17"
+ attribute \src "libresoc.v:53681.9-53681.17"
case 1'1
case
end
sync always
update \cur_pri10 $0\cur_pri10[7:0]
end
- attribute \src "libresoc.v:53687.3-53696.6"
- process $proc$libresoc.v:53687$2554
+ attribute \src "libresoc.v:53690.3-53699.6"
+ process $proc$libresoc.v:53690$2555
assign { } { }
assign { } { }
assign $0\cur_idx10[3:0] $1\cur_idx10[3:0]
- attribute \src "libresoc.v:53688.5-53688.29"
+ attribute \src "libresoc.v:53691.5-53691.29"
switch \initial
- attribute \src "libresoc.v:53688.9-53688.17"
+ attribute \src "libresoc.v:53691.9-53691.17"
case 1'1
case
end
sync always
update \cur_idx10 $0\cur_idx10[3:0]
end
- attribute \src "libresoc.v:53697.3-53706.6"
- process $proc$libresoc.v:53697$2555
+ attribute \src "libresoc.v:53700.3-53709.6"
+ process $proc$libresoc.v:53700$2556
assign { } { }
assign { } { }
assign $0\cur_pri11[7:0] $1\cur_pri11[7:0]
- attribute \src "libresoc.v:53698.5-53698.29"
+ attribute \src "libresoc.v:53701.5-53701.29"
switch \initial
- attribute \src "libresoc.v:53698.9-53698.17"
+ attribute \src "libresoc.v:53701.9-53701.17"
case 1'1
case
end
sync always
update \cur_pri11 $0\cur_pri11[7:0]
end
- attribute \src "libresoc.v:53707.3-53716.6"
- process $proc$libresoc.v:53707$2556
+ attribute \src "libresoc.v:53710.3-53719.6"
+ process $proc$libresoc.v:53710$2557
assign { } { }
assign { } { }
assign $0\cur_idx11[3:0] $1\cur_idx11[3:0]
- attribute \src "libresoc.v:53708.5-53708.29"
+ attribute \src "libresoc.v:53711.5-53711.29"
switch \initial
- attribute \src "libresoc.v:53708.9-53708.17"
+ attribute \src "libresoc.v:53711.9-53711.17"
case 1'1
case
end
sync always
update \cur_idx11 $0\cur_idx11[3:0]
end
- attribute \src "libresoc.v:53717.3-53726.6"
- process $proc$libresoc.v:53717$2557
+ attribute \src "libresoc.v:53720.3-53729.6"
+ process $proc$libresoc.v:53720$2558
assign { } { }
assign { } { }
assign $0\cur_pri12[7:0] $1\cur_pri12[7:0]
- attribute \src "libresoc.v:53718.5-53718.29"
+ attribute \src "libresoc.v:53721.5-53721.29"
switch \initial
- attribute \src "libresoc.v:53718.9-53718.17"
+ attribute \src "libresoc.v:53721.9-53721.17"
case 1'1
case
end
sync always
update \cur_pri12 $0\cur_pri12[7:0]
end
- attribute \src "libresoc.v:53727.3-53736.6"
- process $proc$libresoc.v:53727$2558
+ attribute \src "libresoc.v:53730.3-53739.6"
+ process $proc$libresoc.v:53730$2559
assign { } { }
assign { } { }
assign $0\cur_idx12[3:0] $1\cur_idx12[3:0]
- attribute \src "libresoc.v:53728.5-53728.29"
+ attribute \src "libresoc.v:53731.5-53731.29"
switch \initial
- attribute \src "libresoc.v:53728.9-53728.17"
+ attribute \src "libresoc.v:53731.9-53731.17"
case 1'1
case
end
sync always
update \cur_idx12 $0\cur_idx12[3:0]
end
- attribute \src "libresoc.v:53737.3-53746.6"
- process $proc$libresoc.v:53737$2559
+ attribute \src "libresoc.v:53740.3-53749.6"
+ process $proc$libresoc.v:53740$2560
assign { } { }
assign { } { }
assign $0\cur_pri13[7:0] $1\cur_pri13[7:0]
- attribute \src "libresoc.v:53738.5-53738.29"
+ attribute \src "libresoc.v:53741.5-53741.29"
switch \initial
- attribute \src "libresoc.v:53738.9-53738.17"
+ attribute \src "libresoc.v:53741.9-53741.17"
case 1'1
case
end
sync always
update \cur_pri13 $0\cur_pri13[7:0]
end
- attribute \src "libresoc.v:53747.3-53756.6"
- process $proc$libresoc.v:53747$2560
+ attribute \src "libresoc.v:53750.3-53759.6"
+ process $proc$libresoc.v:53750$2561
assign { } { }
assign { } { }
assign $0\cur_idx13[3:0] $1\cur_idx13[3:0]
- attribute \src "libresoc.v:53748.5-53748.29"
+ attribute \src "libresoc.v:53751.5-53751.29"
switch \initial
- attribute \src "libresoc.v:53748.9-53748.17"
+ attribute \src "libresoc.v:53751.9-53751.17"
case 1'1
case
end
sync always
update \cur_idx13 $0\cur_idx13[3:0]
end
- attribute \src "libresoc.v:53757.3-53766.6"
- process $proc$libresoc.v:53757$2561
+ attribute \src "libresoc.v:53760.3-53769.6"
+ process $proc$libresoc.v:53760$2562
assign { } { }
assign { } { }
assign $0\cur_pri14[7:0] $1\cur_pri14[7:0]
- attribute \src "libresoc.v:53758.5-53758.29"
+ attribute \src "libresoc.v:53761.5-53761.29"
switch \initial
- attribute \src "libresoc.v:53758.9-53758.17"
+ attribute \src "libresoc.v:53761.9-53761.17"
case 1'1
case
end
sync always
update \cur_pri14 $0\cur_pri14[7:0]
end
- attribute \src "libresoc.v:53767.3-53816.6"
- process $proc$libresoc.v:53767$2562
+ attribute \src "libresoc.v:53770.3-53819.6"
+ process $proc$libresoc.v:53770$2563
assign { } { }
assign { } { }
assign $0\be_out[31:0] $1\be_out[31:0]
- attribute \src "libresoc.v:53768.5-53768.29"
+ attribute \src "libresoc.v:53771.5-53771.29"
switch \initial
- attribute \src "libresoc.v:53768.9-53768.17"
+ attribute \src "libresoc.v:53771.9-53771.17"
case 1'1
case
end
sync always
update \be_out $0\be_out[31:0]
end
- attribute \src "libresoc.v:53817.3-53826.6"
- process $proc$libresoc.v:53817$2563
+ attribute \src "libresoc.v:53820.3-53829.6"
+ process $proc$libresoc.v:53820$2564
assign { } { }
assign { } { }
assign $0\cur_idx14[3:0] $1\cur_idx14[3:0]
- attribute \src "libresoc.v:53818.5-53818.29"
+ attribute \src "libresoc.v:53821.5-53821.29"
switch \initial
- attribute \src "libresoc.v:53818.9-53818.17"
+ attribute \src "libresoc.v:53821.9-53821.17"
case 1'1
case
end
sync always
update \cur_idx14 $0\cur_idx14[3:0]
end
- attribute \src "libresoc.v:53827.3-53836.6"
- process $proc$libresoc.v:53827$2564
+ attribute \src "libresoc.v:53830.3-53839.6"
+ process $proc$libresoc.v:53830$2565
assign { } { }
assign { } { }
assign $0\cur_pri15[7:0] $1\cur_pri15[7:0]
- attribute \src "libresoc.v:53828.5-53828.29"
+ attribute \src "libresoc.v:53831.5-53831.29"
switch \initial
- attribute \src "libresoc.v:53828.9-53828.17"
+ attribute \src "libresoc.v:53831.9-53831.17"
case 1'1
case
end
sync always
update \cur_pri15 $0\cur_pri15[7:0]
end
- attribute \src "libresoc.v:53837.3-53846.6"
- process $proc$libresoc.v:53837$2565
+ attribute \src "libresoc.v:53840.3-53849.6"
+ process $proc$libresoc.v:53840$2566
assign { } { }
assign { } { }
assign $0\cur_idx15[3:0] $1\cur_idx15[3:0]
- attribute \src "libresoc.v:53838.5-53838.29"
+ attribute \src "libresoc.v:53841.5-53841.29"
switch \initial
- attribute \src "libresoc.v:53838.9-53838.17"
+ attribute \src "libresoc.v:53841.9-53841.17"
case 1'1
case
end
sync always
update \cur_idx15 $0\cur_idx15[3:0]
end
- attribute \src "libresoc.v:53847.3-53856.6"
- process $proc$libresoc.v:53847$2566
+ attribute \src "libresoc.v:53850.3-53859.6"
+ process $proc$libresoc.v:53850$2567
assign { } { }
assign { } { }
assign $0\ibit[0:0] $1\ibit[0:0]
- attribute \src "libresoc.v:53848.5-53848.29"
+ attribute \src "libresoc.v:53851.5-53851.29"
switch \initial
- attribute \src "libresoc.v:53848.9-53848.17"
+ attribute \src "libresoc.v:53851.9-53851.17"
case 1'1
case
end
sync always
update \ibit $0\ibit[0:0]
end
- attribute \src "libresoc.v:53857.3-53865.6"
- process $proc$libresoc.v:53857$2567
+ attribute \src "libresoc.v:53860.3-53868.6"
+ process $proc$libresoc.v:53860$2568
assign { } { }
assign { } { }
- assign $0\ics_wb__dat_r$next[31:0]$2568 $1\ics_wb__dat_r$next[31:0]$2569
- attribute \src "libresoc.v:53858.5-53858.29"
+ assign $0\ics_wb__dat_r$next[31:0]$2569 $1\ics_wb__dat_r$next[31:0]$2570
+ attribute \src "libresoc.v:53861.5-53861.29"
switch \initial
- attribute \src "libresoc.v:53858.9-53858.17"
+ attribute \src "libresoc.v:53861.9-53861.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ics_wb__dat_r$next[31:0]$2569 0
+ assign $1\ics_wb__dat_r$next[31:0]$2570 0
case
- assign $1\ics_wb__dat_r$next[31:0]$2569 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
+ assign $1\ics_wb__dat_r$next[31:0]$2570 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] }
end
sync always
- update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2568
+ update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$2569
end
- attribute \src "libresoc.v:53866.3-53874.6"
- process $proc$libresoc.v:53866$2570
+ attribute \src "libresoc.v:53869.3-53877.6"
+ process $proc$libresoc.v:53869$2571
assign { } { }
assign { } { }
- assign $0\ics_wb__ack$next[0:0]$2571 $1\ics_wb__ack$next[0:0]$2572
- attribute \src "libresoc.v:53867.5-53867.29"
+ assign $0\ics_wb__ack$next[0:0]$2572 $1\ics_wb__ack$next[0:0]$2573
+ attribute \src "libresoc.v:53870.5-53870.29"
switch \initial
- attribute \src "libresoc.v:53867.9-53867.17"
+ attribute \src "libresoc.v:53870.9-53870.17"
case 1'1
case
end
attribute \src "libresoc.v:0.0-0.0"
case 1'1
assign { } { }
- assign $1\ics_wb__ack$next[0:0]$2572 1'0
- case
- assign $1\ics_wb__ack$next[0:0]$2572 \wb_valid
- end
- sync always
- update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2571
- end
- connect \$7 $ternary$libresoc.v:53237$2325_Y
- connect \$99 $lt$libresoc.v:53238$2326_Y
- connect \$101 $and$libresoc.v:53239$2327_Y
- connect \$103 $lt$libresoc.v:53240$2328_Y
- connect \$105 $and$libresoc.v:53241$2329_Y
- connect \$107 $lt$libresoc.v:53242$2330_Y
- connect \$109 $and$libresoc.v:53243$2331_Y
- connect \$111 $lt$libresoc.v:53244$2332_Y
- connect \$113 $and$libresoc.v:53245$2333_Y
- connect \$115 $lt$libresoc.v:53246$2334_Y
- connect \$117 $and$libresoc.v:53247$2335_Y
- connect \$119 $lt$libresoc.v:53248$2336_Y
- connect \$121 $and$libresoc.v:53249$2337_Y
- connect \$123 $lt$libresoc.v:53250$2338_Y
- connect \$125 $and$libresoc.v:53251$2339_Y
- connect \$127 $lt$libresoc.v:53252$2340_Y
- connect \$12 $eq$libresoc.v:53253$2341_Y
- connect \$129 $and$libresoc.v:53254$2342_Y
- connect \$131 $lt$libresoc.v:53255$2343_Y
- connect \$133 $and$libresoc.v:53256$2344_Y
- connect \$135 $lt$libresoc.v:53257$2345_Y
- connect \$137 $and$libresoc.v:53258$2346_Y
- connect \$11 $ternary$libresoc.v:53259$2347_Y
- connect \$139 $lt$libresoc.v:53260$2348_Y
- connect \$141 $and$libresoc.v:53261$2349_Y
- connect \$143 $lt$libresoc.v:53262$2350_Y
- connect \$145 $and$libresoc.v:53263$2351_Y
- connect \$147 $lt$libresoc.v:53264$2352_Y
- connect \$149 $and$libresoc.v:53265$2353_Y
- connect \$151 $lt$libresoc.v:53266$2354_Y
- connect \$153 $and$libresoc.v:53267$2355_Y
- connect \$155 $lt$libresoc.v:53268$2356_Y
- connect \$157 $and$libresoc.v:53269$2357_Y
- connect \$159 $lt$libresoc.v:53270$2358_Y
- connect \$161 $and$libresoc.v:53271$2359_Y
- connect \$163 $lt$libresoc.v:53272$2360_Y
- connect \$165 $and$libresoc.v:53273$2361_Y
- connect \$167 $lt$libresoc.v:53274$2362_Y
- connect \$16 $eq$libresoc.v:53275$2363_Y
- connect \$169 $and$libresoc.v:53276$2364_Y
- connect \$171 $lt$libresoc.v:53277$2365_Y
- connect \$173 $and$libresoc.v:53278$2366_Y
- connect \$175 $lt$libresoc.v:53279$2367_Y
- connect \$177 $and$libresoc.v:53280$2368_Y
- connect \$15 $ternary$libresoc.v:53281$2369_Y
- connect \$179 $lt$libresoc.v:53282$2370_Y
- connect \$181 $and$libresoc.v:53283$2371_Y
- connect \$183 $lt$libresoc.v:53284$2372_Y
- connect \$185 $and$libresoc.v:53285$2373_Y
- connect \$187 $lt$libresoc.v:53286$2374_Y
- connect \$189 $and$libresoc.v:53287$2375_Y
- connect \$191 $lt$libresoc.v:53288$2376_Y
- connect \$193 $and$libresoc.v:53289$2377_Y
- connect \$195 $lt$libresoc.v:53290$2378_Y
- connect \$197 $and$libresoc.v:53291$2379_Y
- connect \$1 $eq$libresoc.v:53292$2380_Y
- connect \$199 $lt$libresoc.v:53293$2381_Y
- connect \$201 $and$libresoc.v:53294$2382_Y
- connect \$204 $eq$libresoc.v:53295$2383_Y
- connect \$203 $ternary$libresoc.v:53296$2384_Y
- connect \$20 $eq$libresoc.v:53297$2385_Y
- connect \$19 $ternary$libresoc.v:53298$2386_Y
- connect \$24 $eq$libresoc.v:53299$2387_Y
- connect \$23 $ternary$libresoc.v:53300$2388_Y
- connect \$28 $eq$libresoc.v:53301$2389_Y
- connect \$27 $ternary$libresoc.v:53302$2390_Y
- connect \$32 $eq$libresoc.v:53303$2391_Y
- connect \$31 $ternary$libresoc.v:53304$2392_Y
- connect \$36 $eq$libresoc.v:53305$2393_Y
- connect \$35 $ternary$libresoc.v:53306$2394_Y
- connect \$3 $eq$libresoc.v:53307$2395_Y
- connect \$40 $eq$libresoc.v:53308$2396_Y
- connect \$39 $ternary$libresoc.v:53309$2397_Y
- connect \$44 $eq$libresoc.v:53310$2398_Y
- connect \$43 $ternary$libresoc.v:53311$2399_Y
- connect \$48 $eq$libresoc.v:53312$2400_Y
- connect \$47 $ternary$libresoc.v:53313$2401_Y
- connect \$52 $eq$libresoc.v:53314$2402_Y
- connect \$51 $ternary$libresoc.v:53315$2403_Y
- connect \$56 $eq$libresoc.v:53316$2404_Y
- connect \$55 $ternary$libresoc.v:53317$2405_Y
- connect \$5 $and$libresoc.v:53318$2406_Y
- connect \$60 $eq$libresoc.v:53319$2407_Y
- connect \$59 $ternary$libresoc.v:53320$2408_Y
- connect \$64 $eq$libresoc.v:53321$2409_Y
- connect \$63 $ternary$libresoc.v:53322$2410_Y
- connect \$68 $eq$libresoc.v:53323$2411_Y
- connect \$67 $ternary$libresoc.v:53324$2412_Y
- connect \$71 $shr$libresoc.v:53325$2413_Y [0]
- connect \$73 $and$libresoc.v:53326$2414_Y
- connect \$75 $lt$libresoc.v:53327$2415_Y
- connect \$77 $and$libresoc.v:53328$2416_Y
- connect \$79 $lt$libresoc.v:53329$2417_Y
- connect \$81 $and$libresoc.v:53330$2418_Y
- connect \$83 $lt$libresoc.v:53331$2419_Y
- connect \$85 $and$libresoc.v:53332$2420_Y
- connect \$87 $lt$libresoc.v:53333$2421_Y
- connect \$8 $eq$libresoc.v:53334$2422_Y
- connect \$89 $and$libresoc.v:53335$2423_Y
- connect \$91 $lt$libresoc.v:53336$2424_Y
- connect \$93 $and$libresoc.v:53337$2425_Y
- connect \$95 $lt$libresoc.v:53338$2426_Y
- connect \$97 $and$libresoc.v:53339$2427_Y
+ assign $1\ics_wb__ack$next[0:0]$2573 1'0
+ case
+ assign $1\ics_wb__ack$next[0:0]$2573 \wb_valid
+ end
+ sync always
+ update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$2572
+ end
+ connect \$7 $ternary$libresoc.v:53240$2326_Y
+ connect \$99 $lt$libresoc.v:53241$2327_Y
+ connect \$101 $and$libresoc.v:53242$2328_Y
+ connect \$103 $lt$libresoc.v:53243$2329_Y
+ connect \$105 $and$libresoc.v:53244$2330_Y
+ connect \$107 $lt$libresoc.v:53245$2331_Y
+ connect \$109 $and$libresoc.v:53246$2332_Y
+ connect \$111 $lt$libresoc.v:53247$2333_Y
+ connect \$113 $and$libresoc.v:53248$2334_Y
+ connect \$115 $lt$libresoc.v:53249$2335_Y
+ connect \$117 $and$libresoc.v:53250$2336_Y
+ connect \$119 $lt$libresoc.v:53251$2337_Y
+ connect \$121 $and$libresoc.v:53252$2338_Y
+ connect \$123 $lt$libresoc.v:53253$2339_Y
+ connect \$125 $and$libresoc.v:53254$2340_Y
+ connect \$127 $lt$libresoc.v:53255$2341_Y
+ connect \$12 $eq$libresoc.v:53256$2342_Y
+ connect \$129 $and$libresoc.v:53257$2343_Y
+ connect \$131 $lt$libresoc.v:53258$2344_Y
+ connect \$133 $and$libresoc.v:53259$2345_Y
+ connect \$135 $lt$libresoc.v:53260$2346_Y
+ connect \$137 $and$libresoc.v:53261$2347_Y
+ connect \$11 $ternary$libresoc.v:53262$2348_Y
+ connect \$139 $lt$libresoc.v:53263$2349_Y
+ connect \$141 $and$libresoc.v:53264$2350_Y
+ connect \$143 $lt$libresoc.v:53265$2351_Y
+ connect \$145 $and$libresoc.v:53266$2352_Y
+ connect \$147 $lt$libresoc.v:53267$2353_Y
+ connect \$149 $and$libresoc.v:53268$2354_Y
+ connect \$151 $lt$libresoc.v:53269$2355_Y
+ connect \$153 $and$libresoc.v:53270$2356_Y
+ connect \$155 $lt$libresoc.v:53271$2357_Y
+ connect \$157 $and$libresoc.v:53272$2358_Y
+ connect \$159 $lt$libresoc.v:53273$2359_Y
+ connect \$161 $and$libresoc.v:53274$2360_Y
+ connect \$163 $lt$libresoc.v:53275$2361_Y
+ connect \$165 $and$libresoc.v:53276$2362_Y
+ connect \$167 $lt$libresoc.v:53277$2363_Y
+ connect \$16 $eq$libresoc.v:53278$2364_Y
+ connect \$169 $and$libresoc.v:53279$2365_Y
+ connect \$171 $lt$libresoc.v:53280$2366_Y
+ connect \$173 $and$libresoc.v:53281$2367_Y
+ connect \$175 $lt$libresoc.v:53282$2368_Y
+ connect \$177 $and$libresoc.v:53283$2369_Y
+ connect \$15 $ternary$libresoc.v:53284$2370_Y
+ connect \$179 $lt$libresoc.v:53285$2371_Y
+ connect \$181 $and$libresoc.v:53286$2372_Y
+ connect \$183 $lt$libresoc.v:53287$2373_Y
+ connect \$185 $and$libresoc.v:53288$2374_Y
+ connect \$187 $lt$libresoc.v:53289$2375_Y
+ connect \$189 $and$libresoc.v:53290$2376_Y
+ connect \$191 $lt$libresoc.v:53291$2377_Y
+ connect \$193 $and$libresoc.v:53292$2378_Y
+ connect \$195 $lt$libresoc.v:53293$2379_Y
+ connect \$197 $and$libresoc.v:53294$2380_Y
+ connect \$1 $eq$libresoc.v:53295$2381_Y
+ connect \$199 $lt$libresoc.v:53296$2382_Y
+ connect \$201 $and$libresoc.v:53297$2383_Y
+ connect \$204 $eq$libresoc.v:53298$2384_Y
+ connect \$203 $ternary$libresoc.v:53299$2385_Y
+ connect \$20 $eq$libresoc.v:53300$2386_Y
+ connect \$19 $ternary$libresoc.v:53301$2387_Y
+ connect \$24 $eq$libresoc.v:53302$2388_Y
+ connect \$23 $ternary$libresoc.v:53303$2389_Y
+ connect \$28 $eq$libresoc.v:53304$2390_Y
+ connect \$27 $ternary$libresoc.v:53305$2391_Y
+ connect \$32 $eq$libresoc.v:53306$2392_Y
+ connect \$31 $ternary$libresoc.v:53307$2393_Y
+ connect \$36 $eq$libresoc.v:53308$2394_Y
+ connect \$35 $ternary$libresoc.v:53309$2395_Y
+ connect \$3 $eq$libresoc.v:53310$2396_Y
+ connect \$40 $eq$libresoc.v:53311$2397_Y
+ connect \$39 $ternary$libresoc.v:53312$2398_Y
+ connect \$44 $eq$libresoc.v:53313$2399_Y
+ connect \$43 $ternary$libresoc.v:53314$2400_Y
+ connect \$48 $eq$libresoc.v:53315$2401_Y
+ connect \$47 $ternary$libresoc.v:53316$2402_Y
+ connect \$52 $eq$libresoc.v:53317$2403_Y
+ connect \$51 $ternary$libresoc.v:53318$2404_Y
+ connect \$56 $eq$libresoc.v:53319$2405_Y
+ connect \$55 $ternary$libresoc.v:53320$2406_Y
+ connect \$5 $and$libresoc.v:53321$2407_Y
+ connect \$60 $eq$libresoc.v:53322$2408_Y
+ connect \$59 $ternary$libresoc.v:53323$2409_Y
+ connect \$64 $eq$libresoc.v:53324$2410_Y
+ connect \$63 $ternary$libresoc.v:53325$2411_Y
+ connect \$68 $eq$libresoc.v:53326$2412_Y
+ connect \$67 $ternary$libresoc.v:53327$2413_Y
+ connect \$71 $shr$libresoc.v:53328$2414_Y [0]
+ connect \$73 $and$libresoc.v:53329$2415_Y
+ connect \$75 $lt$libresoc.v:53330$2416_Y
+ connect \$77 $and$libresoc.v:53331$2417_Y
+ connect \$79 $lt$libresoc.v:53332$2418_Y
+ connect \$81 $and$libresoc.v:53333$2419_Y
+ connect \$83 $lt$libresoc.v:53334$2420_Y
+ connect \$85 $and$libresoc.v:53335$2421_Y
+ connect \$87 $lt$libresoc.v:53336$2422_Y
+ connect \$8 $eq$libresoc.v:53337$2423_Y
+ connect \$89 $and$libresoc.v:53338$2424_Y
+ connect \$91 $lt$libresoc.v:53339$2425_Y
+ connect \$93 $and$libresoc.v:53340$2426_Y
+ connect \$95 $lt$libresoc.v:53341$2427_Y
+ connect \$97 $and$libresoc.v:53342$2428_Y
connect \icp_r_pri \$203
connect \icp_r_src \cur_idx15
connect \max_idx 4'0000
projects / soclayout.git / commitdiff