Completed experiment10, adder with JTAG (dual clocks) and GPIO pads.

diff --git a/experiments10/Makefile b/experiments10/Makefile
index e9b85e049ba82e6c53ee49893c392c53edcbe804..700c8053f2410425113f319bd01dbb70d06838f8 100755 (executable)
--- a/experiments10/Makefile
+++ b/experiments10/Makefile
@@ -1,17 +1,10 @@
-# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
 
         LOGICAL_SYNTHESIS = Yosys
        PHYSICAL_SYNTHESIS = Coriolis
-               DESIGN_KIT = sxlib
-
+               DESIGN_KIT = cmos45
             YOSYS_FLATTEN = No
                      CHIP = chip
                      CORE = add
-                   MARGIN = 2
-                  BOOMOPT =  # -A
-                  BOOGOPT =
-                  LOONOPT =
-                NSL2VHOPT = -vasy # -split -p
             USE_CLOCKTREE = Yes
                 USE_DEBUG = No
                  USE_KITE = No

diff --git a/experiments10/add.py b/experiments10/add.py
index 73e409272bd136db75bde5090541a55c7ff9aa27..a3b6f085958152a1e2df940e779bcd409a1f8cfb 100644 (file)
--- a/experiments10/add.py
+++ b/experiments10/add.py
@@ -14,9 +14,11 @@ from c4m.nmigen.jtag.tap import TAP, IOType
 
 class ADD(Elaboratable):
     def __init__(self, width):
-        self.a   = Signal(width)
-        self.b   = Signal(width)
-        self.f   = Signal(width)
+        self.a      = Signal(width)
+        self.b      = Signal(width)
+        self.f      = Signal(width)
+        self.io_in  = Signal(1)
+        self.io_out = Signal(1)
 
         # set up JTAG
         self.jtag = TAP(ir_width=3)
@@ -33,6 +35,8 @@ class ADD(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
+        m.d.comb += self.io_in.eq(False)
+        m.d.comb += self.io_out.eq(True)
 
         m.submodules.jtag = jtag = self.jtag
         m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
@@ -51,6 +55,7 @@ def create_ilang(dut, ports, test_name):
 if __name__ == "__main__":
     alu = ADD(width=4)
     create_ilang(alu, [alu.a, alu.b, alu.f,
+                       alu.io_in, alu.io_out,
                        alu.jtag.bus.tck,
                         alu.jtag.bus.tms,
                         alu.jtag.bus.tdo,

diff --git a/experiments10/coriolis2/settings.py b/experiments10/coriolis2/settings.py
index 5a2d575eef2527e7753407a8fb156a258426433c..ba1f2a3b46e09624a793551b618e86a14318efe5 100644 (file)
--- a/experiments10/coriolis2/settings.py
+++ b/experiments10/coriolis2/settings.py
@@ -6,9 +6,13 @@ import Cfg
 import CRL
 import Viewer
 #import node180.scn6m_deep_09
-import symbolic.cmos
+import symbolic.cmos45
 from   helpers       import overlay, l, u, n
 
+if os.environ.has_key('CELLS_TOP'):
+    cellsTop = os.environ['CELLS_TOP']
+else:
+    cellsTop = '../../../alliance-check-toolkit/cells'
 with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     cfg.misc.catchCore = False
     cfg.misc.info = False
@@ -22,7 +26,7 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     cfg.etesian.aspectRatio = 1.0
     cfg.anabatic.edgeLenght = 24
     cfg.anabatic.edgeWidth = 8
-    cfg.anabatic.topRoutingLayer = 'METAL4'
+    cfg.anabatic.topRoutingLayer = 'METAL5'
     cfg.katana.eventsLimit = 4000000
     cfg.etesian.effort = 2
     cfg.etesian.uniformDensity = True
@@ -31,6 +35,8 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
     af  = CRL.AllianceFramework.get()
     env = af.getEnvironment()
-    env.setCLOCK( '^clk|^ck' )
-
+    env.setCLOCK( '^clk|^ck|^tck' )
+    env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib', mode=CRL.Environment.Prepend )
+    env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
 print( '  o  Successfully run "<>/coriolis2/settings.py".' )
+print( '     - CELLS_TOP = "{}"'.format(cellsTop) )

diff --git a/experiments10/doDesign.py b/experiments10/doDesign.py
index 588b7dd0c26bfbbcc8179ce84c2f23d0f3fee469..62558f891bfec8f2f437f88c00ad2371ed411618 100644 (file)
--- a/experiments10/doDesign.py
+++ b/experiments10/doDesign.py
@@ -13,7 +13,7 @@ from   Hurricane  import DbU
 from   plugins.alpha.block.block         import Block
 from   plugins.alpha.block.configuration import IoPin
 from   plugins.alpha.block.configuration import GaugeConf
-from   plugins.alpha.core2chip.cmos      import CoreToChip
+from   plugins.alpha.core2chip.niolib    import CoreToChip
 from   plugins.alpha.chip.configuration  import ChipConf
 from   plugins.alpha.chip.chip           import Chip
 
@@ -26,7 +26,7 @@ def scriptMain ( **kw ):
     global af
     rvalue = True
     try:
-       #helpers.setTraceLevel( 540 )
+        helpers.setTraceLevel( 550 )
         usePadsPosition = True
         buildChip       = True
         cell, editor = plugins.kwParseMain( **kw )
@@ -35,42 +35,48 @@ def scriptMain ( **kw ):
             print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to load cell "{}".'.format('adder') ))
             sys.exit( 1 )
         if editor: editor.setCell( cell ) 
-        #     Spec:  | Side        | Pos | Instance     | Pad net   |Core net |
-        ioPadsSpec = [ (IoPin.SOUTH, None, 'p_a0'       , 'a(0)'   , 'a(0)'   )
-                     , (IoPin.SOUTH, None, 'p_a1'       , 'a(1)'   , 'a(1)'   )
-                     , (IoPin.SOUTH, None, 'power_0'    , 'vddpad' , 'vdd'    )
-                     , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'   )
-                     , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'   )
-                     , (IoPin.EAST , None, 'clock_0'    , 'clk'    , 'clk'    )
-                     , (IoPin.EAST , None, 'p_tms_0'    , 'tms'    , 'tms'    )
-                     , (IoPin.EAST , None, 'p_tdo_0'    , 'tdo'    , 'tdo'    )
-                     , (IoPin.EAST , None, 'p_tdi_0'    , 'tdi'    , 'tdi'    )
-                     , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'   )
-                     , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'   )
-                     , (IoPin.NORTH, None, 'ground_0'   , 'vsspad' , 'vss'    )
-                     , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'   )
-                     , (IoPin.NORTH, None, 'rst'        , 'rst'    , 'rst'    )
-                     , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'   )
-                     , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'   )
-                     , (IoPin.WEST , None, 'p_f1'       , 'f(1)'   , 'f(1)'   )
-                     , (IoPin.WEST , None, 'p_f0'       , 'f(0)'   , 'f(0)'   )
-                     , (IoPin.WEST , None, 'p_a3'       , 'a(3)'   , 'a(3)'   )
+        #     Spec:  | Side        | Pos | Instance     | Pad net   |Core net | Direction |
+        ioPadsSpec = [ (IoPin.SOUTH, None, 'p_a0'       , 'a(0)'   , 'a(0)'   , 'io_in'   )
+                     , (IoPin.SOUTH, None, 'p_a1'       , 'a(1)'   , 'a(1)'   , 'io_in'   )
+                     , (IoPin.SOUTH, None, 'iopower_0'  , 'iovdd'  )
+                     , (IoPin.SOUTH, None, 'power_0'    , 'vdd'    )
+                     , (IoPin.SOUTH, None, 'p_a2'       , 'a(2)'   , 'a(2)'   , 'io_in'   )
+                     , (IoPin.SOUTH, None, 'p_b3'       , 'b(3)'   , 'b(3)'   , 'io_in'   )
+                     , (IoPin.EAST , None, 'p_tms_0'    , 'tms'    , 'tms'    , 'io_in'   )
+                     , (IoPin.EAST , None, 'p_tdo_0'    , 'tdo'    , 'tdo'    , 'io_out'  )
+                     , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
+                     , (IoPin.EAST , None, 'p_clk'      , 'clk'    , 'clk'    , 'io_in'   )
+                     , (IoPin.EAST , None, 'p_tck'      , 'tck'    , 'tck'    , 'io_in'   )
+                     , (IoPin.EAST , None, 'p_tdi_0'    , 'tdi'    , 'tdi'    , 'io_in'   )
+                     , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'   , 'io_in'   )
+                     , (IoPin.NORTH, None, 'ioground_0' , 'iovss'  )
+                     , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'   , 'io_in'   )
+                     , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
+                     , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'   , 'io_in'   )
+                     , (IoPin.NORTH, None, 'rst'        , 'rst'    , 'rst'    , 'io_in'   )
+                     , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'   , 'io_out'  )
+                     , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'   , 'io_out'  )
+                     , (IoPin.WEST , None, 'power_1'    , 'vdd'    )
+                     , (IoPin.WEST , None, 'p_f1'       , 'f(1)'   , 'f(1)'   , 'io_out'  )
+                     , (IoPin.WEST , None, 'p_f0'       , 'f(0)'   , 'f(0)'   , 'io_out'  )
+                     , (IoPin.WEST , None, 'p_a3'       , 'a(3)'   , 'a(3)'   , 'io_in'   )
                      ]
         adderConf = ChipConf( cell, ioPads=ioPadsSpec )
         adderConf.cfg.etesian.bloat = 'nsxlib'
         adderConf.cfg.etesian.uniformDensity = True
         adderConf.cfg.etesian.aspectRatio = 1.0
         adderConf.cfg.etesian.spaceMargin = 0.05
-        adderConf.cfg.block.spareSide = l(350)
+        adderConf.cfg.block.spareSide = l(700)
+        adderConf.cfg.chip.padCoreSide = 'North'
         adderConf.editor = editor
         adderConf.useSpares = True
         adderConf.useClockTree = True
         adderConf.bColumns = 2
         adderConf.bRows = 2
         adderConf.chipConf.name = 'chip'
-        adderConf.chipConf.ioPadGauge = 'pxlib'
-        adderConf.coreSize = ( l(1200), l(1200) )
-        adderConf.chipSize = ( l(3200), l(3200) )
+        adderConf.chipConf.ioPadGauge = 'niolib'
+        adderConf.coreSize = ( l(2000), l(2000) )
+        adderConf.chipSize = ( l(5900), l(5900) )
         adderToChip = CoreToChip( adderConf )
         adderToChip.buildChip()
         chipBuilder = Chip( adderConf )