add second Makefile

diff --git a/Makefile2 b/Makefile2
new file mode 100755 (executable)
index 0000000..a69d673
--- /dev/null
+++ b/Makefile2
@@ -0,0 +1,25 @@
+# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
+
+        LOGICAL_SYNTHESIS = Yosys
+       PHYSICAL_SYNTHESIS = Coriolis
+               DESIGN_KIT = sxlib
+
+#           YOSYS_FLATTEN = Yes
+            USE_CLOCKTREE = Yes
+                USE_DEBUG = No
+                 USE_KITE = No
+
+                 NETLISTS = $(shell cat nets2.txt)
+
+
+ include ./mk/design-flow.mk
+
+
+blif:      part_sig_add.blif
+vst:       part_sig_add.vst
+layout:    part_sig_add_cts_r.ap
+gds:       part_sig_add_cts_r.gds
+
+lvx:       lvx-part_sig_add_cts_r
+druc:      druc-part_sig_add_cts_r
+view:      cgt-part_sig_add_cts_r

diff --git a/coriolis2/settings.py b/coriolis2/settings.py
index a04ab9d12effea451a0e9210d6c3ef71e1920e8c..d409bc325186f2237e193a5373006145e47d657a 100644 (file)
--- a/coriolis2/settings.py
+++ b/coriolis2/settings.py
@@ -22,7 +22,7 @@ Cfg.getParamBool      ( 'misc.verboseLevel2'          ).setBool      ( True    )
 #Cfg.getParamInt       ( 'misc.minTraceLevel'          ).setInt       ( 159     )
 #Cfg.getParamInt       ( 'misc.maxTraceLevel'          ).setInt       ( 160     )
 Cfg.getParamEnumerate ( 'etesian.effort'              ).setInt       ( 2       )
-Cfg.getParamPercentage( 'etesian.spaceMargin'         ).setPercentage( 50.0    )
+Cfg.getParamPercentage( 'etesian.spaceMargin'         ).setPercentage( 20.0    )
 Cfg.getParamPercentage( 'etesian.aspectRatio'         ).setPercentage( 100.0   )
 Cfg.getParamBool      ( 'etesian.uniformDensity'      ).setBool      ( True    )
 Cfg.getParamInt       ( 'anabatic.edgeLenght'         ).setInt       ( 24      )

diff --git a/examples/part_sig_add.py b/examples/part_sig_add.py
index 0113e0425b5f64b306c1b592c5cb9c2d1fdae805..2caf2b471f5a8d5289abd2d9b73f72b3271c2d1b 100644 (file)
--- a/examples/part_sig_add.py
+++ b/examples/part_sig_add.py
@@ -6,14 +6,29 @@ from nmigen import Signal
 
 def test():
     width = 16
-    part_mask = Signal(4)  # divide into 4-bits
-    module = TestAddMod(width, part_mask)
+    pmask = Signal(4)  # divide into 4-bits
+    module = TestAddMod(width, pmask)
     sim = create_ilang(module,
-                               [part_mask,
+                               [pmask,
                                 module.a.sig,
                                 module.b.sig,
                                 module.add_output,
-                                module.eq_output],
+                                module.eq_output,
+                                module.ls_output,
+                                module.sub_output,
+                                module.eq_output,
+                                module.gt_output,
+                                module.ge_output,
+                                module.ne_output,
+                                module.lt_output,
+                                module.le_output,
+                                module.mux_sel,
+                                module.mux_out,
+                                module.carry_in,
+                                module.add_carry_out,
+                                module.sub_carry_out,
+                                module.neg_output,
+                               ],
                                "part_sig_add")
                             
 def run_yosys(test_name):

diff --git a/nets2.txt b/nets2.txt
new file mode 100644 (file)
index 0000000..22ddba7
--- /dev/null
+++ b/nets2.txt
@@ -0,0 +1,45 @@
+part_sig_add
+mux0
+mux1
+mux2
+gtc
+reorder
+gt1
+mux0$$2
+mux1$$3
+mux2$$4
+gtc$$1
+reorder$$5
+eq1
+mux0$$7
+mux1$$8
+mux2$$9
+gtc$$6
+reorder$$10
+ge1
+mux0$$12
+mux1$$13
+mux2$$14
+gtc$$11
+reorder$$15
+gt2
+mux0$$17
+mux1$$18
+mux2$$19
+gtc$$16
+reorder$$20
+eq2
+mux0$$22
+mux1$$23
+mux2$$24
+gtc$$21
+reorder$$25
+ge2
+ripple
+add1
+ripple$$26
+add2
+ripple$$27
+add3
+ls1
+pmux1