use sys_pllclk_from_pad not sys_clk_from_pad

rename module ls180

diff --git a/experiments9/build_full_4ksram_recon.sh b/experiments9/build_full_4ksram_recon.sh
index ba6a0b235978235e3867ad5f533d9010528e72ff..20921bb574822c7a7f456331a500bb7a31d10b4e 100755 (executable)
--- a/experiments9/build_full_4ksram_recon.sh
+++ b/experiments9/build_full_4ksram_recon.sh
@@ -21,7 +21,7 @@ make pinmux
 
 # clear out
 make clean
-rm *.vst *.ap
+rm *.vst *.ap *.blif *.gds
 
 # copies over a "full" core
 #cp non_generated/full_core_4_4ksram_ls180.il ls180.il

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
index 94968380989455376cc341fb17fd9da18fd6bc38..01866e573eafdb0570067e00eb982c9299f5a71e 100644 (file)
--- a/experiments9/doDesign.py
+++ b/experiments9/doDesign.py
@@ -61,7 +61,7 @@ def scriptMain (**kw):
         # ooo, how annoying.  nsxlib (only 6 METAL) cannot cope with 3 clocks!
         #ls180Conf.useHTree('core.por_clk') # output from the PLL, needs to be H-Tree
         ls180Conf.useHTree('jtag_tck_from_pad')
-        ls180Conf.useHTree('sys_clk_from_pad')
+        ls180Conf.useHTree('sys_pllclk_from_pad')
 
         ls180ToChip = CoreToChip( ls180Conf )
         ls180ToChip.buildChip()

diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v
index 44a879205faf393353021d5a28cc814e8c864a96..84155904230909a171b3ac6c45733692acd28244 100644 (file)
--- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v
+++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v
@@ -1,7 +1,7 @@
 //--------------------------------------------------------------------------------
 // Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-06-09 16:10:24
 //--------------------------------------------------------------------------------
-module ls180sram4k(
+module ls180(
        input wire uart_tx,
        input wire uart_rx,
        output wire i2c_scl,