rename sys_clk in adder test experiments10_verilog (success compile)

diff --git a/experiments10_verilog/add.py b/experiments10_verilog/add.py
index bcf0965be949fbb568501bf12b0ce873aa4195f3..7cbabb9d01f1c35d994caa8c81792d2e36c850c8 100644 (file)
--- a/experiments10_verilog/add.py
+++ b/experiments10_verilog/add.py
@@ -50,8 +50,7 @@ def create_verilog(dut, ports, test_name):
         f.write(vl)
 
 if __name__ == "__main__":
-    #alu = DomainRenamer("sys")(ADD(width=4))
-    alu = (ADD(width=4))
+    alu = DomainRenamer("sys")(ADD(width=4))
     create_verilog(alu, [alu.a, alu.b, alu.f,
                        alu.jtag.bus.tck,
                         alu.jtag.bus.tms,

diff --git a/experiments10_verilog/coriolis2/settings.py b/experiments10_verilog/coriolis2/settings.py
index 5c739c21609f4b491bc380b6e925a4facc9bd6ea..a0a92b5023faf8975d929427c4882c1f7fc5282a 100644 (file)
--- a/experiments10_verilog/coriolis2/settings.py
+++ b/experiments10_verilog/coriolis2/settings.py
@@ -35,7 +35,7 @@ with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
     Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
     af  = CRL.AllianceFramework.get()
     env = af.getEnvironment()
-    env.setCLOCK( '^clk|^ck|^jtag_tck' )
+    env.setCLOCK( '^sys_clk|^ck|^jtag_tck' )
     env.setPOWER( 'vdd' )
     env.setGROUND( 'vss' )
     env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib',

diff --git a/experiments10_verilog/doDesign.py b/experiments10_verilog/doDesign.py
index dad7f430d91550a775c2270d15e0bbfe88909185..4aa415ce51af0894897e39868b7824c643d33ffa 100644 (file)
--- a/experiments10_verilog/doDesign.py
+++ b/experiments10_verilog/doDesign.py
@@ -45,7 +45,7 @@ def scriptMain ( **kw ):
          , (IoPin.EAST , None, 'p_jtag_tms' , 'jtag_tms'    , 'jtag_tms'      )
          , (IoPin.EAST , None, 'p_jtag_tdo' , 'jtag_tdo'    , 'jtag_tdo'      )
          , (IoPin.EAST , None, 'ground_0'   , 'vss'    )
-         , (IoPin.EAST , None, 'clk'  , 'clk'    , 'clk'      )
+         , (IoPin.EAST , None, 'p_sys_clk'  , 'sys_clk'    , 'sys_clk'      )
          , (IoPin.EAST , None, 'p_jtag_tck' , 'jtag_tck'    , 'jtag_tck'      )
          , (IoPin.EAST , None, 'p_jtag_tdi' , 'jtag_tdi'    , 'jtag_tdi'      )
          , (IoPin.EAST , None, 'p_b2'       , 'b(2)'   , 'b(2)'     )
@@ -53,7 +53,7 @@ def scriptMain ( **kw ):
          , (IoPin.NORTH, None, 'p_b1'       , 'b(1)'   , 'b(1)'     )
          , (IoPin.NORTH, None, 'ground_1'   , 'vss'    )
          , (IoPin.NORTH, None, 'p_b0'       , 'b(0)'   , 'b(0)'     )
-         , (IoPin.NORTH, None, 'rst'  , 'rst'    , 'rst'      )
+         , (IoPin.NORTH, None, 'p_sys_rst'  , 'sys_rst'    , 'sys_rst'      )
          , (IoPin.WEST , None, 'p_f3'       , 'f(3)'   , 'f(3)'     )
          , (IoPin.WEST , None, 'p_f2'       , 'f(2)'   , 'f(2)'     )
          , (IoPin.WEST , None, 'power_1'    , 'vdd'    )