--- /dev/null
+# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*-
+
+ LOGICAL_SYNTHESIS = Yosys
+ PHYSICAL_SYNTHESIS = Coriolis
+ DESIGN_KIT = sxlib
+
+ YOSYS_FLATTEN = Yes
+ CHIP = chip
+ CORE = alu_hier
+ MARGIN = 5
+ BOOMOPT = -A
+ BOOGOPT =
+ LOONOPT =
+ NSL2VHOPT = -vasy # -split -p
+ USE_CLOCKTREE = Yes
+ USE_DEBUG = No
+ USE_KITE = No
+ RM_CHIP = Yes
+
+ NETLISTS = $(shell cat nets.txt)
+ PATTERNS = alu_hier_r
+
+
+ include ./mk/design-flow.mk
+
+
+#blif: alu_hier.blif
+#vst: alu_hier.vst
+dreal: dreal-chip_cts_r
+flatph: flatph-chip_cts_r
+layout: chip_cts_r.ap
+gds: chip_cts_r.gds
+
+lvx: lvx-chip_cts_r
+druc: druc-chip_cts_r
+view: cgt-chip_cts_r
+sim: asimut-alu_hier_cts_r
--- /dev/null
+from nmigen import *
+from nmigen.cli import rtlil
+
+
+class Adder(Elaboratable):
+ def __init__(self, width):
+ self.a = Signal(width)
+ self.b = Signal(width)
+ self.o = Signal(width)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.d.comb += self.o.eq(self.a + self.b)
+ return m
+
+
+class Subtractor(Elaboratable):
+ def __init__(self, width):
+ self.a = Signal(width)
+ self.b = Signal(width)
+ self.o = Signal(width)
+
+ def elaborate(self, platform):
+ m = Module()
+ m.d.comb += self.o.eq(self.a - self.b)
+ return m
+
+
+class ALU(Elaboratable):
+ def __init__(self, width):
+ self.op = Signal()
+ self.a = Signal(width)
+ self.b = Signal(width)
+ self.o = Signal(width)
+
+ self.add = Adder(width)
+ self.sub = Subtractor(width)
+
+ def elaborate(self, platform):
+
+ m = Module()
+ #m.domains.sync = ClockDomain()
+ #m.d.comb += ClockSignal().eq(self.m_clock)
+
+ m.submodules.add = self.add
+ m.submodules.sub = self.sub
+ m.d.comb += [
+ self.add.a.eq(self.a),
+ self.sub.a.eq(self.a),
+ self.add.b.eq(self.b),
+ self.sub.b.eq(self.b),
+ ]
+ with m.If(self.op):
+ m.d.sync += self.o.eq(self.sub.o)
+ with m.Else():
+ m.d.sync += self.o.eq(self.add.o)
+ return m
+
+
+def create_ilang(dut, ports, test_name):
+ vl = rtlil.convert(dut, name=test_name, ports=ports)
+ with open("%s.il" % test_name, "w") as f:
+ f.write(vl)
+
+if __name__ == "__main__":
+ alu = ALU(width=16)
+ create_ilang(alu, [#alu.m_clock, alu.p_reset,
+ alu.op, alu.a, alu.b, alu.o], "alu_hier")
--- /dev/null
+#!/usr/bin/env python
+
+from helpers import l, u, n
+
+def pad_nums(s, sep="_"):
+ res = []
+ for i in range(16):
+ res.append("%s%s%d" % (s, sep, i))
+ return res
+
+a_pads = pad_nums("a")
+o_pads = pad_nums("o")
+
+chip = { 'pads.ioPadGauge' : 'pxlib'
+ , 'pads.south' : a_pads[:8] + ["p_vddick_0", "p_vssick_0" ] + \
+ a_pads[8:]
+ , 'pads.east' : pad_nums("b")
+ , 'pads.north' : o_pads[:8] + ["p_vddeck_0", "p_vsseck_0" ] + \
+ o_pads[8:]
+ , 'pads.west' : [ "op",
+ "p_clk_0",
+ "rst",
+ ]
+ , 'core.size' : ( l(3000), l(3000) )
+ , 'chip.size' : ( l(5000), l(5000) )
+ , 'chip.clockTree' : True
+ }
--- /dev/null
+
+from Hurricane import DebugSession
+
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) )
--- /dev/null
+# -*- Mode:Python -*-
+
+import os
+import Cfg
+import CRL
+import Viewer
+#import node180.scn6m_deep_09
+import symbolic.cmos
+from helpers import l, u, n
+
+
+Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile )
+
+
+Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
+
+Cfg.getParamBool ( 'misc.catchCore' ).setBool ( False )
+Cfg.getParamBool ( 'misc.info' ).setBool ( False )
+Cfg.getParamBool ( 'misc.paranoid' ).setBool ( False )
+Cfg.getParamBool ( 'misc.bug' ).setBool ( False )
+Cfg.getParamBool ( 'misc.logMode' ).setBool ( True )
+Cfg.getParamBool ( 'misc.verboseLevel1' ).setBool ( True )
+Cfg.getParamBool ( 'misc.verboseLevel2' ).setBool ( True )
+#Cfg.getParamInt ( 'misc.minTraceLevel' ).setInt ( 159 )
+#Cfg.getParamInt ( 'misc.maxTraceLevel' ).setInt ( 160 )
+Cfg.getParamEnumerate ( 'etesian.effort' ).setInt ( 2 )
+Cfg.getParamPercentage( 'etesian.spaceMargin' ).setPercentage( 20.0 )
+Cfg.getParamPercentage( 'etesian.aspectRatio' ).setPercentage( 100.0 )
+Cfg.getParamBool ( 'etesian.uniformDensity' ).setBool ( True )
+Cfg.getParamInt ( 'anabatic.edgeLenght' ).setInt ( 24 )
+Cfg.getParamInt ( 'anabatic.edgeWidth' ).setInt ( 8 )
+Cfg.getParamString ( 'anabatic.topRoutingLayer' ).setString ( 'METAL5')
+Cfg.getParamInt ( 'katana.eventsLimit' ).setInt ( 1000000 )
+Cfg.getParamInt ( 'katana.hTracksReservedLocal' ).setInt ( 7 )
+Cfg.getParamInt ( 'katana.vTracksReservedLocal' ).setInt ( 6 )
+#Cfg.getParamInt ( 'clockTree.minimumSide' ).setInt ( l(1000) )
+
+Cfg.Configuration.popDefaultPriority()
+
+#cellsTop = os.path.abspath( os.getcwd()+'/../cells' )
+if os.environ.has_key('CELLS_TOP'):
+ cellsTop = os.environ['CELLS_TOP']
+else:
+ cellsTop = '../../../cells'
+
+af = CRL.AllianceFramework.get()
+env = af.getEnvironment()
+env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
+env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend )
+#env.setCLOCK( '^clk$|m_clock' )
+env.setCLOCK( 'clk' )
+env.setPOWER( 'vdd' )
+env.setGROUND( 'vss' )
+
+
+print 'Successfully read user configuration'
+
--- /dev/null
+../mksym.sh
\ No newline at end of file
--- /dev/null
+alu_hier add sub
projects / soclayout.git / commitdiff