add clocks and reset and add alu.py as well

diff --git a/examples/alu.py b/examples/alu.py
new file mode 100644 (file)
index 0000000..2fa14a0
--- /dev/null
+++ b/examples/alu.py
@@ -0,0 +1,40 @@
+from nmigen import *
+from nmigen.cli import rtlil
+
+
+class ALU(Elaboratable):
+    def __init__(self, width):
+        self.sel = Signal(2)
+        self.a   = Signal(width)
+        self.b   = Signal(width)
+        self.o   = Signal(width)
+        self.co  = Signal()
+        self.m_clock   = Signal(reset_less=True)
+        self.p_reset   = Signal(reset_less=True)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.domains.sync = ClockDomain()
+        m.d.comb += ClockSignal().eq(self.m_clock)
+
+        with m.If(self.sel == 0b00):
+            m.d.sync += self.o.eq(self.a | self.b)
+        with m.Elif(self.sel == 0b01):
+            m.d.sync += self.o.eq(self.a & self.b)
+        with m.Elif(self.sel == 0b10):
+            m.d.sync += self.o.eq(self.a ^ self.b)
+        with m.Else():
+            m.d.sync += Cat(self.o, self.co).eq(self.a - self.b)
+        return m
+
+
+def create_ilang(dut, ports, test_name):
+    vl = rtlil.convert(dut, name=test_name, ports=ports)
+    with open("%s.il" % test_name, "w") as f:
+        f.write(vl)
+
+if __name__ == "__main__":
+    alu = ALU(width=16)
+    create_ilang(alu, [alu.m_clock, alu.p_reset,
+                       alu.o, alu.a, alu.b, alu.co], "alu")
+

diff --git a/examples/alu_hier.py b/examples/alu_hier.py
index 4ae6ce48914034c0083ec54fc17db98007f37bf5..52ca05a80183cc69f72c8012da002c7a38987fd0 100644 (file)
--- a/examples/alu_hier.py
+++ b/examples/alu_hier.py
@@ -32,12 +32,18 @@ class ALU(Elaboratable):
         self.a   = Signal(width)
         self.b   = Signal(width)
         self.o   = Signal(width)
+        self.m_clock   = Signal(reset_less=True)
+        self.p_reset   = Signal(reset_less=True)
 
         self.add = Adder(width)
         self.sub = Subtractor(width)
 
     def elaborate(self, platform):
+
         m = Module()
+        m.domains.sync = ClockDomain()
+        m.d.comb += ClockSignal().eq(self.m_clock)
+
         m.submodules.add = self.add
         m.submodules.sub = self.sub
         m.d.comb += [
@@ -47,9 +53,9 @@ class ALU(Elaboratable):
             self.sub.b.eq(self.b),
         ]
         with m.If(self.op):
-            m.d.comb += self.o.eq(self.sub.o)
+            m.d.sync += self.o.eq(self.sub.o)
         with m.Else():
-            m.d.comb += self.o.eq(self.add.o)
+            m.d.sync += self.o.eq(self.add.o)
         return m
 
 
@@ -60,4 +66,5 @@ def create_ilang(dut, ports, test_name):
 
 if __name__ == "__main__":
     alu = ALU(width=16)
-    create_ilang(alu, [alu.op, alu.a, alu.b, alu.o], "alu_hier")
+    create_ilang(alu, [alu.m_clock, alu.p_reset,
+                       alu.op, alu.a, alu.b, alu.o], "alu_hier")