wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_adr;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_addr_acked;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output cr_a_ok;
input alu_op__zero_a;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
wire \alu_op__zero_a$63 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
input br_op__lk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
wire \br_op__lk$21 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
input [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0" *)
(* generator = "nMigen" *)
module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0" *)
(* generator = "nMigen" *)
module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alu;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0" *)
(* generator = "nMigen" *)
module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0" *)
(* generator = "nMigen" *)
module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" *)
(* generator = "nMigen" *)
module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0" *)
(* generator = "nMigen" *)
module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [63:0] fast1;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0" *)
(* generator = "nMigen" *)
module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, o, fast1, fast2, nia, msr, ra, rb, \fast1$1 , \fast2$2 , p_valid_i, p_ready_o, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [63:0] fast1;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_alui;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
output cu_busy_o;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_busy;
(* generator = "nMigen" *)
module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fasto1, core_fasto2, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core_msr, core_core_cia, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, \core_core_exc_$signal , \core_core_exc_$signal$3 , \core_core_exc_$signal$4 , \core_core_exc_$signal$5 , \core_core_exc_$signal$6 , \core_core_exc_$signal$7 , \core_core_exc_$signal$8 , \core_core_exc_$signal$9 , core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, raw_insn_i, bigendian_i, sv_a_nz, \wen$10 , \data_i$11 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$12 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$1001 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1003 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1006 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1010 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1012 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1019 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$1022 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1024 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1027 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1031 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1033 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1037 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$1040 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1042 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1045 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1049 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1051 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1059 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$1062 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1064 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1067 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1071 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1073 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1079 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$1082 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1084 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1087 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1091 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1093 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1099 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$1102 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1104 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1107 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1111 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1113 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1118 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$1121 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1123 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1126 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1130 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1132 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1136 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$1139 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1141 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1144 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1147 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1149 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1152 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$1155 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [64:0] \$1157 ;
wire \$1209 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire \$1211 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1213 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1215 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1218 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1221 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1223 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1226 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [7:0] \$1229 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1231 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1233 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1235 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1237 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1239 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1241 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1243 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1246 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1249 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1251 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1254 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [7:0] \$1257 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [255:0] \$1259 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [255:0] \$1261 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1263 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1266 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1269 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1271 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1274 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [7:0] \$1277 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [255:0] \$1279 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [255:0] \$1281 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1283 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1286 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1289 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1291 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1294 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [7:0] \$1297 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [255:0] \$1299 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [255:0] \$1301 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1303 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1306 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1309 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1311 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1314 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [7:0] \$1317 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [255:0] \$1319 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [255:0] \$1321 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1323 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1326 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1329 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1331 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1334 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [7:0] \$1337 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [255:0] \$1339 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [255:0] \$1341 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1343 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1346 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1349 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1351 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1354 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [7:0] \$1357 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
wire [255:0] \$1359 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [255:0] \$1361 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [3:0] \$1363 ;
wire [255:0] \$1380 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [255:0] \$1382 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1384 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1386 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1388 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1390 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1393 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1396 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1398 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1401 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [1:0] \$1404 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1406 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1409 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1412 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1414 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1417 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [1:0] \$1420 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1422 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1425 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1428 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1430 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1433 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [1:0] \$1436 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [1:0] \$1438 ;
wire [1:0] \$1443 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [1:0] \$1445 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1448 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1450 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1452 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1454 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1456 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1459 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1462 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1464 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1467 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [2:0] \$1470 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1472 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1475 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1478 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1480 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1483 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [2:0] \$1486 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1488 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1491 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1494 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1496 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1499 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [2:0] \$1502 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1504 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1507 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1510 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1512 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1515 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [2:0] \$1518 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [1:0] \$1520 ;
wire [2:0] \$1528 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [2:0] \$1530 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1532 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1534 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1536 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1538 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1540 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1543 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1546 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1548 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1551 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire \$1554 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1556 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1559 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1562 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1564 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1567 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire \$1570 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1572 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1575 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1578 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1580 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1583 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire \$1586 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1588 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1591 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1594 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1596 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1599 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire \$1602 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [1:0] \$1604 ;
wire \$1615 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire \$1617 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1620 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1622 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1624 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1626 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1628 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1630 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1633 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1637 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1639 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1644 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [2:0] \$1647 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1649 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1652 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1655 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1657 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1660 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [2:0] \$1663 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1665 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1668 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1671 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1673 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1676 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [2:0] \$1679 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1681 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1684 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1687 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1689 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1692 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [2:0] \$1695 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1697 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1700 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1703 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1705 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1708 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [2:0] \$1711 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [63:0] \$1713 ;
wire \$1733 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire \$1735 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1737 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1739 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1741 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1744 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1747 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1749 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1752 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire \$1755 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1757 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1760 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1763 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1765 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1768 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire \$1771 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [63:0] \$1773 ;
wire [2:0] \$1775 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire \$1776 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1779 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1781 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1784 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1787 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1789 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1792 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [1:0] \$1795 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \$1797 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$1799 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$1801 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$1804 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1807 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$1809 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$181 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$1812 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [9:0] \$1815 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$182 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$185 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$186 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$189 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$190 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$193 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$194 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$197 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$198 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$201 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$202 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$205 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$206 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$209 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$210 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$213 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$214 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire \$217 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
wire [13:0] \$218 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *)
wire \$221 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *)
wire [2:0] \$223 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *)
- wire [2:0] \$224 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *)
+ wire [2:0] \$224 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *)
wire \$226 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [3:0] \$228 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
wire \$229 ;
wire \$245 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
wire \$247 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [5:0] \$250 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [2:0] \$252 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [3:0] \$254 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [2:0] \$256 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
wire \$257 ;
wire \$265 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
wire \$267 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [5:0] \$270 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
wire \$271 ;
wire \$295 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
wire \$297 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [2:0] \$300 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
wire \$301 ;
wire \$309 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
wire \$311 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [2:0] \$314 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
wire \$315 ;
wire \$323 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
wire \$325 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [4:0] \$328 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
wire \$329 ;
wire \$345 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
wire \$347 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *)
wire [2:0] \$350 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$352 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$354 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$356 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$358 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$360 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$362 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$364 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$366 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$368 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$370 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$372 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$374 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$376 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$378 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$380 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$382 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$384 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$386 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$388 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$390 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$392 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$394 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$396 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$398 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$400 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$402 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$404 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$406 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$408 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$410 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$412 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$414 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$416 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$418 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$420 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$422 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$424 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$426 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$428 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$430 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$432 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$434 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$436 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$438 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$440 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$442 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$444 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$446 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$448 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$450 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$452 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$454 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$456 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$458 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$460 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$462 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$464 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$466 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$468 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$470 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$472 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$474 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$476 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$478 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$480 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$482 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$484 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$486 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$488 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$490 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$492 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$494 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$496 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$498 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$500 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$502 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$504 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$506 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$508 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$510 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$512 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$514 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$516 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$518 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$520 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$522 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$524 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$526 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$528 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$530 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$532 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$534 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$536 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$538 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$540 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$542 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$544 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$546 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$548 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$550 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$552 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$554 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$556 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$558 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$560 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$562 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$564 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$566 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$568 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$570 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$572 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$574 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$576 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [6:0] \$578 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [6:0] \$580 ;
wire [6:0] \$613 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [6:0] \$615 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *)
wire \$617 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
wire \$619 ;
wire \$627 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
wire \$629 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$631 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$633 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$635 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$637 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$639 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire \$641 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$643 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$645 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$647 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$649 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$651 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire \$653 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$655 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$657 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$659 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$661 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$663 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire \$665 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$667 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$669 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$671 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$673 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
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wire \$675 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
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wire \$677 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$679 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$681 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$683 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$685 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$687 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire \$689 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$691 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$693 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$695 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$697 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$699 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire \$701 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [2:0] \$703 ;
wire \$719 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
wire \$721 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$723 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$725 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$727 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$729 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$731 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [1:0] \$733 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$735 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$737 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$739 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$741 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$743 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [1:0] \$745 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$747 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$749 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$751 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$753 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$755 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [1:0] \$757 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [2:0] \$759 ;
wire \$769 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *)
wire \$771 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$773 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$775 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$777 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$779 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$781 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [2:0] \$783 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$785 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$787 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$789 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$791 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$793 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [7:0] \$795 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$797 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$799 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$801 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$803 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$805 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *)
wire [7:0] \$807 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *)
wire [255:0] \$809 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [255:0] \$811 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$813 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$815 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$817 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$819 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$821 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *)
wire [7:0] \$823 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *)
wire [255:0] \$825 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [255:0] \$827 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [255:0] \$829 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [255:0] \$830 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$832 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$834 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$836 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$838 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$840 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *)
wire [7:0] \$842 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *)
wire [255:0] \$844 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [255:0] \$846 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$848 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$850 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$852 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$854 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$856 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *)
wire [7:0] \$858 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *)
wire [255:0] \$860 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [255:0] \$862 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$864 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$866 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$868 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$870 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$872 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [2:0] \$874 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$876 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$878 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$880 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$882 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$884 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [2:0] \$886 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$888 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$890 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$892 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$894 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$896 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [2:0] \$898 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$900 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$902 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$904 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$906 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$908 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [2:0] \$910 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$912 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$914 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$916 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$918 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$920 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [2:0] \$922 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [2:0] \$924 ;
wire [2:0] \$928 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [2:0] \$930 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *)
wire \$932 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$934 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *)
wire \$936 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$938 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
wire \$940 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *)
wire \$942 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *)
wire [9:0] \$944 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *)
wire \$946 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$948 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$950 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$952 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$954 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$956 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$958 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$960 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$962 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$964 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$966 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *)
wire \$968 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$970 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$972 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$974 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$980 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
wire [6:0] \$982 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
wire \$984 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
wire \$987 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$991 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$993 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
wire \$998 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] addr_en;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] \addr_en$1000 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] \addr_en$1021 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] \addr_en$1039 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] \addr_en$1061 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] \addr_en$1081 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] \addr_en$1101 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] \addr_en$1120 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] \addr_en$1138 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [6:0] \addr_en$1154 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [7:0] \addr_en$1228 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [255:0] \addr_en$1256 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [255:0] \addr_en$1276 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [255:0] \addr_en$1296 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [255:0] \addr_en$1316 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [255:0] \addr_en$1336 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [255:0] \addr_en$1356 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [1:0] \addr_en$1403 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [1:0] \addr_en$1419 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [1:0] \addr_en$1435 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \addr_en$1469 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \addr_en$1485 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \addr_en$1501 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \addr_en$1517 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire \addr_en$1553 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire \addr_en$1569 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire \addr_en$1585 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire \addr_en$1601 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \addr_en$1646 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \addr_en$1662 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \addr_en$1678 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \addr_en$1694 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [2:0] \addr_en$1710 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire \addr_en$1754 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire \addr_en$1770 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [1:0] \addr_en$1794 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *)
wire [9:0] \addr_en$1814 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [255:0] addr_en_CR_cr_a_branch0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [255:0] addr_en_CR_cr_a_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [255:0] addr_en_CR_cr_b_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [255:0] addr_en_CR_cr_c_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [7:0] addr_en_CR_full_cr_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [2:0] addr_en_FAST_fast1_branch0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [2:0] addr_en_FAST_fast1_branch0_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [2:0] addr_en_FAST_fast1_spr0_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [2:0] addr_en_FAST_fast1_trap0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [2:0] addr_en_FAST_fast1_trap0_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_alu0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_alu0_10;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_cr0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_cr0_11;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_div0_15;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_div0_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_ldst0_18;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_ldst0_7;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_ldst0_9;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_logical0_13;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_logical0_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_mul0_16;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_mul0_5;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_shiftrot0_17;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_shiftrot0_6;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_shiftrot0_8;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_spr0_14;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_trap0_12;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [6:0] addr_en_INT_rabc_trap0_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [9:0] addr_en_SPR_spr1_spr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [1:0] addr_en_XER_xer_ca_alu0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [1:0] addr_en_XER_xer_ca_shiftrot0_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [1:0] addr_en_XER_xer_ca_spr0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire [2:0] addr_en_XER_xer_ov_spr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire addr_en_XER_xer_so_alu0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire addr_en_XER_xer_so_div0_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire addr_en_XER_xer_so_logical0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire addr_en_XER_xer_so_mul0_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire addr_en_XER_xer_so_shiftrot0_5;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:284" *)
wire addr_en_XER_xer_so_spr0_2;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *)
input bigendian_i;
(* enum_value_1011010001 = "SVSRR0" *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
input [9:0] core_spro;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *)
output core_terminate_o;
reg core_terminate_o = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *)
reg \core_terminate_o$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *)
input [2:0] core_xer_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *)
output corebusy_o;
reg corebusy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" *)
reg [1:0] counter = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:197" *)
reg [1:0] \counter$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [3:0] cr_data_i;
output [63:0] dmi__data_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input dmi__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_CR_cr_a_branch0_1 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_CR_cr_a_branch0_1$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_CR_cr_a_cr0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_CR_cr_a_cr0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_CR_cr_b_cr0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_CR_cr_b_cr0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_CR_cr_c_cr0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_CR_cr_c_cr0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_CR_full_cr_cr0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_CR_full_cr_cr0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_FAST_fast1_branch0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_FAST_fast1_branch0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_FAST_fast1_branch0_3 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_FAST_fast1_branch0_3$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_FAST_fast1_spr0_2 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_FAST_fast1_spr0_2$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_FAST_fast1_trap0_1 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_FAST_fast1_trap0_1$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_FAST_fast1_trap0_4 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_FAST_fast1_trap0_4$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_alu0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_alu0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_alu0_10 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_alu0_10$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_cr0_1 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_cr0_1$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_cr0_11 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_cr0_11$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_div0_15 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_div0_15$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_div0_4 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_div0_4$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_ldst0_18 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_ldst0_18$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_ldst0_7 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_ldst0_7$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_ldst0_9 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_ldst0_9$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_logical0_13 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_logical0_13$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_logical0_3 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_logical0_3$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_mul0_16 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_mul0_16$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_mul0_5 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_mul0_5$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_shiftrot0_17 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_shiftrot0_17$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_shiftrot0_6 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_shiftrot0_6$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_shiftrot0_8 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_shiftrot0_8$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_spr0_14 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_spr0_14$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_trap0_12 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_trap0_12$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_INT_rabc_trap0_2 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_INT_rabc_trap0_2$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_SPR_spr1_spr0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_SPR_spr1_spr0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_ca_alu0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_ca_alu0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_ca_shiftrot0_2 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_ca_shiftrot0_2$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_ca_spr0_1 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_ca_spr0_1$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_ov_spr0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_ov_spr0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_so_alu0_0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_so_alu0_0$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_so_div0_3 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_so_div0_3$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_so_logical0_1 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_so_logical0_1$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_so_mul0_4 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_so_mul0_4$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_so_shiftrot0_5 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_so_shiftrot0_5$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg dp_XER_xer_so_spr0_2 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
reg \dp_XER_xer_so_spr0_2$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
wire ea_ok;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_alu0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_branch0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_cr0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_div0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_ldst0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_logical0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_mul0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_shiftrot0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_spr0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:192" *)
wire en_trap0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [2:0] fast_dest1__addr;
wire [63:0] fast_src1__data_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire fast_src1__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" *)
wire [9:0] fu_enable;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
output [31:0] full_rd2__data_o;
input [2:0] msr__ren;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
wire o_ok;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_CR_cr_a_branch0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_CR_cr_a_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_CR_cr_b_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_CR_cr_c_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_CR_full_cr_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_FAST_fast1_branch0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_FAST_fast1_branch0_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_FAST_fast1_spr0_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_FAST_fast1_trap0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_FAST_fast1_trap0_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_alu0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_alu0_10;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_cr0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_cr0_11;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_div0_15;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_div0_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_ldst0_18;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_ldst0_7;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_ldst0_9;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_logical0_13;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_logical0_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_mul0_16;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_mul0_5;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_shiftrot0_17;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_shiftrot0_6;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_shiftrot0_8;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_spr0_14;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_trap0_12;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_INT_rabc_trap0_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_SPR_spr1_spr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_ca_alu0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_ca_shiftrot0_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_ca_spr0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_ov_spr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_so_alu0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_so_div0_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_so_logical0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_so_mul0_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_so_shiftrot0_5;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
wire pick_XER_xer_so_spr0_2;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *)
input [31:0] raw_insn_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_CR_cr_a_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_CR_cr_b_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_CR_cr_c_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_CR_full_cr_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_FAST_fast1_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_FAST_fast1_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_INT_rabc_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_INT_rabc_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_INT_rabc_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_SPR_spr1_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_XER_xer_ca_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_XER_xer_ov_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:261" *)
wire rdflag_XER_xer_so_0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
wire rdpick_CR_cr_a_en_o;
wire [5:0] rdpick_XER_xer_so_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
wire [5:0] rdpick_XER_xer_so_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_CR_cr_a_branch0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_CR_cr_a_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_CR_cr_b_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_CR_cr_c_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_CR_full_cr_cr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_FAST_fast1_branch0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_FAST_fast1_branch0_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_FAST_fast1_spr0_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_FAST_fast1_trap0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_FAST_fast1_trap0_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_alu0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_alu0_10;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_cr0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_cr0_11;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_div0_15;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_div0_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_ldst0_18;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_ldst0_7;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_ldst0_9;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_logical0_13;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_logical0_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_mul0_16;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_mul0_5;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_shiftrot0_17;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_shiftrot0_6;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_shiftrot0_8;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_spr0_14;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_trap0_12;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_INT_rabc_trap0_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_SPR_spr1_spr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_ca_alu0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_ca_shiftrot0_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_ca_spr0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_ov_spr0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_so_alu0_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_so_div0_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_so_logical0_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_so_mul0_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_so_shiftrot0_5;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
wire rp_XER_xer_so_spr0_2;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [3:0] spr_spr1__addr;
input [2:0] wen;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [2:0] \wen$10 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire wp;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1018 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1036 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1058 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1078 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1098 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1117 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1135 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1151 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1225 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1253 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1273 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1293 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1313 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1333 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1353 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1400 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1416 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1432 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1466 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1482 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1498 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1514 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1550 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1566 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1582 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1598 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1643 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1659 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1675 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1691 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1707 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1751 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1767 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1791 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$1811 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
wire \wp$997 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire wr_pick;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1005 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1026 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1044 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1066 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1086 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1106 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1125 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1143 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1217 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1245 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1265 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1285 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1305 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1325 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1345 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1392 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1408 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1424 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1458 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1474 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1490 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1506 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1542 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1558 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1574 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1590 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1632 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1651 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1667 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1683 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1699 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1743 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1759 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1783 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$1803 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" *)
wire \wr_pick$986 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
reg wr_pick_dly = 1'h0;
wire \wr_pick_rise$995 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
wire \wr_pick_rise$996 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_alu0_cr_a_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_alu0_o_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_alu0_xer_ca_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_alu0_xer_ov_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_alu0_xer_so_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_branch0_fast1_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_branch0_fast1_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_branch0_nia_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_cr0_cr_a_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_cr0_full_cr_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_cr0_o_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_div0_cr_a_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_div0_o_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_div0_xer_ov_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_div0_xer_so_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_ldst0_o_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_ldst0_o_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_logical0_cr_a_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_logical0_o_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_mul0_cr_a_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_mul0_o_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_mul0_xer_ov_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_mul0_xer_so_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_shiftrot0_cr_a_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_shiftrot0_o_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_shiftrot0_xer_ca_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_spr0_fast1_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_spr0_o_0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_spr0_spr1_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_spr0_xer_ca_5;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_spr0_xer_ov_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_spr0_xer_so_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_trap0_fast1_1;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_trap0_fast1_2;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_trap0_msr_4;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_trap0_nia_3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:412" *)
wire wrflag_trap0_o_0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
wire wrpick_CR_cr_a_en_o;
wire [2:0] \xer_wen$171 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [2:0] \xer_wen$173 ;
- assign \$1001 = \wp$997 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
- assign \$1003 = \fus_o_ok$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
- assign \$1006 = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$1001 = \wp$997 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00;
+ assign \$1003 = \fus_o_ok$95 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ;
+ assign \$1006 = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$1010 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1008 ;
assign \$1012 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1010 ;
- assign \$1019 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
- assign \$1022 = \wp$1018 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
- assign \$1024 = \fus_o_ok$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$23 ;
- assign \$1027 = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$1019 = \wr_pick$1005 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
+ assign \$1022 = \wp$1018 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00;
+ assign \$1024 = \fus_o_ok$98 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$23 ;
+ assign \$1027 = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$1031 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1029 ;
assign \$1033 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1031 ;
- assign \$1037 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
- assign \$1040 = \wp$1036 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
- assign \$1042 = \fus_o_ok$101 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
- assign \$1045 = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$1037 = \wr_pick$1026 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
+ assign \$1040 = \wp$1036 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00;
+ assign \$1042 = \fus_o_ok$101 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ;
+ assign \$1045 = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$1049 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1047 ;
assign \$1051 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1049 ;
- assign \$1059 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
- assign \$1062 = \wp$1058 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
- assign \$1064 = \fus_o_ok$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ;
- assign \$1067 = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$1059 = \wr_pick$1044 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
+ assign \$1062 = \wp$1058 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00;
+ assign \$1064 = \fus_o_ok$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ;
+ assign \$1067 = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$1071 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1069 ;
assign \$1073 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1071 ;
- assign \$1079 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
- assign \$1082 = \wp$1078 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
- assign \$1084 = \fus_o_ok$107 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ;
- assign \$1087 = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$1079 = \wr_pick$1066 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
+ assign \$1082 = \wp$1078 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00;
+ assign \$1084 = \fus_o_ok$107 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ;
+ assign \$1087 = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$1091 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1089 ;
assign \$1093 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1091 ;
- assign \$1099 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
- assign \$1102 = \wp$1098 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
- assign \$1104 = \fus_o_ok$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ;
- assign \$1107 = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$1099 = \wr_pick$1086 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
+ assign \$1102 = \wp$1098 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00;
+ assign \$1104 = \fus_o_ok$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$35 ;
+ assign \$1107 = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$1111 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1109 ;
assign \$1113 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1111 ;
- assign \$1118 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
- assign \$1121 = \wp$1117 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
- assign \$1123 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$38 ;
- assign \$1126 = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$1118 = \wr_pick$1106 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
+ assign \$1121 = \wp$1117 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00;
+ assign \$1123 = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$38 ;
+ assign \$1126 = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$1130 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1128 ;
assign \$1132 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1130 ;
- assign \$1136 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
- assign \$1139 = \wp$1135 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
- assign \$1141 = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$38 ;
- assign \$1144 = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$1136 = \wr_pick$1125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
+ assign \$1139 = \wp$1135 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00;
+ assign \$1141 = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$38 ;
+ assign \$1144 = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$1147 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1146 ;
assign \$1149 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1147 ;
- assign \$1152 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
- assign \$1155 = \wp$1151 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_ea : 7'h00;
+ assign \$1152 = \wr_pick$1143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
+ assign \$1155 = \wp$1151 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_ea : 7'h00;
assign \$1158 = fus_dest1_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$115 ;
assign \$1160 = \fus_dest1_o$117 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$118 ;
assign \$1162 = \fus_dest1_o$116 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1160 ;
assign \$1207 = \wp$1117 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1205 ;
assign \$1209 = \$1203 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1207 ;
assign \$1211 = \$1201 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1209 ;
- assign \$1213 = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ;
- assign \$1215 = \fus_cu_wr__rel_o$93 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1];
- assign \$1218 = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_full_cr_en_o;
+ assign \$1213 = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$14 ;
+ assign \$1215 = \fus_cu_wr__rel_o$93 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[1];
+ assign \$1218 = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_full_cr_en_o;
assign \$1221 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1220 ;
assign \$1223 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1221 ;
- assign \$1226 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_full_cr_en_o;
- assign \$1229 = \wp$1225 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_core_cr_wr : 8'h00;
- assign \$1231 = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
- assign \$1233 = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
- assign \$1235 = \fus_cu_wr__rel_o$93 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1];
- assign \$1237 = \fus_cu_wr__rel_o$99 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[4];
- assign \$1239 = \fus_cu_wr__rel_o$105 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6];
- assign \$1241 = \fus_cu_wr__rel_o$108 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7];
- assign \$1243 = \fus_cu_wr__rel_o$111 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8];
- assign \$1246 = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
+ assign \$1226 = \wr_pick$1217 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_full_cr_en_o;
+ assign \$1229 = \wp$1225 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_core_cr_wr : 8'h00;
+ assign \$1231 = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o;
+ assign \$1233 = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0];
+ assign \$1235 = \fus_cu_wr__rel_o$93 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[1];
+ assign \$1237 = \fus_cu_wr__rel_o$99 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[4];
+ assign \$1239 = \fus_cu_wr__rel_o$105 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6];
+ assign \$1241 = \fus_cu_wr__rel_o$108 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7];
+ assign \$1243 = \fus_cu_wr__rel_o$111 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[8];
+ assign \$1246 = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o;
assign \$1249 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1248 ;
assign \$1251 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1249 ;
- assign \$1254 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
+ assign \$1254 = \wr_pick$1245 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o;
assign \$1257 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
assign \$1259 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1257 ;
- assign \$1261 = \wp$1253 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1259 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
- assign \$1263 = \fus_cr_a_ok$122 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ;
- assign \$1266 = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
+ assign \$1261 = \wp$1253 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1259 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$1263 = \fus_cr_a_ok$122 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$14 ;
+ assign \$1266 = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o;
assign \$1269 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1268 ;
assign \$1271 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1269 ;
- assign \$1274 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
+ assign \$1274 = \wr_pick$1265 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o;
assign \$1277 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
assign \$1279 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1277 ;
- assign \$1281 = \wp$1273 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1279 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
- assign \$1283 = \fus_cr_a_ok$123 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$23 ;
- assign \$1286 = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
+ assign \$1281 = \wp$1273 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1279 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$1283 = \fus_cr_a_ok$123 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$23 ;
+ assign \$1286 = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o;
assign \$1289 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1288 ;
assign \$1291 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1289 ;
- assign \$1294 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
+ assign \$1294 = \wr_pick$1285 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o;
assign \$1297 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
assign \$1299 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1297 ;
- assign \$1301 = \wp$1293 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1299 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
- assign \$1303 = \fus_cr_a_ok$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ;
- assign \$1306 = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
+ assign \$1301 = \wp$1293 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1299 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$1303 = \fus_cr_a_ok$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ;
+ assign \$1306 = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o;
assign \$1309 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1308 ;
assign \$1311 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1309 ;
- assign \$1314 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
+ assign \$1314 = \wr_pick$1305 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o;
assign \$1317 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
assign \$1319 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1317 ;
- assign \$1321 = \wp$1313 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1319 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
- assign \$1323 = \fus_cr_a_ok$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ;
- assign \$1326 = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
+ assign \$1321 = \wp$1313 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1319 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$1323 = \fus_cr_a_ok$125 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ;
+ assign \$1326 = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o;
assign \$1329 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1328 ;
assign \$1331 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1329 ;
- assign \$1334 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
+ assign \$1334 = \wr_pick$1325 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o;
assign \$1337 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
assign \$1339 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1337 ;
- assign \$1341 = \wp$1333 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1339 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
- assign \$1343 = \fus_cr_a_ok$126 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ;
- assign \$1346 = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
+ assign \$1341 = \wp$1333 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1339 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$1343 = \fus_cr_a_ok$126 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$35 ;
+ assign \$1346 = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_CR_cr_a_en_o;
assign \$1349 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1348 ;
assign \$1351 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1349 ;
- assign \$1354 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
+ assign \$1354 = \wr_pick$1345 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_CR_cr_a_en_o;
assign \$1357 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
assign \$1359 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1357 ;
- assign \$1361 = \wp$1353 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1359 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$1361 = \wp$1353 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) \$1359 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
assign \$1363 = fus_dest3_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$128 ;
assign \$1365 = \fus_dest2_o$127 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1363 ;
assign \$1367 = \fus_dest2_o$130 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$131 ;
assign \$1378 = \addr_en$1336 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1356 ;
assign \$1380 = \addr_en$1316 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1378 ;
assign \$1382 = \$1376 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1380 ;
- assign \$1384 = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
- assign \$1386 = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
- assign \$1388 = \fus_cu_wr__rel_o$102 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
- assign \$1390 = \fus_cu_wr__rel_o$111 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8];
- assign \$1393 = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o;
+ assign \$1384 = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o;
+ assign \$1386 = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0];
+ assign \$1388 = \fus_cu_wr__rel_o$102 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5];
+ assign \$1390 = \fus_cu_wr__rel_o$111 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[8];
+ assign \$1393 = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ca_en_o;
assign \$1396 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1395 ;
assign \$1398 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1396 ;
- assign \$1401 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o;
- assign \$1404 = \wp$1400 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0;
- assign \$1406 = \fus_xer_ca_ok$132 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
- assign \$1409 = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o;
+ assign \$1401 = \wr_pick$1392 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ca_en_o;
+ assign \$1404 = \wp$1400 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0;
+ assign \$1406 = \fus_xer_ca_ok$132 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ;
+ assign \$1409 = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ca_en_o;
assign \$1412 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1411 ;
assign \$1414 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1412 ;
- assign \$1417 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o;
- assign \$1420 = \wp$1416 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0;
- assign \$1422 = \fus_xer_ca_ok$133 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ;
- assign \$1425 = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o;
+ assign \$1417 = \wr_pick$1408 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ca_en_o;
+ assign \$1420 = \wp$1416 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0;
+ assign \$1422 = \fus_xer_ca_ok$133 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$35 ;
+ assign \$1425 = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ca_en_o;
assign \$1428 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1427 ;
assign \$1430 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1428 ;
- assign \$1433 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o;
- assign \$1436 = \wp$1432 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0;
+ assign \$1433 = \wr_pick$1424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ca_en_o;
+ assign \$1436 = \wp$1432 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0;
assign \$1438 = fus_dest6_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$135 ;
assign \$1440 = \fus_dest3_o$134 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1438 ;
assign \$1443 = \addr_en$1419 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1435 ;
assign \$1445 = \addr_en$1403 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1443 ;
assign \$1442 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1445 ;
- assign \$1448 = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
- assign \$1450 = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
- assign \$1452 = \fus_cu_wr__rel_o$102 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
- assign \$1454 = \fus_cu_wr__rel_o$105 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6];
- assign \$1456 = \fus_cu_wr__rel_o$108 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7];
- assign \$1459 = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o;
+ assign \$1448 = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o;
+ assign \$1450 = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0];
+ assign \$1452 = \fus_cu_wr__rel_o$102 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5];
+ assign \$1454 = \fus_cu_wr__rel_o$105 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6];
+ assign \$1456 = \fus_cu_wr__rel_o$108 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7];
+ assign \$1459 = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o;
assign \$1462 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1461 ;
assign \$1464 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1462 ;
- assign \$1467 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o;
- assign \$1470 = \wp$1466 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0;
- assign \$1472 = \fus_xer_ov_ok$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
- assign \$1475 = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o;
+ assign \$1467 = \wr_pick$1458 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o;
+ assign \$1470 = \wp$1466 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0;
+ assign \$1472 = \fus_xer_ov_ok$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ;
+ assign \$1475 = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o;
assign \$1478 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1477 ;
assign \$1480 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1478 ;
- assign \$1483 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o;
- assign \$1486 = \wp$1482 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0;
- assign \$1488 = \fus_xer_ov_ok$137 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ;
- assign \$1491 = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o;
+ assign \$1483 = \wr_pick$1474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o;
+ assign \$1486 = \wp$1482 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0;
+ assign \$1488 = \fus_xer_ov_ok$137 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ;
+ assign \$1491 = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o;
assign \$1494 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1493 ;
assign \$1496 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1494 ;
- assign \$1499 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o;
- assign \$1502 = \wp$1498 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0;
- assign \$1504 = \fus_xer_ov_ok$138 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ;
- assign \$1507 = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o;
+ assign \$1499 = \wr_pick$1490 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o;
+ assign \$1502 = \wp$1498 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0;
+ assign \$1504 = \fus_xer_ov_ok$138 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ;
+ assign \$1507 = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_ov_en_o;
assign \$1510 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1509 ;
assign \$1512 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1510 ;
- assign \$1515 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o;
- assign \$1518 = \wp$1514 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0;
+ assign \$1515 = \wr_pick$1506 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_ov_en_o;
+ assign \$1518 = \wp$1514 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 3'h4 : 3'h0;
assign \$1520 = fus_dest4_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) fus_dest5_o;
assign \$1522 = \fus_dest3_o$139 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$140 ;
assign \$1524 = \$1520 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1522 ;
assign \$1526 = \addr_en$1469 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1485 ;
assign \$1528 = \addr_en$1501 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1517 ;
assign \$1530 = \$1526 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1528 ;
- assign \$1532 = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
- assign \$1534 = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
- assign \$1536 = \fus_cu_wr__rel_o$102 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
- assign \$1538 = \fus_cu_wr__rel_o$105 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6];
- assign \$1540 = \fus_cu_wr__rel_o$108 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7];
- assign \$1543 = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o;
+ assign \$1532 = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o;
+ assign \$1534 = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0];
+ assign \$1536 = \fus_cu_wr__rel_o$102 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5];
+ assign \$1538 = \fus_cu_wr__rel_o$105 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6];
+ assign \$1540 = \fus_cu_wr__rel_o$108 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7];
+ assign \$1543 = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o;
assign \$1546 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1545 ;
assign \$1548 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1546 ;
- assign \$1551 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o;
- assign \$1554 = \wp$1550 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
- assign \$1556 = \fus_xer_so_ok$141 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
- assign \$1559 = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o;
+ assign \$1551 = \wr_pick$1542 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o;
+ assign \$1554 = \wp$1550 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0;
+ assign \$1556 = \fus_xer_so_ok$141 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ;
+ assign \$1559 = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o;
assign \$1562 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1561 ;
assign \$1564 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1562 ;
- assign \$1567 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o;
- assign \$1570 = \wp$1566 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
- assign \$1572 = \fus_xer_so_ok$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ;
- assign \$1575 = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o;
+ assign \$1567 = \wr_pick$1558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o;
+ assign \$1570 = \wp$1566 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0;
+ assign \$1572 = \fus_xer_so_ok$142 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$29 ;
+ assign \$1575 = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o;
assign \$1578 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1577 ;
assign \$1580 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1578 ;
- assign \$1583 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o;
- assign \$1586 = \wp$1582 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
- assign \$1588 = \fus_xer_so_ok$143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ;
- assign \$1591 = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o;
+ assign \$1583 = \wr_pick$1574 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o;
+ assign \$1586 = \wp$1582 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0;
+ assign \$1588 = \fus_xer_so_ok$143 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$32 ;
+ assign \$1591 = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_XER_xer_so_en_o;
assign \$1594 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1593 ;
assign \$1596 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1594 ;
- assign \$1599 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o;
- assign \$1602 = \wp$1598 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
+ assign \$1599 = \wr_pick$1590 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_XER_xer_so_en_o;
+ assign \$1602 = \wp$1598 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0;
assign \$1605 = \fus_dest5_o$144 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$145 ;
assign \$1607 = \fus_dest4_o$146 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$147 ;
assign \$1609 = \$1605 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1607 ;
assign \$1615 = \addr_en$1585 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1601 ;
assign \$1617 = \$1613 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1615 ;
assign \$1612 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1617 ;
- assign \$1620 = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ;
- assign \$1622 = \fus_cu_wr__rel_o$148 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2];
- assign \$1624 = \fus_cu_wr__rel_o$96 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
- assign \$1626 = \fus_cu_wr__rel_o$102 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
- assign \$1628 = \fus_cu_wr__rel_o$148 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2];
- assign \$1630 = \fus_cu_wr__rel_o$96 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
- assign \$1633 = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
+ assign \$1620 = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$17 ;
+ assign \$1622 = \fus_cu_wr__rel_o$148 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[2];
+ assign \$1624 = \fus_cu_wr__rel_o$96 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3];
+ assign \$1626 = \fus_cu_wr__rel_o$102 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5];
+ assign \$1628 = \fus_cu_wr__rel_o$148 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[2];
+ assign \$1630 = \fus_cu_wr__rel_o$96 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3];
+ assign \$1633 = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o;
assign \$1637 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1635 ;
assign \$1639 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1637 ;
- assign \$1644 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
- assign \$1647 = \wp$1643 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0;
- assign \$1649 = \fus_fast1_ok$150 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
- assign \$1652 = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
+ assign \$1644 = \wr_pick$1632 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o;
+ assign \$1647 = \wp$1643 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto1 : 3'h0;
+ assign \$1649 = \fus_fast1_ok$150 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ;
+ assign \$1652 = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o;
assign \$1655 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1654 ;
assign \$1657 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1655 ;
- assign \$1660 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
- assign \$1663 = \wp$1659 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0;
- assign \$1665 = \fus_fast1_ok$151 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
- assign \$1668 = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
+ assign \$1660 = \wr_pick$1651 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o;
+ assign \$1663 = \wp$1659 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto1 : 3'h0;
+ assign \$1665 = \fus_fast1_ok$151 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ;
+ assign \$1668 = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o;
assign \$1671 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1670 ;
assign \$1673 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1671 ;
- assign \$1676 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
- assign \$1679 = \wp$1675 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0;
- assign \$1681 = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ;
- assign \$1684 = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
+ assign \$1676 = \wr_pick$1667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o;
+ assign \$1679 = \wp$1675 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto1 : 3'h0;
+ assign \$1681 = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$17 ;
+ assign \$1684 = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o;
assign \$1687 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1686 ;
assign \$1689 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1687 ;
- assign \$1692 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
- assign \$1695 = \wp$1691 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto2 : 3'h0;
- assign \$1697 = \fus_fast2_ok$152 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
- assign \$1700 = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
+ assign \$1692 = \wr_pick$1683 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o;
+ assign \$1695 = \wp$1691 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto2 : 3'h0;
+ assign \$1697 = \fus_fast2_ok$152 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ;
+ assign \$1700 = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_FAST_fast1_en_o;
assign \$1703 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1702 ;
assign \$1705 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1703 ;
- assign \$1708 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
- assign \$1711 = \wp$1707 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto2 : 3'h0;
+ assign \$1708 = \wr_pick$1699 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_FAST_fast1_en_o;
+ assign \$1711 = \wp$1707 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_fasto2 : 3'h0;
assign \$1713 = \fus_dest1_o$153 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$154 ;
assign \$1715 = \fus_dest2_o$156 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$157 ;
assign \$1717 = \fus_dest3_o$155 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1715 ;
assign \$1731 = \wp$1691 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1707 ;
assign \$1733 = \wp$1675 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1731 ;
assign \$1735 = \$1729 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1733 ;
- assign \$1737 = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ;
- assign \$1739 = \fus_cu_wr__rel_o$148 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2];
- assign \$1741 = \fus_cu_wr__rel_o$96 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
- assign \$1744 = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_nia_en_o;
+ assign \$1737 = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$17 ;
+ assign \$1739 = \fus_cu_wr__rel_o$148 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[2];
+ assign \$1741 = \fus_cu_wr__rel_o$96 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3];
+ assign \$1744 = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_STATE_nia_en_o;
assign \$1747 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1746 ;
assign \$1749 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1747 ;
- assign \$1752 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_nia_en_o;
- assign \$1755 = \wp$1751 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
- assign \$1757 = \fus_nia_ok$158 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
- assign \$1760 = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_nia_en_o;
+ assign \$1752 = \wr_pick$1743 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_STATE_nia_en_o;
+ assign \$1755 = \wp$1751 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0;
+ assign \$1757 = \fus_nia_ok$158 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ;
+ assign \$1760 = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_STATE_nia_en_o;
assign \$1763 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1762 ;
assign \$1765 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1763 ;
- assign \$1768 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_nia_en_o;
- assign \$1771 = \wp$1767 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
+ assign \$1768 = \wr_pick$1759 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_STATE_nia_en_o;
+ assign \$1771 = \wp$1767 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 1'h1 : 1'h0;
assign \$1773 = \fus_dest3_o$159 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$160 ;
assign \$1776 = \addr_en$1754 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1770 ;
assign \$1775 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \$1776 ;
- assign \$1779 = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
- assign \$1781 = \fus_cu_wr__rel_o$96 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
- assign \$1784 = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_msr_en_o;
+ assign \$1779 = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$20 ;
+ assign \$1781 = \fus_cu_wr__rel_o$96 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3];
+ assign \$1784 = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_STATE_msr_en_o;
assign \$1787 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1786 ;
assign \$1789 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1787 ;
- assign \$1792 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_msr_en_o;
- assign \$1795 = \wp$1791 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0;
- assign \$1797 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) \addr_en$1794 ;
- assign \$1799 = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
- assign \$1801 = \fus_cu_wr__rel_o$102 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
- assign \$1804 = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_SPR_spr1_en_o;
+ assign \$1792 = \wr_pick$1783 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_STATE_msr_en_o;
+ assign \$1795 = \wp$1791 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) 2'h2 : 2'h0;
+ assign \$1797 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:427" *) \addr_en$1794 ;
+ assign \$1799 = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$26 ;
+ assign \$1801 = \fus_cu_wr__rel_o$102 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5];
+ assign \$1804 = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_SPR_spr1_en_o;
assign \$1807 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1806 ;
assign \$1809 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1807 ;
- assign \$1812 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_SPR_spr1_en_o;
- assign \$1815 = \wp$1811 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_spro : 10'h000;
- assign \$182 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 2'h2;
- assign \$181 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$182 ;
- assign \$186 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 7'h40;
- assign \$185 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$186 ;
- assign \$190 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 6'h20;
- assign \$189 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$190 ;
- assign \$194 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 8'h80;
- assign \$193 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$194 ;
- assign \$198 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 5'h10;
- assign \$197 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$198 ;
- assign \$202 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 11'h400;
- assign \$201 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$202 ;
- assign \$206 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 10'h200;
- assign \$205 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$206 ;
- assign \$210 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 9'h100;
- assign \$209 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$210 ;
- assign \$214 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 4'h8;
- assign \$213 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$214 ;
- assign \$218 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 3'h4;
- assign \$217 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$218 ;
- assign \$221 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h0;
- assign \$224 = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *) 1'h1;
- assign \$226 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h0;
+ assign \$1812 = \wr_pick$1803 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_SPR_spr1_en_o;
+ assign \$1815 = \wp$1811 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_spro : 10'h000;
+ assign \$182 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 2'h2;
+ assign \$181 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$182 ;
+ assign \$186 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 7'h40;
+ assign \$185 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$186 ;
+ assign \$190 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 6'h20;
+ assign \$189 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$190 ;
+ assign \$194 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 8'h80;
+ assign \$193 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$194 ;
+ assign \$198 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 5'h10;
+ assign \$197 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$198 ;
+ assign \$202 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 11'h400;
+ assign \$201 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$202 ;
+ assign \$206 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 10'h200;
+ assign \$205 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$206 ;
+ assign \$210 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 9'h100;
+ assign \$209 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$210 ;
+ assign \$214 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 4'h8;
+ assign \$213 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$214 ;
+ assign \$218 = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) 3'h4;
+ assign \$217 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *) \$218 ;
+ assign \$221 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) 1'h0;
+ assign \$224 = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h1;
+ assign \$226 = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *) 1'h0;
assign \$229 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
assign \$231 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$233 = \$231 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$243 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
assign \$245 = \$243 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
assign \$247 = \$241 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$245 ;
- assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$247 , \$239 , core_reg2_ok, core_reg1_ok };
- assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok };
- assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok };
- assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok };
+ assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$247 , \$239 , core_reg2_ok, core_reg1_ok };
+ assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok };
+ assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok };
+ assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok };
assign \$257 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
assign \$259 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$261 = \$259 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$263 = \$257 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$261 ;
assign \$265 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
assign \$267 = \$263 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$265 ;
- assign \$256 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$267 , core_reg2_ok, core_reg1_ok };
+ assign \$256 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$267 , core_reg2_ok, core_reg1_ok };
assign \$271 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
assign \$273 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$275 = \$273 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$293 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
assign \$295 = \$293 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
assign \$297 = \$291 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$295 ;
- assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$297 , \$289 , \$281 , core_fast1_ok, core_spr1_ok, core_reg1_ok };
+ assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$297 , \$289 , \$281 , core_fast1_ok, core_spr1_ok, core_reg1_ok };
assign \$301 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
assign \$303 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$305 = \$303 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$307 = \$301 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$305 ;
assign \$309 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
assign \$311 = \$307 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$309 ;
- assign \$300 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$311 , core_reg2_ok, core_reg1_ok };
+ assign \$300 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$311 , core_reg2_ok, core_reg1_ok };
assign \$315 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
assign \$317 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$319 = \$317 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$321 = \$315 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$319 ;
assign \$323 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
assign \$325 = \$321 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$323 ;
- assign \$314 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$325 , core_reg2_ok, core_reg1_ok };
+ assign \$314 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$325 , core_reg2_ok, core_reg1_ok };
assign \$329 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
assign \$331 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$333 = \$331 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$343 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
assign \$345 = \$343 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
assign \$347 = \$341 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$345 ;
- assign \$328 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$347 , \$339 , core_reg3_ok, core_reg2_ok, core_reg1_ok };
- assign \$350 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok };
- assign \$352 = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0];
- assign \$354 = \$352 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
- assign \$356 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_alu0_0;
- assign \$358 = \$354 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$356 ;
- assign \$360 = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$362 = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
- assign \$364 = \fus_cu_rd__rel_o$40 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
- assign \$366 = \$364 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
- assign \$368 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_cr0_1;
- assign \$370 = \$366 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$368 ;
- assign \$372 = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$374 = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
- assign \$376 = \fus_cu_rd__rel_o$43 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3];
- assign \$378 = \$376 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
- assign \$380 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_trap0_2;
- assign \$382 = \$378 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$380 ;
- assign \$384 = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$386 = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
- assign \$388 = \fus_cu_rd__rel_o$46 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4];
- assign \$390 = \$388 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
- assign \$392 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_logical0_3;
- assign \$394 = \$390 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$392 ;
- assign \$396 = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$398 = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
- assign \$400 = \fus_cu_rd__rel_o$49 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6];
- assign \$402 = \$400 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
- assign \$404 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_div0_4;
- assign \$406 = \$402 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$404 ;
- assign \$408 = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$410 = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
- assign \$412 = \fus_cu_rd__rel_o$52 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7];
- assign \$414 = \$412 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
- assign \$416 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_mul0_5;
- assign \$418 = \$414 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$416 ;
- assign \$420 = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$422 = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
- assign \$424 = \fus_cu_rd__rel_o$55 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
- assign \$426 = \$424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
- assign \$428 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_6;
- assign \$430 = \$426 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$428 ;
- assign \$432 = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$434 = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
- assign \$436 = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9];
- assign \$438 = \$436 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
- assign \$440 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_7;
- assign \$442 = \$438 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$440 ;
- assign \$444 = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$446 = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
- assign \$448 = \fus_cu_rd__rel_o$55 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
- assign \$450 = \$448 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_1;
- assign \$452 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_8;
- assign \$454 = \$450 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$452 ;
- assign \$456 = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$458 = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg3 : 7'h00;
- assign \$460 = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9];
- assign \$462 = \$460 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_1;
- assign \$464 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_9;
- assign \$466 = \$462 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$464 ;
- assign \$468 = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$470 = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg3 : 7'h00;
- assign \$472 = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0];
- assign \$474 = \$472 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
- assign \$476 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_alu0_10;
- assign \$478 = \$474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$476 ;
- assign \$480 = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$482 = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
- assign \$484 = \fus_cu_rd__rel_o$40 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
- assign \$486 = \$484 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
- assign \$488 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_cr0_11;
- assign \$490 = \$486 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$488 ;
- assign \$492 = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$494 = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
- assign \$496 = \fus_cu_rd__rel_o$43 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3];
- assign \$498 = \$496 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
- assign \$500 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_trap0_12;
- assign \$502 = \$498 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$500 ;
- assign \$504 = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$506 = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
- assign \$508 = \fus_cu_rd__rel_o$46 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4];
- assign \$510 = \$508 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
- assign \$512 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_logical0_13;
- assign \$514 = \$510 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$512 ;
- assign \$516 = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$518 = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
- assign \$520 = \fus_cu_rd__rel_o$65 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
- assign \$522 = \$520 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
- assign \$524 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_spr0_14;
- assign \$526 = \$522 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$524 ;
- assign \$528 = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$530 = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
- assign \$532 = \fus_cu_rd__rel_o$49 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6];
- assign \$534 = \$532 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
- assign \$536 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_div0_15;
- assign \$538 = \$534 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$536 ;
- assign \$540 = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$542 = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
- assign \$544 = \fus_cu_rd__rel_o$52 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7];
- assign \$546 = \$544 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
- assign \$548 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_mul0_16;
- assign \$550 = \$546 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$548 ;
- assign \$552 = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$554 = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
- assign \$556 = \fus_cu_rd__rel_o$55 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
- assign \$558 = \$556 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
- assign \$560 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_17;
- assign \$562 = \$558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$560 ;
- assign \$564 = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$566 = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
- assign \$568 = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9];
- assign \$570 = \$568 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
- assign \$572 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_18;
- assign \$574 = \$570 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$572 ;
- assign \$576 = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
- assign \$578 = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
+ assign \$328 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { \$347 , \$339 , core_reg3_ok, core_reg2_ok, core_reg1_ok };
+ assign \$350 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:229" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok };
+ assign \$352 = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0];
+ assign \$354 = \$352 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0;
+ assign \$356 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_alu0_0;
+ assign \$358 = \$354 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$356 ;
+ assign \$360 = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$362 = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00;
+ assign \$364 = \fus_cu_rd__rel_o$40 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1];
+ assign \$366 = \$364 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0;
+ assign \$368 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_cr0_1;
+ assign \$370 = \$366 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$368 ;
+ assign \$372 = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$374 = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00;
+ assign \$376 = \fus_cu_rd__rel_o$43 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3];
+ assign \$378 = \$376 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0;
+ assign \$380 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_trap0_2;
+ assign \$382 = \$378 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$380 ;
+ assign \$384 = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$386 = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00;
+ assign \$388 = \fus_cu_rd__rel_o$46 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[4];
+ assign \$390 = \$388 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0;
+ assign \$392 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_logical0_3;
+ assign \$394 = \$390 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$392 ;
+ assign \$396 = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$398 = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00;
+ assign \$400 = \fus_cu_rd__rel_o$49 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[6];
+ assign \$402 = \$400 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0;
+ assign \$404 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_div0_4;
+ assign \$406 = \$402 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$404 ;
+ assign \$408 = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$410 = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00;
+ assign \$412 = \fus_cu_rd__rel_o$52 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[7];
+ assign \$414 = \$412 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0;
+ assign \$416 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_mul0_5;
+ assign \$418 = \$414 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$416 ;
+ assign \$420 = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$422 = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00;
+ assign \$424 = \fus_cu_rd__rel_o$55 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8];
+ assign \$426 = \$424 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0;
+ assign \$428 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_shiftrot0_6;
+ assign \$430 = \$426 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$428 ;
+ assign \$432 = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$434 = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00;
+ assign \$436 = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[9];
+ assign \$438 = \$436 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_0;
+ assign \$440 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_ldst0_7;
+ assign \$442 = \$438 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$440 ;
+ assign \$444 = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$446 = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg2 : 7'h00;
+ assign \$448 = \fus_cu_rd__rel_o$55 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8];
+ assign \$450 = \$448 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_1;
+ assign \$452 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_shiftrot0_8;
+ assign \$454 = \$450 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$452 ;
+ assign \$456 = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$458 = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg3 : 7'h00;
+ assign \$460 = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[9];
+ assign \$462 = \$460 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_1;
+ assign \$464 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_ldst0_9;
+ assign \$466 = \$462 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$464 ;
+ assign \$468 = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$470 = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg3 : 7'h00;
+ assign \$472 = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0];
+ assign \$474 = \$472 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2;
+ assign \$476 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_alu0_10;
+ assign \$478 = \$474 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$476 ;
+ assign \$480 = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$482 = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00;
+ assign \$484 = \fus_cu_rd__rel_o$40 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1];
+ assign \$486 = \$484 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2;
+ assign \$488 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_cr0_11;
+ assign \$490 = \$486 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$488 ;
+ assign \$492 = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$494 = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00;
+ assign \$496 = \fus_cu_rd__rel_o$43 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3];
+ assign \$498 = \$496 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2;
+ assign \$500 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_trap0_12;
+ assign \$502 = \$498 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$500 ;
+ assign \$504 = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$506 = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00;
+ assign \$508 = \fus_cu_rd__rel_o$46 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[4];
+ assign \$510 = \$508 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2;
+ assign \$512 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_logical0_13;
+ assign \$514 = \$510 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$512 ;
+ assign \$516 = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$518 = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00;
+ assign \$520 = \fus_cu_rd__rel_o$65 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5];
+ assign \$522 = \$520 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2;
+ assign \$524 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_spr0_14;
+ assign \$526 = \$522 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$524 ;
+ assign \$528 = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$530 = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00;
+ assign \$532 = \fus_cu_rd__rel_o$49 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[6];
+ assign \$534 = \$532 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2;
+ assign \$536 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_div0_15;
+ assign \$538 = \$534 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$536 ;
+ assign \$540 = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$542 = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00;
+ assign \$544 = \fus_cu_rd__rel_o$52 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[7];
+ assign \$546 = \$544 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2;
+ assign \$548 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_mul0_16;
+ assign \$550 = \$546 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$548 ;
+ assign \$552 = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$554 = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00;
+ assign \$556 = \fus_cu_rd__rel_o$55 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8];
+ assign \$558 = \$556 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2;
+ assign \$560 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_shiftrot0_17;
+ assign \$562 = \$558 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$560 ;
+ assign \$564 = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$566 = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00;
+ assign \$568 = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[9];
+ assign \$570 = \$568 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_INT_rabc_2;
+ assign \$572 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_INT_rabc_ldst0_18;
+ assign \$574 = \$570 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$572 ;
+ assign \$576 = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_INT_rabc_en_o;
+ assign \$578 = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_reg1 : 7'h00;
assign \$581 = addr_en_INT_rabc_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_cr0_1;
assign \$583 = addr_en_INT_rabc_trap0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_3;
assign \$585 = \$581 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$583 ;
assign \$611 = \$605 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$609 ;
assign \$613 = \$603 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$611 ;
assign \$615 = \$595 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$613 ;
- assign \$617 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 };
+ assign \$617 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 };
assign \$619 = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
assign \$621 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$623 = \$621 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
assign \$625 = \$619 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$623 ;
assign \$627 = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
assign \$629 = \$625 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$627 ;
- assign \$631 = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0];
- assign \$633 = \$631 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
- assign \$635 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_alu0_0;
- assign \$637 = \$633 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$635 ;
- assign \$639 = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
- assign \$641 = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
- assign \$643 = \fus_cu_rd__rel_o$46 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4];
- assign \$645 = \$643 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
- assign \$647 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_logical0_1;
- assign \$649 = \$645 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$647 ;
- assign \$651 = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
- assign \$653 = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
- assign \$655 = \fus_cu_rd__rel_o$65 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
- assign \$657 = \$655 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
- assign \$659 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_spr0_2;
- assign \$661 = \$657 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$659 ;
- assign \$663 = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
- assign \$665 = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
- assign \$667 = \fus_cu_rd__rel_o$49 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6];
- assign \$669 = \$667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
- assign \$671 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_div0_3;
- assign \$673 = \$669 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$671 ;
- assign \$675 = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
- assign \$677 = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
- assign \$679 = \fus_cu_rd__rel_o$52 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7];
- assign \$681 = \$679 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
- assign \$683 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_mul0_4;
- assign \$685 = \$681 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$683 ;
- assign \$687 = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
- assign \$689 = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
- assign \$691 = \fus_cu_rd__rel_o$55 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
- assign \$693 = \$691 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
- assign \$695 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_shiftrot0_5;
- assign \$697 = \$693 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$695 ;
- assign \$699 = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
- assign \$701 = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
+ assign \$631 = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0];
+ assign \$633 = \$631 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0;
+ assign \$635 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_alu0_0;
+ assign \$637 = \$633 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$635 ;
+ assign \$639 = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o;
+ assign \$641 = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0;
+ assign \$643 = \fus_cu_rd__rel_o$46 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[4];
+ assign \$645 = \$643 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0;
+ assign \$647 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_logical0_1;
+ assign \$649 = \$645 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$647 ;
+ assign \$651 = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o;
+ assign \$653 = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0;
+ assign \$655 = \fus_cu_rd__rel_o$65 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5];
+ assign \$657 = \$655 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0;
+ assign \$659 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_spr0_2;
+ assign \$661 = \$657 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$659 ;
+ assign \$663 = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o;
+ assign \$665 = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0;
+ assign \$667 = \fus_cu_rd__rel_o$49 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[6];
+ assign \$669 = \$667 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0;
+ assign \$671 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_div0_3;
+ assign \$673 = \$669 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$671 ;
+ assign \$675 = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o;
+ assign \$677 = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0;
+ assign \$679 = \fus_cu_rd__rel_o$52 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[7];
+ assign \$681 = \$679 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0;
+ assign \$683 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_mul0_4;
+ assign \$685 = \$681 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$683 ;
+ assign \$687 = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o;
+ assign \$689 = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0;
+ assign \$691 = \fus_cu_rd__rel_o$55 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8];
+ assign \$693 = \$691 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_so_0;
+ assign \$695 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_so_shiftrot0_5;
+ assign \$697 = \$693 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$695 ;
+ assign \$699 = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_so_en_o;
+ assign \$701 = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 1'h1 : 1'h0;
assign \$704 = addr_en_XER_xer_so_logical0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_spr0_2;
assign \$706 = addr_en_XER_xer_so_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$704 ;
assign \$708 = addr_en_XER_xer_so_mul0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_shiftrot0_5;
assign \$717 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
assign \$719 = \$717 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
assign \$721 = \$715 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$719 ;
- assign \$723 = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0];
- assign \$725 = \$723 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0;
- assign \$727 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_alu0_0;
- assign \$729 = \$725 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$727 ;
- assign \$731 = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o;
- assign \$733 = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0;
- assign \$735 = \fus_cu_rd__rel_o$65 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
- assign \$737 = \$735 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0;
- assign \$739 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_spr0_1;
- assign \$741 = \$737 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$739 ;
- assign \$743 = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o;
- assign \$745 = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0;
- assign \$747 = \fus_cu_rd__rel_o$55 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
- assign \$749 = \$747 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0;
- assign \$751 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_shiftrot0_2;
- assign \$753 = \$749 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$751 ;
- assign \$755 = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o;
- assign \$757 = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0;
+ assign \$723 = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[0];
+ assign \$725 = \$723 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ca_0;
+ assign \$727 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ca_alu0_0;
+ assign \$729 = \$725 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$727 ;
+ assign \$731 = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ca_en_o;
+ assign \$733 = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 2'h2 : 2'h0;
+ assign \$735 = \fus_cu_rd__rel_o$65 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5];
+ assign \$737 = \$735 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ca_0;
+ assign \$739 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ca_spr0_1;
+ assign \$741 = \$737 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$739 ;
+ assign \$743 = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ca_en_o;
+ assign \$745 = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 2'h2 : 2'h0;
+ assign \$747 = \fus_cu_rd__rel_o$55 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[8];
+ assign \$749 = \$747 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ca_0;
+ assign \$751 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ca_shiftrot0_2;
+ assign \$753 = \$749 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$751 ;
+ assign \$755 = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ca_en_o;
+ assign \$757 = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 2'h2 : 2'h0;
assign \$760 = addr_en_XER_xer_ca_spr0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_ca_shiftrot0_2;
assign \$762 = addr_en_XER_xer_ca_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$760 ;
assign \$759 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$762 ;
assign \$767 = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2;
assign \$769 = \$767 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2;
assign \$771 = \$765 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) \$769 ;
- assign \$773 = \fus_cu_rd__rel_o$65 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
- assign \$775 = \$773 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ov_0;
- assign \$777 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ov_spr0_0;
- assign \$779 = \$775 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$777 ;
- assign \$781 = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ov_en_o;
- assign \$783 = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 3'h4 : 3'h0;
- assign \$785 = \fus_cu_rd__rel_o$40 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
- assign \$787 = \$785 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_full_cr_0;
- assign \$789 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_full_cr_cr0_0;
- assign \$791 = \$787 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$789 ;
- assign \$793 = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_full_cr_en_o;
- assign \$795 = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_core_cr_rd : 8'h00;
- assign \$797 = \fus_cu_rd__rel_o$40 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
- assign \$799 = \$797 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_a_0;
- assign \$801 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_a_cr0_0;
- assign \$803 = \$799 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$801 ;
- assign \$805 = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_a_en_o;
+ assign \$773 = \fus_cu_rd__rel_o$65 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5];
+ assign \$775 = \$773 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_XER_xer_ov_0;
+ assign \$777 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_XER_xer_ov_spr0_0;
+ assign \$779 = \$775 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$777 ;
+ assign \$781 = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_XER_xer_ov_en_o;
+ assign \$783 = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) 3'h4 : 3'h0;
+ assign \$785 = \fus_cu_rd__rel_o$40 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1];
+ assign \$787 = \$785 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_full_cr_0;
+ assign \$789 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_full_cr_cr0_0;
+ assign \$791 = \$787 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$789 ;
+ assign \$793 = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_full_cr_en_o;
+ assign \$795 = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_core_cr_rd : 8'h00;
+ assign \$797 = \fus_cu_rd__rel_o$40 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1];
+ assign \$799 = \$797 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_a_0;
+ assign \$801 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_a_cr0_0;
+ assign \$803 = \$799 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$801 ;
+ assign \$805 = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_a_en_o;
assign \$807 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1;
assign \$809 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$807 ;
- assign \$811 = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$809 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
- assign \$813 = \fus_cu_rd__rel_o$81 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2];
- assign \$815 = \$813 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_a_0;
- assign \$817 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_a_branch0_1;
- assign \$819 = \$815 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$817 ;
- assign \$821 = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_a_en_o;
+ assign \$811 = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$809 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$813 = \fus_cu_rd__rel_o$81 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[2];
+ assign \$815 = \$813 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_a_0;
+ assign \$817 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_a_branch0_1;
+ assign \$819 = \$815 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$817 ;
+ assign \$821 = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_a_en_o;
assign \$823 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1;
assign \$825 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$823 ;
- assign \$827 = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$825 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$827 = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$825 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
assign \$830 = addr_en_CR_cr_a_cr0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_CR_cr_a_branch0_1;
- assign \$832 = \fus_cu_rd__rel_o$40 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
- assign \$834 = \$832 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_b_0;
- assign \$836 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_b_cr0_0;
- assign \$838 = \$834 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$836 ;
- assign \$840 = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_b_en_o;
+ assign \$832 = \fus_cu_rd__rel_o$40 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1];
+ assign \$834 = \$832 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_b_0;
+ assign \$836 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_b_cr0_0;
+ assign \$838 = \$834 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$836 ;
+ assign \$840 = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_b_en_o;
assign \$842 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) core_cr_in2;
assign \$844 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) \$842 ;
- assign \$846 = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$844 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
- assign \$848 = \fus_cu_rd__rel_o$40 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
- assign \$850 = \$848 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_c_0;
- assign \$852 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_c_cr0_0;
- assign \$854 = \$850 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$852 ;
- assign \$856 = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_c_en_o;
+ assign \$846 = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$844 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$848 = \fus_cu_rd__rel_o$40 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[1];
+ assign \$850 = \$848 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_CR_cr_c_0;
+ assign \$852 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_CR_cr_c_cr0_0;
+ assign \$854 = \$850 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$852 ;
+ assign \$856 = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_CR_cr_c_en_o;
assign \$858 = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \core_cr_in2$1 ;
assign \$860 = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \$858 ;
- assign \$862 = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$860 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
- assign \$864 = \fus_cu_rd__rel_o$81 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2];
- assign \$866 = \$864 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0;
- assign \$868 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_branch0_0;
- assign \$870 = \$866 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$868 ;
- assign \$872 = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
- assign \$874 = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0;
- assign \$876 = \fus_cu_rd__rel_o$43 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3];
- assign \$878 = \$876 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0;
- assign \$880 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_trap0_1;
- assign \$882 = \$878 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$880 ;
- assign \$884 = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
- assign \$886 = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0;
- assign \$888 = \fus_cu_rd__rel_o$65 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
- assign \$890 = \$888 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0;
- assign \$892 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_spr0_2;
- assign \$894 = \$890 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$892 ;
- assign \$896 = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
- assign \$898 = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0;
- assign \$900 = \fus_cu_rd__rel_o$81 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2];
- assign \$902 = \$900 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_1;
- assign \$904 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_branch0_3;
- assign \$906 = \$902 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$904 ;
- assign \$908 = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
- assign \$910 = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast2 : 3'h0;
- assign \$912 = \fus_cu_rd__rel_o$43 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3];
- assign \$914 = \$912 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_1;
- assign \$916 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_trap0_4;
- assign \$918 = \$914 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$916 ;
- assign \$920 = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
- assign \$922 = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast2 : 3'h0;
+ assign \$862 = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) \$860 : 256'h0000000000000000000000000000000000000000000000000000000000000000;
+ assign \$864 = \fus_cu_rd__rel_o$81 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[2];
+ assign \$866 = \$864 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_0;
+ assign \$868 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_branch0_0;
+ assign \$870 = \$866 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$868 ;
+ assign \$872 = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o;
+ assign \$874 = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast1 : 3'h0;
+ assign \$876 = \fus_cu_rd__rel_o$43 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3];
+ assign \$878 = \$876 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_0;
+ assign \$880 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_trap0_1;
+ assign \$882 = \$878 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$880 ;
+ assign \$884 = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o;
+ assign \$886 = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast1 : 3'h0;
+ assign \$888 = \fus_cu_rd__rel_o$65 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5];
+ assign \$890 = \$888 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_0;
+ assign \$892 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_spr0_2;
+ assign \$894 = \$890 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$892 ;
+ assign \$896 = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o;
+ assign \$898 = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast1 : 3'h0;
+ assign \$900 = \fus_cu_rd__rel_o$81 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[2];
+ assign \$902 = \$900 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_1;
+ assign \$904 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_branch0_3;
+ assign \$906 = \$902 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$904 ;
+ assign \$908 = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o;
+ assign \$910 = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast2 : 3'h0;
+ assign \$912 = \fus_cu_rd__rel_o$43 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[3];
+ assign \$914 = \$912 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_FAST_fast1_1;
+ assign \$916 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_FAST_fast1_trap0_4;
+ assign \$918 = \$914 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$916 ;
+ assign \$920 = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_FAST_fast1_en_o;
+ assign \$922 = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_fast2 : 3'h0;
assign \$924 = addr_en_FAST_fast1_branch0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_1;
assign \$926 = addr_en_FAST_fast1_branch0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_4;
assign \$928 = addr_en_FAST_fast1_spr0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$926 ;
assign \$930 = \$924 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$928 ;
- assign \$932 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) { rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 };
- assign \$934 = \fus_cu_rd__rel_o$65 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
- assign \$936 = \$934 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_SPR_spr1_0;
- assign \$938 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_SPR_spr1_spr0_0;
- assign \$940 = \$936 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$938 ;
- assign \$942 = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_SPR_spr1_en_o;
- assign \$944 = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_spr1 : 10'h000;
- assign \$946 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) rp_SPR_spr1_spr0_0;
- assign \$948 = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
- assign \$950 = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
- assign \$952 = \fus_cu_wr__rel_o$93 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1];
- assign \$954 = \fus_cu_wr__rel_o$96 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
- assign \$956 = \fus_cu_wr__rel_o$99 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[4];
- assign \$958 = \fus_cu_wr__rel_o$102 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
- assign \$960 = \fus_cu_wr__rel_o$105 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6];
- assign \$962 = \fus_cu_wr__rel_o$108 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7];
- assign \$964 = \fus_cu_wr__rel_o$111 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8];
- assign \$966 = \fus_cu_wr__rel_o$113 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[9];
- assign \$968 = \fus_cu_wr__rel_o$113 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[9];
- assign \$970 = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$932 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) { rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 };
+ assign \$934 = \fus_cu_rd__rel_o$65 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) fu_enable[5];
+ assign \$936 = \$934 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:290" *) rdflag_SPR_spr1_0;
+ assign \$938 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) dp_SPR_spr1_spr0_0;
+ assign \$940 = \$936 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) \$938 ;
+ assign \$942 = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296" *) rdpick_SPR_spr1_en_o;
+ assign \$944 = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:298" *) core_spr1 : 10'h000;
+ assign \$946 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:325" *) rp_SPR_spr1_spr0_0;
+ assign \$948 = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) fus_cu_busy_o;
+ assign \$950 = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[0];
+ assign \$952 = \fus_cu_wr__rel_o$93 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[1];
+ assign \$954 = \fus_cu_wr__rel_o$96 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[3];
+ assign \$956 = \fus_cu_wr__rel_o$99 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[4];
+ assign \$958 = \fus_cu_wr__rel_o$102 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[5];
+ assign \$960 = \fus_cu_wr__rel_o$105 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[6];
+ assign \$962 = \fus_cu_wr__rel_o$108 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[7];
+ assign \$964 = \fus_cu_wr__rel_o$111 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[8];
+ assign \$966 = \fus_cu_wr__rel_o$113 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[9];
+ assign \$968 = \fus_cu_wr__rel_o$113 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" *) fu_enable[9];
+ assign \$970 = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$972 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wr_pick_dly;
assign \$974 = wr_pick & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$972 ;
- assign \$980 = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
- assign \$982 = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
- assign \$984 = \fus_o_ok$92 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ;
- assign \$987 = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
+ assign \$980 = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
+ assign \$982 = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) core_rego : 7'h00;
+ assign \$984 = \fus_o_ok$92 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *) \fus_cu_busy_o$14 ;
+ assign \$987 = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *) wrpick_INT_o_en_o;
assign \$991 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$989 ;
assign \$993 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$991 ;
- assign \$998 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
+ assign \$998 = \wr_pick$986 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *) wrpick_INT_o_en_o;
always @(posedge coresync_clk)
\wr_pick_dly$1806 <= \wr_pick_dly$1806$next ;
always @(posedge coresync_clk)
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__output_carry = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__output_carry = dec_LOGICAL_LOGICAL__output_carry;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__is_32bit = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__is_32bit = dec_LOGICAL_LOGICAL__is_32bit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__is_signed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__is_signed = dec_LOGICAL_LOGICAL__is_signed;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__data_len = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__data_len = dec_LOGICAL_LOGICAL__data_len;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__insn = dec_LOGICAL_LOGICAL__insn;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_issue_i$22 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_issue_i$22 = issue_i;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_rdmaskn_i$24 = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_rdmaskn_i$24 = \$256 ;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_spr0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[5])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_spr0__insn_type = dec_SPR_SPR__insn_type;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_spr0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[5])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_spr0__fn_unit = dec_SPR_SPR__fn_unit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_spr0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[5])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_spr0__insn = dec_SPR_SPR__insn;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_spr0__is_32bit = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[5])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_spr0__is_32bit = dec_SPR_SPR__is_32bit;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_issue_i$25 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[5])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_issue_i$25 = issue_i;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_rdmaskn_i$27 = 6'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[5])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_rdmaskn_i$27 = \$270 ;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__insn_type = dec_DIV_DIV__insn_type;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__fn_unit = dec_DIV_DIV__fn_unit;
endcase
if (\initial ) begin end
fus_oper_i_alu_div0__imm_data__data = 64'h0000000000000000;
fus_oper_i_alu_div0__imm_data__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_div0__imm_data__ok, fus_oper_i_alu_div0__imm_data__data } = { dec_DIV_DIV__imm_data__ok, dec_DIV_DIV__imm_data__data };
endcase
if (\initial ) begin end
fus_oper_i_alu_div0__rc__rc = 1'h0;
fus_oper_i_alu_div0__rc__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_div0__rc__ok, fus_oper_i_alu_div0__rc__rc } = { dec_DIV_DIV__rc__ok, dec_DIV_DIV__rc__rc };
endcase
if (\initial ) begin end
fus_oper_i_alu_div0__oe__oe = 1'h0;
fus_oper_i_alu_div0__oe__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_div0__oe__ok, fus_oper_i_alu_div0__oe__oe } = { dec_DIV_DIV__oe__ok, dec_DIV_DIV__oe__oe };
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__invert_in = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__invert_in = dec_DIV_DIV__invert_in;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__zero_a = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__zero_a = dec_DIV_DIV__zero_a;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__input_carry = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__input_carry = dec_DIV_DIV__input_carry;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__invert_out = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__invert_out = dec_DIV_DIV__invert_out;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__write_cr0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__write_cr0 = dec_DIV_DIV__write_cr0;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__output_carry = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__output_carry = dec_DIV_DIV__output_carry;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__is_32bit = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__is_32bit = dec_DIV_DIV__is_32bit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__is_signed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__is_signed = dec_DIV_DIV__is_signed;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__data_len = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__data_len = dec_DIV_DIV__data_len;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_div0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_div0__insn = dec_DIV_DIV__insn;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_issue_i$28 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_issue_i$28 = issue_i;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_rdmaskn_i$30 = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_rdmaskn_i$30 = \$300 ;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_mul0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_mul0__insn_type = dec_MUL_MUL__insn_type;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_mul0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_mul0__fn_unit = dec_MUL_MUL__fn_unit;
endcase
if (\initial ) begin end
fus_oper_i_alu_mul0__imm_data__data = 64'h0000000000000000;
fus_oper_i_alu_mul0__imm_data__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_mul0__imm_data__ok, fus_oper_i_alu_mul0__imm_data__data } = { dec_MUL_MUL__imm_data__ok, dec_MUL_MUL__imm_data__data };
endcase
if (\initial ) begin end
fus_oper_i_alu_mul0__rc__rc = 1'h0;
fus_oper_i_alu_mul0__rc__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_mul0__rc__ok, fus_oper_i_alu_mul0__rc__rc } = { dec_MUL_MUL__rc__ok, dec_MUL_MUL__rc__rc };
endcase
if (\initial ) begin end
fus_oper_i_alu_mul0__oe__oe = 1'h0;
fus_oper_i_alu_mul0__oe__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_mul0__oe__ok, fus_oper_i_alu_mul0__oe__oe } = { dec_MUL_MUL__oe__ok, dec_MUL_MUL__oe__oe };
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_mul0__write_cr0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_mul0__write_cr0 = dec_MUL_MUL__write_cr0;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_mul0__is_32bit = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_mul0__is_32bit = dec_MUL_MUL__is_32bit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_mul0__is_signed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_mul0__is_signed = dec_MUL_MUL__is_signed;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_mul0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_mul0__insn = dec_MUL_MUL__insn;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_issue_i$31 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_issue_i$31 = issue_i;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_rdmaskn_i$33 = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_rdmaskn_i$33 = \$314 ;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__insn_type = dec_SHIFT_ROT_SHIFT_ROT__insn_type;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__fn_unit = dec_SHIFT_ROT_SHIFT_ROT__fn_unit;
endcase
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__imm_data__data = 64'h0000000000000000;
fus_oper_i_alu_shift_rot0__imm_data__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_shift_rot0__imm_data__ok, fus_oper_i_alu_shift_rot0__imm_data__data } = { dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok, dec_SHIFT_ROT_SHIFT_ROT__imm_data__data };
endcase
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__rc__rc = 1'h0;
fus_oper_i_alu_shift_rot0__rc__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_shift_rot0__rc__ok, fus_oper_i_alu_shift_rot0__rc__rc } = { dec_SHIFT_ROT_SHIFT_ROT__rc__ok, dec_SHIFT_ROT_SHIFT_ROT__rc__rc };
endcase
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__oe__oe = 1'h0;
fus_oper_i_alu_shift_rot0__oe__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_shift_rot0__oe__ok, fus_oper_i_alu_shift_rot0__oe__oe } = { dec_SHIFT_ROT_SHIFT_ROT__oe__ok, dec_SHIFT_ROT_SHIFT_ROT__oe__oe };
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__write_cr0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__write_cr0 = dec_SHIFT_ROT_SHIFT_ROT__write_cr0;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__invert_in = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__invert_in = dec_SHIFT_ROT_SHIFT_ROT__invert_in;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__input_carry = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__input_carry = dec_SHIFT_ROT_SHIFT_ROT__input_carry;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__output_carry = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__output_carry = dec_SHIFT_ROT_SHIFT_ROT__output_carry;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__input_cr = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__input_cr = dec_SHIFT_ROT_SHIFT_ROT__input_cr;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__output_cr = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__output_cr = dec_SHIFT_ROT_SHIFT_ROT__output_cr;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__is_32bit = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__is_32bit = dec_SHIFT_ROT_SHIFT_ROT__is_32bit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__is_signed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__is_signed = dec_SHIFT_ROT_SHIFT_ROT__is_signed;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_shift_rot0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_shift_rot0__insn = dec_SHIFT_ROT_SHIFT_ROT__insn;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_issue_i$34 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_issue_i$34 = issue_i;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_rdmaskn_i$36 = 5'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_rdmaskn_i$36 = \$328 ;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__insn_type = dec_LDST_LDST__insn_type;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__fn_unit = dec_LDST_LDST__fn_unit;
endcase
if (\initial ) begin end
fus_oper_i_ldst_ldst0__imm_data__data = 64'h0000000000000000;
fus_oper_i_ldst_ldst0__imm_data__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_ldst_ldst0__imm_data__ok, fus_oper_i_ldst_ldst0__imm_data__data } = { dec_LDST_LDST__imm_data__ok, dec_LDST_LDST__imm_data__data };
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__zero_a = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__zero_a = dec_LDST_LDST__zero_a;
endcase
if (\initial ) begin end
fus_oper_i_ldst_ldst0__rc__rc = 1'h0;
fus_oper_i_ldst_ldst0__rc__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_ldst_ldst0__rc__ok, fus_oper_i_ldst_ldst0__rc__rc } = { dec_LDST_LDST__rc__ok, dec_LDST_LDST__rc__rc };
endcase
if (\initial ) begin end
fus_oper_i_ldst_ldst0__oe__oe = 1'h0;
fus_oper_i_ldst_ldst0__oe__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_ldst_ldst0__oe__ok, fus_oper_i_ldst_ldst0__oe__oe } = { dec_LDST_LDST__oe__ok, dec_LDST_LDST__oe__oe };
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__is_32bit = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__is_32bit = dec_LDST_LDST__is_32bit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__is_signed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__is_signed = dec_LDST_LDST__is_signed;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__data_len = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__data_len = dec_LDST_LDST__data_len;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__byte_reverse = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__byte_reverse = dec_LDST_LDST__byte_reverse;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__sign_extend = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__sign_extend = dec_LDST_LDST__sign_extend;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__ldst_mode = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__ldst_mode = dec_LDST_LDST__ldst_mode;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_ldst_ldst0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_ldst_ldst0__insn = dec_LDST_LDST__insn;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_issue_i$37 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_issue_i$37 = issue_i;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_rdmaskn_i$39 = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_rdmaskn_i$39 = \$350 ;
endcase
always @* begin
if (\initial ) begin end
fus_src2_i = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_alu0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
fus_src2_i = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src2_i$42 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_cr0_1)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src2_i$42 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src2_i$45 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_trap0_2)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src2_i$45 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src2_i$48 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_logical0_3)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src2_i$48 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src2_i$51 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_div0_4)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src2_i$51 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src2_i$54 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_mul0_5)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src2_i$54 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src2_i$57 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_shiftrot0_6)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src2_i$57 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src2_i$60 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_ldst0_7)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src2_i$60 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
fus_src3_i = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_shiftrot0_8)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
fus_src3_i = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src3_i$61 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_ldst0_9)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src3_i$61 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
fus_src1_i = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_alu0_10)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
fus_src1_i = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src1_i$62 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_cr0_11)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src1_i$62 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src1_i$63 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_trap0_12)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src1_i$63 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src1_i$64 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_logical0_13)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src1_i$64 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src1_i$67 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_spr0_14)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src1_i$67 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src1_i$68 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_div0_15)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src1_i$68 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src1_i$69 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_mul0_16)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src1_i$69 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src1_i$70 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_shiftrot0_17)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src1_i$70 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src1_i$71 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_INT_rabc_ldst0_18)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src1_i$71 = int_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src3_i$72 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_so_alu0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src3_i$72 = xer_src1__data_o[0];
endcase
always @* begin
if (\initial ) begin end
\fus_src3_i$73 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_so_logical0_1)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src3_i$73 = xer_src1__data_o[0];
endcase
always @* begin
if (\initial ) begin end
fus_src4_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_so_spr0_2)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
fus_src4_i = xer_src1__data_o[0];
endcase
always @* begin
if (\initial ) begin end
\fus_src3_i$74 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_so_div0_3)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src3_i$74 = xer_src1__data_o[0];
endcase
always @* begin
if (\initial ) begin end
\fus_src3_i$75 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_so_mul0_4)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src3_i$75 = xer_src1__data_o[0];
endcase
always @* begin
if (\initial ) begin end
\fus_src4_i$76 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_so_shiftrot0_5)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src4_i$76 = xer_src1__data_o[0];
endcase
always @* begin
if (\initial ) begin end
\fus_src4_i$77 = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_ca_alu0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src4_i$77 = xer_src2__data_o;
endcase
always @* begin
if (\initial ) begin end
fus_src6_i = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_ca_spr0_1)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
fus_src6_i = xer_src2__data_o;
endcase
always @* begin
if (\initial ) begin end
fus_src5_i = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_ca_shiftrot0_2)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
fus_src5_i = xer_src2__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src5_i$78 = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_XER_xer_ov_spr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src5_i$78 = xer_src3__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src3_i$79 = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_CR_full_cr_cr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src3_i$79 = cr_full_rd__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src4_i$80 = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_CR_cr_a_cr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src4_i$80 = cr_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src3_i$83 = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_CR_cr_a_branch0_1)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src3_i$83 = cr_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\counter$next = counter;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *)
casez (\$221 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" */
1'h1:
\counter$next = \$223 [1:0];
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
\counter$next = 2'h2;
endcase
always @* begin
if (\initial ) begin end
\fus_src5_i$84 = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_CR_cr_b_cr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src5_i$84 = cr_src2__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src6_i$85 = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_CR_cr_c_cr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src6_i$85 = cr_src3__data_o;
endcase
always @* begin
if (\initial ) begin end
corebusy_o = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *)
casez (\$226 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" */
1'h1:
corebusy_o = 1'h1;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
corebusy_o = 1'h1;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
begin
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = fus_cu_busy_o;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[1])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = \fus_cu_busy_o$14 ;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = \fus_cu_busy_o$17 ;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = \fus_cu_busy_o$20 ;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = \fus_cu_busy_o$23 ;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[5])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = \fus_cu_busy_o$26 ;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[6])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = \fus_cu_busy_o$29 ;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[7])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = \fus_cu_busy_o$32 ;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[8])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = \fus_cu_busy_o$35 ;
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[9])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
corebusy_o = \fus_cu_busy_o$38 ;
endcase
always @* begin
if (\initial ) begin end
\fus_src1_i$86 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_FAST_fast1_branch0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src1_i$86 = fast_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\core_terminate_o$next = core_terminate_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
\core_terminate_o$next = 1'h1;
endcase
always @* begin
if (\initial ) begin end
\fus_src3_i$87 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_FAST_fast1_trap0_1)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src3_i$87 = fast_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src3_i$88 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_FAST_fast1_spr0_2)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src3_i$88 = fast_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__insn_type = dec_ALU_ALU__insn_type;
endcase
always @* begin
if (\initial ) begin end
\fus_src2_i$89 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_FAST_fast1_branch0_3)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src2_i$89 = fast_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
\fus_src4_i$90 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_FAST_fast1_trap0_4)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src4_i$90 = fast_src1__data_o;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__fn_unit = dec_ALU_ALU__fn_unit;
endcase
always @* begin
if (\initial ) begin end
\fus_src2_i$91 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" *)
casez (dp_SPR_spr1_spr0_0)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309" */
1'h1:
\fus_src2_i$91 = spr_spr1__data_o;
endcase
if (\initial ) begin end
fus_oper_i_alu_alu0__imm_data__data = 64'h0000000000000000;
fus_oper_i_alu_alu0__imm_data__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_alu0__imm_data__ok, fus_oper_i_alu_alu0__imm_data__data } = { dec_ALU_ALU__imm_data__ok, dec_ALU_ALU__imm_data__data };
endcase
if (\initial ) begin end
fus_oper_i_alu_alu0__rc__rc = 1'h0;
fus_oper_i_alu_alu0__rc__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_alu0__rc__ok, fus_oper_i_alu_alu0__rc__rc } = { dec_ALU_ALU__rc__ok, dec_ALU_ALU__rc__rc };
endcase
if (\initial ) begin end
fus_oper_i_alu_alu0__oe__oe = 1'h0;
fus_oper_i_alu_alu0__oe__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_alu0__oe__ok, fus_oper_i_alu_alu0__oe__oe } = { dec_ALU_ALU__oe__ok, dec_ALU_ALU__oe__oe };
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__invert_in = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__invert_in = dec_ALU_ALU__invert_in;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__zero_a = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__zero_a = dec_ALU_ALU__zero_a;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__invert_out = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__invert_out = dec_ALU_ALU__invert_out;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__write_cr0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__write_cr0 = dec_ALU_ALU__write_cr0;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__input_carry = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__input_carry = dec_ALU_ALU__input_carry;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__output_carry = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__output_carry = dec_ALU_ALU__output_carry;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__is_32bit = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__is_32bit = dec_ALU_ALU__is_32bit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__is_signed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__is_signed = dec_ALU_ALU__is_signed;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__data_len = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__data_len = dec_ALU_ALU__data_len;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_alu0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_alu0__insn = dec_ALU_ALU__insn;
endcase
always @* begin
if (\initial ) begin end
fus_cu_issue_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_cu_issue_i = issue_i;
endcase
always @* begin
if (\initial ) begin end
fus_cu_rdmaskn_i = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[0])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_cu_rdmaskn_i = \$228 ;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_cr0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[1])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_cr0__insn_type = dec_CR_CR__insn_type;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_cr0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[1])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_cr0__fn_unit = dec_CR_CR__fn_unit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_cr0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[1])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_cr0__insn = dec_CR_CR__insn;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_issue_i$13 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[1])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_issue_i$13 = issue_i;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_rdmaskn_i$15 = 6'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[1])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_rdmaskn_i$15 = \$250 ;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_branch0__cia = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_branch0__cia = dec_BRANCH_BRANCH__cia;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_branch0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_branch0__insn_type = dec_BRANCH_BRANCH__insn_type;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_branch0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_branch0__fn_unit = dec_BRANCH_BRANCH__fn_unit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_branch0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_branch0__insn = dec_BRANCH_BRANCH__insn;
endcase
if (\initial ) begin end
fus_oper_i_alu_branch0__imm_data__data = 64'h0000000000000000;
fus_oper_i_alu_branch0__imm_data__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_branch0__imm_data__ok, fus_oper_i_alu_branch0__imm_data__data } = { dec_BRANCH_BRANCH__imm_data__ok, dec_BRANCH_BRANCH__imm_data__data };
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_branch0__lk = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_branch0__lk = dec_BRANCH_BRANCH__lk;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_branch0__is_32bit = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_branch0__is_32bit = dec_BRANCH_BRANCH__is_32bit;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_issue_i$16 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_issue_i$16 = issue_i;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_rdmaskn_i$18 = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[2])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_rdmaskn_i$18 = \$252 ;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_trap0__insn_type = core_core_insn_type;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_trap0__fn_unit = core_core_fn_unit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__insn = 32'd0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_trap0__insn = core_core_insn;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__msr = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_trap0__msr = core_core_msr;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__cia = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_trap0__cia = core_core_cia;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__is_32bit = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_trap0__is_32bit = core_core_is_32bit;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__traptype = 8'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_trap0__traptype = core_core_traptype;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__trapaddr = 13'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_trap0__trapaddr = core_core_trapaddr;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_trap0__ldst_exc = 8'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_trap0__ldst_exc = { \core_core_exc_$signal$9 , \core_core_exc_$signal$8 , \core_core_exc_$signal$7 , \core_core_exc_$signal$6 , \core_core_exc_$signal$5 , \core_core_exc_$signal$4 , \core_core_exc_$signal$3 , \core_core_exc_$signal };
endcase
always @* begin
if (\initial ) begin end
\fus_cu_issue_i$19 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_issue_i$19 = issue_i;
endcase
always @* begin
if (\initial ) begin end
\fus_cu_rdmaskn_i$21 = 4'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[3])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
\fus_cu_rdmaskn_i$21 = \$254 ;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__insn_type = 7'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__insn_type = dec_LOGICAL_LOGICAL__insn_type;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__fn_unit = 14'h0000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__fn_unit = dec_LOGICAL_LOGICAL__fn_unit;
endcase
if (\initial ) begin end
fus_oper_i_alu_logical0__imm_data__data = 64'h0000000000000000;
fus_oper_i_alu_logical0__imm_data__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_logical0__imm_data__ok, fus_oper_i_alu_logical0__imm_data__data } = { dec_LOGICAL_LOGICAL__imm_data__ok, dec_LOGICAL_LOGICAL__imm_data__data };
endcase
if (\initial ) begin end
fus_oper_i_alu_logical0__rc__rc = 1'h0;
fus_oper_i_alu_logical0__rc__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_logical0__rc__ok, fus_oper_i_alu_logical0__rc__rc } = { dec_LOGICAL_LOGICAL__rc__ok, dec_LOGICAL_LOGICAL__rc__rc };
endcase
if (\initial ) begin end
fus_oper_i_alu_logical0__oe__oe = 1'h0;
fus_oper_i_alu_logical0__oe__ok = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
{ fus_oper_i_alu_logical0__oe__ok, fus_oper_i_alu_logical0__oe__oe } = { dec_LOGICAL_LOGICAL__oe__ok, dec_LOGICAL_LOGICAL__oe__oe };
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__invert_in = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__invert_in = dec_LOGICAL_LOGICAL__invert_in;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__zero_a = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__zero_a = dec_LOGICAL_LOGICAL__zero_a;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__input_carry = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__input_carry = dec_LOGICAL_LOGICAL__input_carry;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__invert_out = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__invert_out = dec_LOGICAL_LOGICAL__invert_out;
endcase
always @* begin
if (\initial ) begin end
fus_oper_i_alu_logical0__write_cr0 = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" *)
casez (ivalid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
casez (core_core_insn_type)
/* \nmigen.decoding = "OP_ATTN/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:206" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" */
7'h05:
/* empty */;
/* \nmigen.decoding = "OP_NOP/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:209" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" */
7'h01:
/* empty */;
/* \nmigen.decoding = {0{1'b0}} */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:213" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" *)
casez (fu_enable[4])
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:220" */
1'h1:
fus_oper_i_alu_logical0__write_cr0 = dec_LOGICAL_LOGICAL__write_cr0;
endcase
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] data_i;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output cr_a_ok;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_cyc;
wire \$97 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
wire \$99 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
input [6:0] core_dbg_core_dbg_dststep;
wire [63:0] log_dmi_data;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" *)
wire [31:0] log_write_addr_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" *)
wire [63:0] stat_reg;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output cr_a_ok;
(* generator = "nMigen" *)
module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 , issue__wen, issue__data_i, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [2:0] dest1__addr;
(* \nmigen.hierarchy = "test_issuer.ti.core.fus" *)
(* generator = "nMigen" *)
module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src2_i$79 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$80 , \cu_wr__rel_o$81 , \cu_wr__go_i$82 , \o_ok$83 , \cu_wr__rel_o$84 , \cu_wr__go_i$85 , \o_ok$86 , \cu_wr__rel_o$87 , \cu_wr__go_i$88 , \o_ok$89 , \cu_wr__rel_o$90 , \cu_wr__go_i$91 , \o_ok$92 , \cu_wr__rel_o$93 , \cu_wr__go_i$94 , \o_ok$95 , \cu_wr__rel_o$96 , \cu_wr__go_i$97 , \o_ok$98 , \cu_wr__rel_o$99 , \cu_wr__go_i$100 , \cu_wr__rel_o$101 , \cu_wr__go_i$102 , dest1_o, \dest1_o$103 , \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$110 , \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \dest2_o$115 , dest3_o, \dest2_o$116 , \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , xer_ca_ok, \xer_ca_ok$120 , \xer_ca_ok$121 , \dest3_o$122 , dest6_o, \dest3_o$123 , xer_ov_ok, \xer_ov_ok$124 , \xer_ov_ok$125 , \xer_ov_ok$126 , dest4_o, dest5_o, \dest3_o$127 , \dest3_o$128 , xer_so_ok, \xer_so_ok$129 , \xer_so_ok$130 , \xer_so_ok$131 , \dest5_o$132 , \dest4_o$133 , \dest4_o$134 , \dest4_o$135 , fast1_ok, \cu_wr__rel_o$136 , \cu_wr__go_i$137 , \fast1_ok$138 , \fast1_ok$139 , fast2_ok, \fast2_ok$140 , \dest1_o$141 , \dest2_o$142 , \dest3_o$143 , \dest2_o$144 , \dest3_o$145 , nia_ok, \nia_ok$146 , \dest3_o$147 , \dest4_o$148 , msr_ok, \dest5_o$149 , spr1_ok, \dest2_o$150 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$151 , \ldst_port0_exc_$signal$152 , \ldst_port0_exc_$signal$153 , \ldst_port0_exc_$signal$154 , \ldst_port0_exc_$signal$155 , \ldst_port0_exc_$signal$156 , \ldst_port0_exc_$signal$157 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output cr_a_ok;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
output q_idx_l;
wire a_stall_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *)
input a_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *)
reg [44:0] f_badaddr_o = 45'h000000000000;
reg [63:0] ibus_rdata = 64'h0000000000000000;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *)
reg [63:0] \ibus_rdata$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
input wb_icache_en;
(* generator = "nMigen" *)
module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [4:0] dest1__addr;
input TAP_bus__tms;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:420" *)
reg TAP_tdo;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
input dmi0__ack_o;
wire posjtag_clk;
(* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *)
wire posjtag_rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input sdr_a_0__core__o;
(* \nmigen.hierarchy = "test_issuer.ti.core.l0" *)
(* generator = "nMigen" *)
module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
input dbus__ack;
wire [95:0] \$31 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" *)
wire [95:0] \$32 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
reg \idx_l$23 = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \alu_ok$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" *)
wire alu_valid;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
input cu_ad__go_i;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output cr_a_ok;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$64 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$49 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
input [3:0] cr_a;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$93 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *)
wire \$95 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
input dbus__ack;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output cr_a_ok;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$50 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* enum_base_type = "Function" *)
(* enum_value_00000000000000 = "NONE" *)
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$34 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* enum_base_type = "Function" *)
(* enum_value_00000000000000 = "NONE" *)
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$56 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
reg busy_l_r_busy;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
reg busy_l_s_busy;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
wire cyc_l_q_cyc;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$14 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
input [3:0] cr_a;
reg \br_op__lk$8 = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
reg \br_op__lk$8$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
input [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$22 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
input [63:0] fast1;
wire \alu_op__zero_a$79 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
reg \alu_op__zero_a$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$65 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$30 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
wire [63:0] dummy_fast1;
reg \alu_op__zero_a$11$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
wire \alu_op__zero_a$72 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
input [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$51 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
input [3:0] cr_a;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$26 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
input [63:0] fast1;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$74 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output [3:0] cr_a;
wire \$63 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *)
wire \$66 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
input div_by_zero;
reg \initial = 0;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
wire \$66 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
output div_by_zero;
(* \nmigen.hierarchy = "test_issuer.pll" *)
(* generator = "nMigen" *)
-module pll(clk_24_i, pll_18_o, clk_sel_i, pll_lck_o, clk_pll_o);
+module pll(\ref , div_out_test, vco_test_ana, clk_sel_i, out);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
wire \$1 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+ wire \$11 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:23" *)
+ wire \$13 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
wire \$3 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
wire \$5 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *)
- input clk_24_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *)
- output clk_pll_o;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+ wire \$7 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+ wire \$9 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *)
- input [1:0] clk_sel_i;
+ wire a0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *)
+ wire a1;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *)
- output pll_18_o;
- reg pll_18_o;
+ output [1:0] clk_sel_i;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *)
+ output div_out_test;
+ reg div_out_test;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *)
- output pll_lck_o;
- reg pll_lck_o;
- assign \$1 = clk_sel_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *) 2'h0;
- assign \$3 = clk_sel_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *) 2'h0;
- assign \$5 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) clk_24_i;
- always @* begin
- if (\initial ) begin end
- pll_lck_o = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *)
- casez (\$1 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" */
+ output out;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *)
+ input \ref ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *)
+ output vco_test_ana;
+ reg vco_test_ana;
+ assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) a1;
+ assign \$11 = \$7 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) \$9 ;
+ assign \$13 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:23" *) \ref ;
+ assign \$1 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) a0;
+ assign \$3 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) a1;
+ assign \$5 = \$1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) \$3 ;
+ assign \$7 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *) a0;
+ always @* begin
+ if (\initial ) begin end
+ vco_test_ana = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+ casez (\$5 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" */
1'h1:
- pll_lck_o = clk_24_i;
+ vco_test_ana = \ref ;
endcase
end
always @* begin
if (\initial ) begin end
- pll_18_o = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" *)
- casez (\$3 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" */
+ div_out_test = 1'h0;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" *)
+ casez (\$11 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" */
1'h1:
- pll_18_o = \$5 ;
+ div_out_test = \$13 ;
endcase
end
- assign clk_pll_o = clk_24_i;
+ assign a0 = 1'h0;
+ assign a1 = 1'h0;
+ assign clk_sel_i = 2'h0;
+ assign out = \ref ;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" *)
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest10__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] dest10__data_i;
reg [63:0] \cia0__data_o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input cia0__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] d_wr10__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest11__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] dest11__data_i;
reg [63:0] \cia1__data_o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input cia1__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] d_wr11__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest12__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] dest12__data_i;
reg [63:0] \cia2__data_o$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input cia2__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] d_wr12__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest13__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest14__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest15__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest16__data_i;
wire \$6 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [3:0] dest17__data_i;
wire [4:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [4:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [4:0] q_int = 5'h00;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [4:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [4:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [4:0] q_int = 5'h00;
wire [1:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [1:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [1:0] q_int = 2'h0;
wire [5:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [5:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [5:0] q_int = 6'h00;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
output cr_a_ok;
(* generator = "nMigen" *)
module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
wire [3:0] memory_r_addr;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
output cu_busy_o;
wire \$1 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *)
reg [63:0] d;
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *)
output sram4k_0_wb__ack;
wire \$1 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *)
reg [63:0] d;
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *)
output sram4k_1_wb__ack;
wire \$1 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *)
reg [63:0] d;
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *)
output sram4k_2_wb__ack;
wire \$1 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" *)
reg [8:0] a;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:43" *)
reg [63:0] d;
input enable;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" *)
wire [63:0] q;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *)
output sram4k_3_wb__ack;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire [5:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [5:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [5:0] q_int = 6'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [4:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [4:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [4:0] q_int = 5'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [3:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [3:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [3:0] q_int = 4'h0;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire [5:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [5:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [5:0] q_int = 6'h00;
wire [2:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire [2:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg [2:0] q_int = 3'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
reg [63:0] cia__data_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [2:0] cia__ren;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [63:0] data_i;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
(* \nmigen.hierarchy = "test_issuer" *)
(* top = 1 *)
(* generator = "nMigen" *)
-module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_18_o, pll_lck_o, pc_i);
+module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_18_o, vco_test_ana, pc_i);
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
input TAP_bus__tck;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
input TAP_bus__tms;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *)
output busy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *)
- input [1:0] clk_sel_i;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *)
+ output [1:0] clk_sel_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *)
input core_bigendian_i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
input pc_i_ok;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *)
output [63:0] pc_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1159" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *)
output pll_18_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *)
- wire pll_clk_24_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" *)
- wire pll_clk_pll_o;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:14" *)
+ wire pll_div_out_test;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" *)
- output pll_lck_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" *)
- wire pll_pll_18_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *)
+ wire pll_out;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" *)
+ wire pll_ref;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" *)
wire pllclk_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" *)
wire pllclk_rst;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input sdr_a_0__core__o;
input sram4k_3_wb__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *)
input sram4k_3_wb__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
wire ti_coresync_clk;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *)
+ output vco_test_ana;
pll pll (
- .clk_24_i(pll_clk_24_i),
- .clk_pll_o(pll_clk_pll_o),
.clk_sel_i(clk_sel_i),
- .pll_18_o(pll_pll_18_o),
- .pll_lck_o(pll_lck_o)
+ .div_out_test(pll_div_out_test),
+ .out(pll_out),
+ .\ref (pll_ref),
+ .vco_test_ana(vco_test_ana)
);
ti ti (
.TAP_bus__tck(TAP_bus__tck),
.sram4k_3_wb__stb(sram4k_3_wb__stb),
.sram4k_3_wb__we(sram4k_3_wb__we)
);
- assign ti_coresync_clk = pll_clk_pll_o;
+ assign ti_coresync_clk = pll_out;
assign pllclk_rst = rst;
- assign pll_18_o = pll_pll_18_o;
- assign pll_clk_24_i = clk;
- assign pllclk_clk = pll_clk_pll_o;
+ assign pll_18_o = pll_div_out_test;
+ assign pll_ref = clk;
+ assign pllclk_clk = pll_out;
endmodule
(* \nmigen.hierarchy = "test_issuer.ti" *)
(* generator = "nMigen" *)
module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__we, jtag_wb__cyc, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ack, sram4k_0_wb__adr, sram4k_0_wb__dat_r, sram4k_0_wb__dat_w, sram4k_0_wb__we, sram4k_0_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_r, sram4k_1_wb__dat_w, sram4k_1_wb__we, sram4k_1_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_r, sram4k_2_wb__dat_w, sram4k_2_wb__we, sram4k_2_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_r, sram4k_3_wb__dat_w, sram4k_3_wb__we, sram4k_3_wb__sel, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk);
reg \initial = 0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$100 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *)
wire \$102 ;
wire \$120 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$122 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$124 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$126 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$128 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
wire \$130 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$132 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$134 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *)
wire [7:0] \$136 ;
wire \$150 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$152 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
wire \$154 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
wire \$156 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" *)
wire \$158 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$160 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$162 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$164 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
wire \$166 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$168 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$170 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$172 ;
wire \$174 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$176 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$178 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$180 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$182 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$184 ;
wire \$186 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$188 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$190 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$192 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$194 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
wire \$196 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
- wire \$198 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *)
+ wire [2:0] \$197 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$200 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$202 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$204 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$206 ;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$208 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *)
- wire [2:0] \$209 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
+ wire \$210 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
wire \$212 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$214 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$216 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$218 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$220 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$222 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$224 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$226 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$228 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *)
wire \$23 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
wire \$230 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
- wire \$232 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" *)
+ wire [2:0] \$231 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
wire \$234 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
wire \$236 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *)
wire \$238 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$240 ;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$242 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *)
- wire [2:0] \$243 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
+ wire \$244 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$246 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$248 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
wire \$25 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$250 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
wire \$252 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
- wire \$254 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *)
+ wire [63:0] \$254 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" *)
wire \$256 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *)
wire \$258 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *)
wire \$260 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
- wire \$262 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700" *)
- wire \$264 ;
- (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *)
- wire [63:0] \$266 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *)
- wire \$268 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *)
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
+ wire [63:0] \$262 ;
+ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
+ wire [63:0] \$264 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *)
+ wire [64:0] \$266 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *)
+ wire [64:0] \$267 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *)
+ wire [64:0] \$269 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
wire [2:0] \$27 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *)
- wire \$270 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *)
- wire \$272 ;
- (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
- wire [63:0] \$274 ;
- (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
- wire [63:0] \$276 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *)
- wire [64:0] \$278 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *)
- wire [64:0] \$279 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *)
+ wire [64:0] \$270 ;
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
wire [2:0] \$28 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *)
- wire [64:0] \$281 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *)
- wire [64:0] \$282 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *)
wire \$30 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *)
wire \$32 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *)
wire \$34 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
wire \$36 ;
wire \$60 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$62 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
wire \$64 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
wire \$66 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$68 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$70 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$72 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
wire \$74 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$76 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$78 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$80 ;
wire \$82 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
wire \$84 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
wire \$86 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
wire \$88 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$90 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$92 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
wire \$94 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
wire \$96 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *)
wire \$98 ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
input TAP_bus__tck;
input TAP_bus__tms;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *)
output busy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *)
reg [7:0] core_asmcode = 8'h00;
reg [1:0] core_core_svstep = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *)
reg [1:0] \core_core_svstep$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *)
wire core_core_terminate_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
reg [6:0] core_core_vl = 7'h00;
reg [2:0] \core_core_xer_in$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *)
wire core_corebusy_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
wire core_coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
reg core_cr_out_ok = 1'h0;
reg \core_spro_ok$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [2:0] core_state_nia_wen;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *)
- reg core_stopped_i;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
wire [63:0] core_sv__data_o;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
reg core_xer_out = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *)
reg \core_xer_out$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
reg cu_st__rel_o_dly = 1'h0;
reg [6:0] cur_cur_vl = 7'h00;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
reg [6:0] \cur_cur_vl$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *)
reg d_cr_delay = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *)
reg \d_cr_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *)
reg d_reg_delay = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *)
reg \d_reg_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" *)
reg d_xer_delay = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" *)
reg \d_xer_delay$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
wire [6:0] dbg_core_dbg_core_dbg_dststep;
wire [2:0] dec2_xer_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *)
wire dec2_xer_out;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" *)
reg [1:0] delay = 2'h3;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" *)
reg [1:0] \delay$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
output eint_0__core__i;
output eint_2__core__i;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input eint_2__pad__i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
reg exec_fsm_state = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
reg \exec_fsm_state$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:954" *)
reg exec_insn_ready_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:953" *)
reg exec_insn_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:960" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" *)
reg exec_pc_ready_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:959" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" *)
reg exec_pc_valid_o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
reg [1:0] fetch_fsm_state = 2'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
reg [1:0] \fetch_fsm_state$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:944" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
reg fetch_insn_ready_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:941" *)
reg fetch_insn_valid_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:940" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *)
reg fetch_pc_ready_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:939" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
reg fetch_pc_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
reg [1:0] fsm_state = 2'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
reg [1:0] \fsm_state$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
output gpio_e10__core__i;
reg insn_done;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *)
input [15:0] int_level_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:698" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:697" *)
reg is_last;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:933" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *)
wire is_svp64_mode;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *)
reg [2:0] issue_fsm_state = 3'h0;
output mtwi_sda__pad__o;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
output mtwi_sda__pad__oe;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1077" *)
reg [63:0] new_dec;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
reg [6:0] new_svstate_dststep;
reg [1:0] new_svstate_svstep;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
reg [6:0] new_svstate_vl;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1096" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" *)
reg [63:0] new_tb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
wire [6:0] next_dststep;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:546" *)
wire [6:0] next_srcstep;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:920" *)
reg [63:0] nia = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:922" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:920" *)
reg [63:0] \nia$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *)
reg [63:0] pc;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:901" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *)
reg pc_changed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:901" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:899" *)
reg \pc_changed$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
input [63:0] pc_i;
reg pc_ok_delay = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
reg \pc_ok_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:852" *)
wire por_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" *)
wire pred_insn_ready_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:945" *)
reg pred_insn_valid_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:952" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950" *)
reg pred_mask_ready_i;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:951" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:949" *)
wire pred_mask_valid_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
input sdr_a_0__core__o;
input sram4k_3_wb__stb;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:25" *)
input sram4k_3_wb__we;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *)
reg sv_changed = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:902" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:900" *)
reg \sv_changed$next ;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *)
reg [63:0] svstate;
reg svstate_ok_delay = 1'h0;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
reg \svstate_ok_delay$next ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" *)
wire ti_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
reg update_svstate;
wire [7:0] xics_ics_icp_o_pri;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
wire [3:0] xics_ics_icp_o_src;
- assign \$100 = \$98 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last;
+ assign \$100 = \$98 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last;
assign \$102 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read;
assign \$105 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) 3'h4;
assign \$108 = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20;
assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
assign \$120 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
assign \$122 = \$118 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$120 ;
- assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$126 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$126 ;
- assign \$130 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed;
- assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0;
- assign \$134 = \$132 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last;
+ assign \$124 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$126 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$128 = \$124 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$126 ;
+ assign \$130 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed;
+ assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0;
+ assign \$134 = \$132 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last;
assign \$137 = cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:548" *) 1'h1;
assign \$140 = cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *) 1'h1;
assign \$142 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$150 ;
- assign \$154 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0;
- assign \$156 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$154 ;
- assign \$158 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *) is_svp64_mode;
- assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$162 ;
- assign \$166 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed;
- assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0;
- assign \$170 = \$168 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last;
+ assign \$154 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) 1'h0;
+ assign \$156 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) \$154 ;
+ assign \$158 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" *) is_svp64_mode;
+ assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$162 ;
+ assign \$166 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed;
+ assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0;
+ assign \$170 = \$168 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last;
assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$174 ;
- assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$180 ;
+ assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$180 ;
assign \$184 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
assign \$186 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
assign \$188 = \$184 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$186 ;
- assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$192 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$194 = \$190 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$192 ;
- assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
- assign \$198 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
- assign \$200 = \$196 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$198 ;
- assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$204 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$206 = \$202 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$204 ;
- assign \$209 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) 1'h1;
- assign \$208 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$209 ;
- assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
- assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
- assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$214 ;
- assign \$218 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$220 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$222 = \$218 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$220 ;
- assign \$224 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed;
- assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0;
- assign \$228 = \$226 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last;
- assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
- assign \$232 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
- assign \$234 = \$230 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$232 ;
- assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$238 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
+ assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$192 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$194 = \$190 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$192 ;
+ assign \$197 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) 1'h1;
+ assign \$196 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$197 ;
+ assign \$200 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
+ assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
+ assign \$204 = \$200 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$202 ;
+ assign \$206 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$210 = \$206 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$208 ;
+ assign \$212 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed;
+ assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0;
+ assign \$216 = \$214 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last;
+ assign \$218 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
+ assign \$220 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
+ assign \$222 = \$218 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$220 ;
+ assign \$224 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$228 = \$224 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$226 ;
+ assign \$231 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" *) 3'h4;
+ assign \$230 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$231 ;
+ assign \$234 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) 1'h0;
+ assign \$236 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) \$234 ;
+ assign \$238 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) core_corebusy_o;
assign \$23 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read;
- assign \$240 = \$236 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$238 ;
- assign \$243 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *) 3'h4;
- assign \$242 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$243 ;
- assign \$246 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0;
- assign \$248 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$246 ;
- assign \$250 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o;
- assign \$252 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$254 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$256 = \$252 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$254 ;
- assign \$258 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$25 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *) 1'h0;
- assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$262 = \$258 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$260 ;
- assign \$264 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:700" *) cur_cur_vl;
- assign \$266 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
- assign \$268 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *) 7'h01;
- assign \$270 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o;
- assign \$272 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *) core_corebusy_o;
- assign \$274 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o;
- assign \$276 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o;
- assign \$279 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1081" *) 1'h1;
- assign \$282 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1097" *) 1'h1;
- assign \$28 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:862" *) 1'h1;
- assign \$30 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) dbg_core_rst_o;
- assign \$32 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) rst;
- assign \$34 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" *) \$32 ;
+ assign \$240 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$242 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$244 = \$240 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$242 ;
+ assign \$246 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$250 = \$246 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$248 ;
+ assign \$252 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) cur_cur_vl;
+ assign \$254 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
+ assign \$256 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" *) 7'h01;
+ assign \$258 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) core_corebusy_o;
+ assign \$25 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) 1'h0;
+ assign \$260 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *) core_corebusy_o;
+ assign \$262 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o;
+ assign \$264 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o;
+ assign \$267 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" *) 1'h1;
+ assign \$270 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *) 1'h1;
+ assign \$28 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) 1'h1;
+ assign \$30 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *) dbg_core_rst_o;
+ assign \$32 = \$30 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *) rst;
+ assign \$34 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" *) \$32 ;
assign \$36 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly;
assign \$38 = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$36 ;
assign \$40 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst;
assign \$58 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
assign \$60 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
assign \$62 = \$58 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$60 ;
- assign \$64 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0;
- assign \$66 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$64 ;
- assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$70 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$72 = \$68 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$70 ;
- assign \$74 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed;
- assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0;
- assign \$78 = \$76 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) is_last;
+ assign \$64 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) 1'h0;
+ assign \$66 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) \$64 ;
+ assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$70 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$72 = \$68 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$70 ;
+ assign \$74 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed;
+ assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0;
+ assign \$78 = \$76 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) is_last;
assign \$80 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) dbg_core_stop_o;
assign \$82 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) core_coresync_rst;
assign \$84 = \$80 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *) \$82 ;
- assign \$86 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) 1'h0;
- assign \$88 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) \$86 ;
- assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) dbg_core_stop_o;
- assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) core_coresync_rst;
- assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) \$92 ;
- assign \$96 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *) sv_changed;
- assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" *) 1'h0;
+ assign \$86 = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) 1'h0;
+ assign \$88 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *) \$86 ;
+ assign \$90 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) dbg_core_stop_o;
+ assign \$92 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) core_coresync_rst;
+ assign \$94 = \$90 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *) \$92 ;
+ assign \$96 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *) sv_changed;
+ assign \$98 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" *) 1'h0;
always @(posedge clk)
fsm_state <= \fsm_state$next ;
always @(posedge clk)
always @* begin
if (\initial ) begin end
\delay$next = delay;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *)
casez (\$25 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:861" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */
1'h1:
\delay$next = \$27 [1:0];
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
{ \core_core_maxvl$next , \core_core_vl$next , \core_core_srcstep$next , \core_core_dststep$next , \core_core_subvl$next , \core_core_svstep$next , \core_dec$next , \core_eint$next , \core_msr$next , \core_core_pc$next } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc };
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
\core_raw_insn_i$next = dec2_raw_opcode_in;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
\core_bigendian_i$10$next = core_bigendian_i;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
\core_sv_a_nz$next = dec2_sv_a_nz;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
exec_insn_valid_i = 1'h1;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
- casez (\$256 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
+ casez (\$244 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
exec_pc_ready_i = 1'h1;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
- casez (\$262 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
+ casez (\$250 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */
1'h1:
- is_last = \$264 ;
+ is_last = \$252 ;
endcase
endcase
endcase
always @* begin
if (\initial ) begin end
\core_wen$11 = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" *)
casez (update_svstate)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" */
1'h1:
\core_wen$11 = 3'h4;
endcase
always @* begin
if (\initial ) begin end
\core_data_i$12 = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" *)
casez (update_svstate)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" */
1'h1:
- \core_data_i$12 = \$266 ;
+ \core_data_i$12 = \$254 ;
endcase
end
always @* begin
if (\initial ) begin end
exec_insn_ready_o = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */
1'h0:
exec_insn_ready_o = 1'h1;
endcase
if (\initial ) begin end
core_ivalid_i = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
1'h1:
core_ivalid_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" *)
- casez (\$268 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" *)
+ casez (\$256 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" */
1'h1:
core_ivalid_i = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_issue_i = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
1'h1:
core_issue_i = 1'h1;
endcase
if (\initial ) begin end
\exec_fsm_state$next = exec_fsm_state;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
1'h1:
\exec_fsm_state$next = 1'h1;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *)
- casez (\$270 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *)
+ casez (\$258 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *)
casez (exec_pc_ready_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */
1'h1:
\exec_fsm_state$next = 1'h0;
endcase
if (\initial ) begin end
exec_pc_valid_o = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */
1'h0:
/* empty */;
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *)
- casez (\$272 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *)
+ casez (\$260 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */
1'h1:
exec_pc_valid_o = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_dmi__addr = 5'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *)
casez (dbg_d_gpr_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" */
1'h1:
core_dmi__addr = dbg_d_gpr_addr[4:0];
endcase
always @* begin
if (\initial ) begin end
core_dmi__ren = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *)
casez (dbg_d_gpr_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" */
1'h1:
core_dmi__ren = 1'h1;
endcase
always @* begin
if (\initial ) begin end
dbg_d_gpr_data = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *)
casez (d_reg_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" */
1'h1:
dbg_d_gpr_data = core_dmi__data_o;
endcase
always @* begin
if (\initial ) begin end
dbg_d_gpr_ack = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" *)
casez (d_reg_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1026" */
1'h1:
dbg_d_gpr_ack = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_full_rd2__ren = 8'h00;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *)
casez (dbg_d_cr_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" */
1'h1:
core_full_rd2__ren = 8'hff;
endcase
always @* begin
if (\initial ) begin end
dbg_d_cr_data = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *)
casez (d_cr_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" */
1'h1:
- dbg_d_cr_data = \$274 ;
+ dbg_d_cr_data = \$262 ;
endcase
end
always @* begin
if (\initial ) begin end
dbg_d_cr_ack = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *)
casez (d_cr_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1038" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" */
1'h1:
dbg_d_cr_ack = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_full_rd__ren = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1042" *)
casez (dbg_d_xer_req)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1044" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1042" */
1'h1:
core_full_rd__ren = 3'h7;
endcase
always @* begin
if (\initial ) begin end
dbg_d_xer_data = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *)
casez (d_xer_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" */
1'h1:
- dbg_d_xer_data = \$276 ;
+ dbg_d_xer_data = \$264 ;
endcase
end
always @* begin
if (\initial ) begin end
dbg_d_xer_ack = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" *)
casez (d_xer_delay)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1048" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1046" */
1'h1:
dbg_d_xer_ack = 1'h1;
endcase
always @* begin
if (\initial ) begin end
core_issue__addr = 3'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
2'h0:
core_issue__addr = 3'h6;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */
2'h1:
/* empty */;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */
2'h2:
core_issue__addr = 3'h7;
endcase
always @* begin
if (\initial ) begin end
core_issue__ren = 1'h0;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
2'h0:
core_issue__ren = 1'h1;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */
2'h1:
/* empty */;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */
2'h2:
core_issue__ren = 1'h1;
endcase
always @* begin
if (\initial ) begin end
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
2'h0:
\fsm_state$next = 2'h1;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */
2'h1:
\fsm_state$next = 2'h2;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */
2'h2:
\fsm_state$next = 2'h3;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */
2'h3:
\fsm_state$next = 2'h0;
endcase
always @* begin
if (\initial ) begin end
new_dec = 64'h0000000000000000;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */
2'h1:
- new_dec = \$278 [63:0];
+ new_dec = \$266 [63:0];
endcase
end
always @* begin
if (\initial ) begin end
\core_issue__addr$13 = 3'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */
2'h1:
\core_issue__addr$13 = 3'h6;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */
2'h3:
\core_issue__addr$13 = 3'h7;
endcase
if (\initial ) begin end
core_issue__wen = 1'h0;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */
2'h1:
core_issue__wen = 1'h1;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */
2'h3:
core_issue__wen = 1'h1;
endcase
if (\initial ) begin end
core_issue__data_i = 64'h0000000000000000;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */
2'h1:
core_issue__data_i = new_dec;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */
2'h3:
core_issue__data_i = new_tb;
endcase
if (\initial ) begin end
new_tb = 64'h0000000000000000;
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */
2'h1:
/* empty */;
/* \nmigen.decoding = "TB_READ/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1089" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1087" */
2'h2:
/* empty */;
/* \nmigen.decoding = "TB_WRITE/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1093" */
2'h3:
- new_tb = \$281 [63:0];
+ new_tb = \$269 [63:0];
endcase
end
always @* begin
\cur_cur_vl$next = cur_cur_vl;
\cur_cur_maxvl$next = cur_cur_maxvl;
\dec2_cur_eint$next = xics_icp_core_irq_o;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:894" *)
casez (core_coresync_rst)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:896" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:894" */
1'h1:
{ \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next , \dec2_cur_dec$next , \dec2_cur_eint$next , \dec2_cur_msr$next , \dec2_cur_pc$next } = 225'h000000000000000000000000000000000000000000000000000000000;
endcase
\dec2_cur_msr$next = core_msr__data_o;
endcase
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" *)
casez (update_svstate)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:751" */
1'h1:
{ \cur_cur_maxvl$next , \cur_cur_vl$next , \cur_cur_srcstep$next , \cur_cur_dststep$next , \cur_cur_subvl$next , \cur_cur_svstep$next } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1069" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
casez (fsm_state)
/* \nmigen.decoding = "DEC_READ/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1072" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */
2'h0:
/* empty */;
/* \nmigen.decoding = "DEC_WRITE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1078" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1076" */
2'h1:
\dec2_cur_dec$next = new_dec;
endcase
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" */
1'h1:
core_wen = 3'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
casez (\$66 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" */
1'h1:
core_wen = 3'h1;
endcase
endcase
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
casez (\$72 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
casez ({ \$78 , \$74 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */
2'b1?:
core_wen = 3'h1;
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" */
1'h1:
core_wen = 3'h1;
endcase
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" */
1'h1:
core_data_i = pc_i;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
casez (\$88 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" */
1'h1:
core_data_i = nia;
endcase
endcase
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
casez (\$94 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
casez ({ \$100 , \$96 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */
2'b1?:
core_data_i = nia;
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" */
1'h1:
core_data_i = pc_i;
endcase
\nia$next = \$104 [63:0];
endcase
endcase
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:994" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:992" *)
casez (core_coresync_rst)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:994" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:992" */
1'h1:
\nia$next = 64'h0000000000000000;
endcase
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" */
1'h1:
{ new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
casez (\$128 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
casez ({ \$134 , \$130 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */
2'b1?:
begin
new_svstate_srcstep = 7'h00;
new_svstate_dststep = 7'h00;
end
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" */
default:
begin
new_svstate_srcstep = next_srcstep;
end
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" */
1'h1:
{ new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i;
endcase
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
casez (\$156 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" */
1'h1:
\issue_fsm_state$next = 3'h0;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" */
default:
\issue_fsm_state$next = 3'h2;
endcase
endcase
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:601" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" *)
casez (pred_insn_ready_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:601" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:600" */
1'h1:
\issue_fsm_state$next = 3'h4;
endcase
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *)
casez (pred_mask_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" */
1'h1:
\issue_fsm_state$next = 3'h5;
endcase
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" *)
casez (\$158 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
1'h1:
\issue_fsm_state$next = 3'h2;
endcase
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
\issue_fsm_state$next = 3'h6;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:686" *)
casez (exec_insn_ready_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:687" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:686" */
1'h1:
\issue_fsm_state$next = 3'h7;
endcase
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
casez (\$164 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
casez ({ \$170 , \$166 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */
2'b?1:
\issue_fsm_state$next = 3'h0;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */
2'b1?:
\issue_fsm_state$next = 3'h0;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" */
default:
\issue_fsm_state$next = 3'h5;
endcase
\issue_fsm_state$next = 3'h0;
endcase
end
- always @* begin
- if (\initial ) begin end
- core_stopped_i = 1'h0;
- (* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" *)
- casez (issue_fsm_state)
- /* \nmigen.decoding = "ISSUE_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" */
- 3'h0:
- (* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
- casez (\$176 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */
- 1'h1:
- /* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */
- default:
- core_stopped_i = 1'h1;
- endcase
- /* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
- 3'h1:
- /* empty */;
- /* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
- 3'h3:
- /* empty */;
- /* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
- 3'h4:
- /* empty */;
- /* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
- 3'h5:
- /* empty */;
- /* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
- 3'h2:
- /* empty */;
- /* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
- 3'h6:
- /* empty */;
- /* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
- 3'h7:
- (* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
- casez (\$182 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
- 1'h1:
- /* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */
- default:
- core_stopped_i = 1'h1;
- endcase
- endcase
- end
always @* begin
if (\initial ) begin end
dbg_core_stopped_i = 1'h0;
3'h0:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
- casez (\$188 )
+ casez (\$176 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */
1'h1:
/* empty */;
dbg_core_stopped_i = 1'h1;
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
- casez (\$194 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
+ casez (\$182 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
default:
dbg_core_stopped_i = 1'h1;
endcase
3'h0:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
- casez (\$200 )
+ casez (\$188 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */
1'h1:
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" */
1'h1:
\pc_changed$next = 1'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
- casez (\$206 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
+ casez (\$194 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *)
casez (pc_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:743" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" */
1'h1:
\pc_changed$next = 1'h1;
endcase
endcase
endcase
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
1'h1:
\pc_changed$next = 1'h0;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *)
- casez (\$208 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *)
+ casez (\$196 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" */
1'h1:
\pc_changed$next = 1'h1;
endcase
3'h0:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
- casez (\$216 )
+ casez (\$204 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */
1'h1:
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" */
1'h1:
update_svstate = 1'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
- casez (\$222 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
+ casez (\$210 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" *)
casez (exec_pc_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:695" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:694" */
1'h1:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" *)
- casez ({ \$228 , \$224 })
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:705" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" *)
+ casez ({ \$216 , \$212 })
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:704" */
2'b?1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:711" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" */
2'b1?:
update_svstate = 1'h1;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" */
default:
update_svstate = 1'h1;
endcase
endcase
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" */
1'h1:
update_svstate = 1'h1;
endcase
3'h0:
(* full_case = 32'd1 *)
(* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" *)
- casez (\$234 )
+ casez (\$222 )
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:559" */
1'h1:
/* empty */;
/* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:563" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:571" */
1'h1:
\sv_changed$next = 1'h1;
endcase
endcase
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
/* empty */;
/* \nmigen.decoding = "INSN_EXECUTE/6" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:685" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" */
3'h6:
/* empty */;
/* \nmigen.decoding = "EXECUTE_WAIT/7" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:690" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:689" */
3'h7:
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
- casez (\$240 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" *)
+ casez (\$228 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:692" */
1'h1:
/* empty */;
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:739" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:738" */
default:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" *)
casez (svstate_i_ok)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:745" */
1'h1:
\sv_changed$next = 1'h1;
endcase
endcase
endcase
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */
1'h0:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *)
casez (exec_insn_valid_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
1'h1:
\sv_changed$next = 1'h0;
endcase
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" *)
- casez (\$242 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:796" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" *)
+ casez (\$230 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:794" */
1'h1:
\sv_changed$next = 1'h1;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
fetch_insn_ready_i = 1'h1;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" *)
casez (fetch_insn_valid_o)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:580" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:579" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *)
- casez (\$248 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" *)
+ casez (\$236 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:584" */
1'h1:
insn_done = 1'h1;
endcase
endcase
endcase
(* full_case = 32'd1 *)
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:779" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *)
casez (exec_fsm_state)
/* \nmigen.decoding = "INSN_START/0" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:780" */
1'h0:
/* empty */;
/* \nmigen.decoding = "INSN_ACTIVE/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *)
- casez (\$250 )
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" *)
+ casez (\$238 )
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" */
1'h1:
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" *)
casez (exec_pc_ready_i)
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:802" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:800" */
1'h1:
insn_done = 1'h1;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
pred_insn_valid_i = 1'h1;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
pred_mask_ready_i = 1'h1;
endcase
3'h0:
/* empty */;
/* \nmigen.decoding = "INSN_WAIT/1" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:578" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:577" */
3'h1:
/* empty */;
/* \nmigen.decoding = "PRED_START/3" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:598" */
3'h3:
/* empty */;
/* \nmigen.decoding = "MASK_WAIT/4" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" */
3'h4:
/* empty */;
/* \nmigen.decoding = "PRED_SKIP/5" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:610" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:609" */
3'h5:
/* empty */;
/* \nmigen.decoding = "DECODE_SV/2" */
- /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:674" */
+ /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:673" */
3'h2:
{ \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_$signal$9$next , \core_core_core_exc_$signal$8$next , \core_core_core_exc_$signal$7$next , \core_core_core_exc_$signal$6$next , \core_core_core_exc_$signal$5$next , \core_core_core_exc_$signal$4$next , \core_core_core_exc_$signal$3$next , \core_core_core_exc_$signal$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, \dec2_exc_$signal$22 , \dec2_exc_$signal$21 , \dec2_exc_$signal$20 , \dec2_exc_$signal$19 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal , dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_cia, dec2_msr, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$15 , \dec2_cr_in2$14 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode };
endcase
assign \$112 = \$113 ;
assign \$136 = \$137 ;
assign \$139 = \$140 ;
- assign \$278 = \$279 ;
- assign \$281 = \$282 ;
+ assign \$266 = \$267 ;
+ assign \$269 = \$270 ;
assign dec2_sv_a_nz = 1'h0;
assign svstate_i_ok = 1'h0;
assign svstate_i = 32'd0;
reg \alui_l_r_alui$next ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
wire alui_l_s_alui;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
output cu_busy_o;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
wire \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
reg q_int = 1'h0;
wire [1:0] \$7 ;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
wire [1:0] \$9 ;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_clk;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:856" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *)
input coresync_rst;
(* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
input [1:0] data_i;
wire [31:0] be_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" *)
reg [31:0] be_out;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *)
output core_irq_o;
reg [7:0] min_pri;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" *)
reg [7:0] pending_priority;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *)
reg wb_ack = 1'h0;
wire [31:0] be_in;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" *)
reg [31:0] be_out;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input clk;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
reg [3:0] cur_idx0;
wire reg_is_debug;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" *)
wire reg_is_xive;
- (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
+ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:853" *)
input rst;
(* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" *)
wire wb_valid;
projects / soclayout.git / commitdiff