--- /dev/null
+
+ LOGICAL_SYNTHESIS = Yosys
+ PHYSICAL_SYNTHESIS = Coriolis
+ DESIGN_KIT = cmos45
+ YOSYS_FLATTEN = No
+ CHIP = chip
+ CORE = add
+ USE_CLOCKTREE = Yes
+ USE_DEBUG = No
+ USE_KITE = No
+ RM_CHIP = Yes
+
+ NETLISTS = $(shell cat netlists.txt)
+# PATTERNS = add_r
+
+
+ include ./mk/design-flow.mk
+
+# generate verilog file from python nmigen command
+add.v: add.py
+ python3 add.py
+
+chip_r.vst: add.vst
+ -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
+
+chip_r.ap: chip_r.vst
+
+
+blif: add.blif
+vst: add.vst
+
+lvx: lvx-chip_r
+druc: druc-chip_r
+dreal: dreal-chip_r
+flatph: flatph-chip_r
+view: cgt-chip_r
+
+layout: chip_r.ap
+gds: chip_r.gds
+gds_flat: chip_r_flat.gds
+cif: chip_r.cif
+
+view: cgt-chip_r
+sim: asimut-add_r
--- /dev/null
+# generate add.il ilang file with: python3 add.py
+#
+
+from nmigen import Elaboratable, Signal, Module
+from nmigen.cli import verilog
+
+# to get c4m-jtag
+# clone with $ git clone gitolite3@git.libre-soc.org:c4m-jtag.git
+# $ git clone gitolite3@git.libre-soc.org:nmigen-soc.git
+# for each: $ python3 setup.py develop --user
+
+from c4m.nmigen.jtag.tap import TAP, IOType
+
+
+class ADD(Elaboratable):
+ def __init__(self, width):
+ self.a = Signal(width)
+ self.b = Signal(width)
+ self.f = Signal(width)
+
+ # set up JTAG
+ self.jtag = TAP(ir_width=4)
+ self.jtag.bus.tck.name = 'tck'
+ self.jtag.bus.tms.name = 'tms'
+ self.jtag.bus.tdo.name = 'tdo'
+ self.jtag.bus.tdi.name = 'tdi'
+
+ # have to create at least one shift register
+ self.sr = self.jtag.add_shiftreg(ircode=4, length=3)
+
+ # sigh and one iotype
+ self.ios = self.jtag.add_io(name="test", iotype=IOType.In)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.submodules.jtag = jtag = self.jtag
+ m.d.comb += self.sr.i.eq(self.sr.o) # loopback test
+
+ # do a simple "add"
+ m.d.sync += self.f.eq(self.a + self.b)
+
+ return m
+
+
+def create_ilang(dut, ports, test_name):
+ vl = verilog.convert(dut, name=test_name, ports=ports)
+ with open("%s.v" % test_name, "w") as f:
+ f.write(vl)
+
+if __name__ == "__main__":
+ alu = ADD(width=4)
+ create_ilang(alu, [alu.a, alu.b, alu.f,
+ alu.jtag.bus.tck,
+ alu.jtag.bus.tms,
+ alu.jtag.bus.tdo,
+ alu.jtag.bus.tdi], "add")
--- /dev/null
+#!/usr/bin/env python
+
+from helpers import l, u, n
+
+
+chip = { 'pads.ioPadGauge' : 'pxlib',
+
+ # | Instance | Pad | To Core | From Core | Enable |
+ 'pads.instances' :[
+ # "a" input.
+ [ 'p_a0' , 'a(0)', 'a(0)' ],
+ [ 'p_a1' , 'a(1)', 'a(1)' ],
+ [ 'p_a2' , 'a(2)', 'a(2)' ],
+ [ 'p_a3' , 'a(3)', 'a(3)' ],
+ # "b" input.
+ [ 'p_b0' , 'b(0)', 'b(0)' ],
+ [ 'p_b1' , 'b(1)', 'b(1)' ],
+ [ 'p_b2' , 'b(2)', 'b(2)' ],
+ [ 'p_b3' , 'b(3)', 'b(3)' ],
+ # "f" output.
+ [ 'p_f0' , 'f(0)', 'f(0)' ], # , 'f_oe' ],
+ [ 'p_f1' , 'f(1)', 'f(1)' ], # , 'f_oe' ],
+ [ 'p_f2' , 'f(2)', 'f(2)' ], # , 'f_oe' ],
+ [ 'p_f3' , 'f(3)', 'f(3)' ], # , 'f_oe' ],
+ # JTAG
+ [ 'p_tck_0' , 'tck', 'tck'], # 2nd clock
+ [ 'p_tms_0' , 'tms', 'tms'],
+ [ 'p_tdo_0' , 'tdo', 'tdo'],
+ [ 'p_tdi_0' , 'tdi', 'tdi'],
+ ],
+ 'pads.south' :
+ [ 'p_a1', 'p_vddick_0', 'p_vssick_0' , 'p_a0', 'p_a2', 'p_b3', ],
+ 'pads.east' :
+ [ 'p_tck_0', # 2nd clock
+ 'p_tms_0', 'p_tdo_0', 'p_tdi_0',
+ 'p_b2' ],
+ 'pads.north' :
+ [ 'p_b1', 'p_vddeck_0', 'p_b0', 'p_vsseck_0', 'rst' ],
+ 'pads.west' :
+ [ 'p_f3', 'p_f2' , 'p_clk_0', 'p_f1' , 'p_f0', 'p_a3' ],
+ 'core.size' : ( l( 1200), l( 1200) ),
+ 'chip.size' : ( l(3200), l(3200) ),
+ 'pads.useCoreSize' : True,
+ 'chip.clockTree' : True,
+ }
+
--- /dev/null
+
+from Hurricane import DebugSession
+
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) )
+#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) )
--- /dev/null
+# -*- Mode:Python -*-
+
+from __future__ import print_function
+import os
+import Cfg
+import CRL
+import Viewer
+#import node180.scn6m_deep_09
+import symbolic.cmos45
+from helpers import overlay, l, u, n
+
+if os.environ.has_key('CELLS_TOP'):
+ cellsTop = os.environ['CELLS_TOP']
+else:
+ cellsTop = '../../../alliance-check-toolkit/cells'
+with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
+ cfg.misc.catchCore = False
+ cfg.misc.info = False
+ cfg.misc.paranoid = False
+ cfg.misc.bug = False
+ cfg.misc.logMode = True
+ cfg.misc.verboseLevel1 = True
+ cfg.misc.verboseLevel2 = True
+ cfg.etesian.graphics = 3
+ cfg.etesian.spaceMargin = 0.05
+ cfg.etesian.aspectRatio = 1.0
+ cfg.anabatic.edgeLenght = 24
+ cfg.anabatic.edgeWidth = 8
+ cfg.anabatic.topRoutingLayer = 'METAL5'
+ cfg.katana.eventsLimit = 4000000
+ cfg.etesian.effort = 2
+ cfg.etesian.uniformDensity = True
+ cfg.katana.hTracksReservedLocal = 7
+ cfg.katana.vTracksReservedLocal = 6
+ Viewer.Graphics.setStyle( 'Alliance.Classic [black]' )
+ af = CRL.AllianceFramework.get()
+ env = af.getEnvironment()
+ env.setCLOCK( '^clk|^ck|^tck' )
+ env.addSYSTEM_LIBRARY( library=cellsTop+'/niolib', mode=CRL.Environment.Prepend )
+ env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
+print( ' o Successfully run "<>/coriolis2/settings.py".' )
+print( ' - CELLS_TOP = "{}"'.format(cellsTop) )
--- /dev/null
+
+from __future__ import print_function
+import sys
+import traceback
+import CRL
+import helpers
+from helpers.io import ErrorMessage
+from helpers.io import WarningMessage
+from helpers import trace
+from helpers import l, u, n
+import plugins
+from Hurricane import DbU
+from plugins.alpha.block.block import Block
+from plugins.alpha.block.configuration import IoPin
+from plugins.alpha.block.configuration import GaugeConf
+from plugins.alpha.core2chip.niolib import CoreToChip
+from plugins.alpha.chip.configuration import ChipConf
+from plugins.alpha.chip.chip import Chip
+
+
+af = CRL.AllianceFramework.get()
+
+
+def scriptMain ( **kw ):
+ """The mandatory function to be called by Coriolis CGT/Unicorn."""
+ global af
+ rvalue = True
+ try:
+ helpers.setTraceLevel( 550 )
+ usePadsPosition = True
+ buildChip = True
+ cell, editor = plugins.kwParseMain( **kw )
+ cell = af.getCell( 'add', CRL.Catalog.State.Logical )
+ if cell is None:
+ print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to load cell "{}".'.format('adder') ))
+ sys.exit( 1 )
+ if editor: editor.setCell( cell )
+ # Spec:
+ # | Side | Pos | Instance | Pad net |Core net | Direction |
+ ioPadsSpec = [
+ (IoPin.SOUTH, None, 'p_a0' , 'a(0)' , 'a(0)' )
+ , (IoPin.SOUTH, None, 'p_a1' , 'a(1)' , 'a(1)' )
+ , (IoPin.SOUTH, None, 'iopower_0' , 'iovdd' )
+ , (IoPin.SOUTH, None, 'power_0' , 'vdd' )
+ , (IoPin.SOUTH, None, 'p_a2' , 'a(2)' , 'a(2)' )
+ , (IoPin.SOUTH, None, 'p_b3' , 'b(3)' , 'b(3)' )
+ , (IoPin.EAST , None, 'p_tms_0' , 'tms' , 'tms' )
+ , (IoPin.EAST , None, 'p_tdo_0' , 'tdo' , 'tdo' )
+ , (IoPin.EAST , None, 'ground_0' , 'vss' )
+ , (IoPin.EAST , None, 'p_clk' , 'clk' , 'clk' )
+ , (IoPin.EAST , None, 'p_tck' , 'tck' , 'tck' )
+ , (IoPin.EAST , None, 'p_tdi_0' , 'tdi' , 'tdi' )
+ , (IoPin.EAST , None, 'p_b2' , 'b(2)' , 'b(2)' )
+ , (IoPin.NORTH, None, 'ioground_0' , 'iovss' )
+ , (IoPin.NORTH, None, 'p_b1' , 'b(1)' , 'b(1)' )
+ , (IoPin.NORTH, None, 'ground_1' , 'vss' )
+ , (IoPin.NORTH, None, 'p_b0' , 'b(0)' , 'b(0)' )
+ , (IoPin.NORTH, None, 'rst' , 'rst' , 'rst' )
+ , (IoPin.WEST , None, 'p_f3' , 'f(3)' , 'f(3)' )
+ , (IoPin.WEST , None, 'p_f2' , 'f(2)' , 'f(2)' )
+ , (IoPin.WEST , None, 'power_1' , 'vdd' )
+ , (IoPin.WEST , None, 'p_f1' , 'f(1)' , 'f(1)' )
+ , (IoPin.WEST , None, 'p_f0' , 'f(0)' , 'f(0)' )
+ , (IoPin.WEST , None, 'p_a3' , 'a(3)' , 'a(3)' )
+ ]
+ adderConf = ChipConf( cell, ioPads=ioPadsSpec )
+ adderConf.cfg.etesian.bloat = 'nsxlib'
+ adderConf.cfg.etesian.uniformDensity = True
+ adderConf.cfg.etesian.aspectRatio = 1.0
+ adderConf.cfg.etesian.spaceMargin = 0.05
+ adderConf.cfg.block.spareSide = l(700)
+ adderConf.cfg.chip.padCoreSide = 'North'
+ adderConf.editor = editor
+ adderConf.useSpares = True
+ adderConf.useClockTree = True
+ adderConf.bColumns = 2
+ adderConf.bRows = 2
+ adderConf.chipConf.name = 'chip'
+ adderConf.chipConf.ioPadGauge = 'niolib'
+ adderConf.coreSize = ( l(2000), l(2000) )
+ adderConf.chipSize = ( l(5900), l(5900) )
+ adderToChip = CoreToChip( adderConf )
+ adderToChip.buildChip()
+ chipBuilder = Chip( adderConf )
+ chipBuilder.doChipFloorplan()
+ rvalue = chipBuilder.doPnR()
+ chipBuilder.save()
+ except Exception, e:
+ helpers.io.catch( e )
+ rvalue = False
+ sys.stdout.flush()
+ sys.stderr.flush()
+ return rvalue
--- /dev/null
+../mksym.sh
\ No newline at end of file
--- /dev/null
+add
+fsm
+idblock
+irblock
+jtag
projects / soclayout.git / commitdiff