enabling experiments9 new LibreSOCMem fake blackbox SRAM

diff --git a/experiments9/LibreSOCMem.py b/experiments9/LibreSOCMem.py
index eaf9fe23212534512b20240d1f8e42c9b7e4af66..2d137094a9f14c7361120f79140945e564af4cc5 100644 (file)
--- a/experiments9/LibreSOCMem.py
+++ b/experiments9/LibreSOCMem.py
@@ -208,20 +208,20 @@ def _load():
 
     lib = Library.create(rootlib, 'LibreSOCMem')
 
-    cell = Cell.create(lib, 'real_sram')
+    cell = Cell.create(lib, 'spblock_512w64b8w')
     with UpdateSession():
         cell.setAbutmentBox(Box(
-            u(0.0), u(0.0), u(110.0), u(100.0),
+            u(0.0), u(0.0), u(110.0), u(2.5),
         ))
         nets = {
             '*': Net.create(cell, '*'),
             'clk': Net.create(cell, 'clk'),
-            'vdd': Net.create(cell, 'vdd'),
-            'vss': Net.create(cell, 'vss'),
+            #'vdd': Net.create(cell, 'vdd'),
+            #'vss': Net.create(cell, 'vss'),
         }
-        for name, qty in (('a', 8),
-                          ('d', 63),
-                          ('q', 63),
+        for name, qty in (('a', 9),
+                          ('d', 64),
+                          ('q', 64),
                           ('we', 8),
                       ):
             for i in range(qty):
@@ -232,9 +232,9 @@ def _load():
         x = 0.135*20
         wid = 0.135 / 2
         step = wid*10
-        for name, qty in (('a', 8),
-                          ('d', 63),
-                          ('q', 63),
+        for name, qty in (('a', 9),
+                          ('d', 64),
+                          ('q', 64),
                           ('we', 8),
                       ):
             for i in range(qty):
@@ -296,95 +296,97 @@ def _load():
             tech, net, 'pimplant',
             ((0.115,0.195),(0.115,0.365),(0.285,0.365),(0.285,0.195),(0.115,0.195)),
         )
-        net = nets['vss']
-        createRL(
-            tech, net, 'pwell',
-            ((-0.12,-0.32),(-0.12,1.92),(1.72,1.92),(1.72,-0.32),(-0.12,-0.32)),
-        )
-        createRL(
-            tech, net, 'metal1',
-            ((0.0,0.0),(0.0,0.48),(1.6,0.48),(1.6,0.0),(0.0,0.0)),
-        )
         if False:
-            Vertical.create(
-                net, tech.getLayer('metal1.pin'),
+            net = nets['vss']
+            createRL(
+                tech, net, 'pwell',
+                ((-0.12,-0.32),(-0.12,1.92),(1.72,1.92),(1.72,-0.32),(-0.12,-0.32)),
+            )
+            createRL(
+                tech, net, 'metal1',
+                ((0.0,0.0),(0.0,0.48),(1.6,0.48),(1.6,0.0),(0.0,0.0)),
+            )
+            if False:
+                Vertical.create(
+                    net, tech.getLayer('metal1.pin'),
+                    u(0.8), u(1.6), u(0.0), u(0.48),
+                )
+            pin = Vertical.create(
+                net, tech.getLayer('metal1'),
                 u(0.8), u(1.6), u(0.0), u(0.48),
             )
-        pin = Vertical.create(
-            net, tech.getLayer('metal1'),
-            u(0.8), u(1.6), u(0.0), u(0.48),
-        )
-        net.setExternal(True)
-        NetExternalComponents.setExternal(pin)
-        createRL(
-            tech, net, 'active',
-            ((0.12,0.2),(0.12,0.36),(0.28,0.36),(0.28,0.2),(0.12,0.2)),
-        )
-        createRL(
-            tech, net, 'active',
-            ((0.9625,0.3075),(1.0375,0.3075),(1.0375,0.3825),(0.9625,0.3825),(0.9625,0.3075)),
-        )
-        createRL(
-            tech, net, 'contact',
-            ((0.1675,0.2475),(0.2325,0.2475),(0.2325,0.3125),(0.1675,0.3125),(0.1675,0.2475)),
-        )
-        createRL(
-            tech, net, 'contact',
-            ((0.9675,0.3125),(1.0325,0.3125),(1.0325,0.3775),(0.9675,0.3775),(0.9675,0.3125)),
-        )
+            net.setExternal(True)
+            NetExternalComponents.setExternal(pin)
+            createRL(
+                tech, net, 'active',
+                ((0.12,0.2),(0.12,0.36),(0.28,0.36),(0.28,0.2),(0.12,0.2)),
+            )
+            createRL(
+                tech, net, 'active',
+                ((0.9625,0.3075),(1.0375,0.3075),(1.0375,0.3825),(0.9625,0.3825),(0.9625,0.3075)),
+            )
+            createRL(
+                tech, net, 'contact',
+                ((0.1675,0.2475),(0.2325,0.2475),(0.2325,0.3125),(0.1675,0.3125),(0.1675,0.2475)),
+            )
+            createRL(
+                tech, net, 'contact',
+                ((0.9675,0.3125),(1.0325,0.3125),(1.0325,0.3775),(0.9675,0.3775),(0.9675,0.3125)),
+            )
         net = nets['*']
         createRL(
             tech, net, 'active',
             ((1.105,3.8),(1.4375,3.8),(1.4375,2.2),(0.9625,2.2),(0.9625,3.8),(1.105,3.8)),
         )
-        net = nets['vdd']
-        createRL(
-            tech, net, 'nwell',
-            ((-0.12,1.92),(-0.12,4.32),(1.72,4.32),(1.72,1.92),(-0.12,1.92)),
-        )
-        createRL(
-            tech, net, 'metal1',
-            ((0.0,3.52),(0.0,4.0),(1.6,4.0),(1.6,3.52),(0.0,3.52)),
-        )
         if False:
-            Vertical.create(
-                net, tech.getLayer('metal1.pin'),
+            net = nets['vdd']
+            createRL(
+                tech, net, 'nwell',
+                ((-0.12,1.92),(-0.12,4.32),(1.72,4.32),(1.72,1.92),(-0.12,1.92)),
+            )
+            createRL(
+                tech, net, 'metal1',
+                ((0.0,3.52),(0.0,4.0),(1.6,4.0),(1.6,3.52),(0.0,3.52)),
+            )
+            if False:
+                Vertical.create(
+                    net, tech.getLayer('metal1.pin'),
+                    u(0.8), u(1.6), u(3.52), u(4.0),
+                )
+            pin = Vertical.create(
+                net, tech.getLayer('metal1'),
                 u(0.8), u(1.6), u(3.52), u(4.0),
             )
-        pin = Vertical.create(
-            net, tech.getLayer('metal1'),
-            u(0.8), u(1.6), u(3.52), u(4.0),
-        )
-        net.setExternal(True)
-        NetExternalComponents.setExternal(pin)
-        createRL(
-            tech, net, 'active',
-            ((0.52,3.6),(0.52,3.76),(0.68,3.76),(0.68,3.6),(0.52,3.6)),
-        )
-        createRL(
-            tech, net, 'active',
-            ((0.9625,3.5675),(1.0375,3.5675),(1.0375,3.7825),(0.9625,3.7825),(0.9625,3.5675)),
-        )
-        createRL(
-            tech, net, 'active',
-            ((0.1625,3.6025),(0.2375,3.6025),(0.2375,3.6775),(0.1625,3.6775),(0.1625,3.6025)),
-        )
-        createRL(
-            tech, net, 'contact',
-            ((0.5675,3.6475),(0.6325,3.6475),(0.6325,3.7125),(0.5675,3.7125),(0.5675,3.6475)),
-        )
-        createRL(
-            tech, net, 'contact',
-            ((0.9675,3.5725),(1.0325,3.5725),(1.0325,3.6375),(0.9675,3.6375),(0.9675,3.5725)),
-        )
-        createRL(
-            tech, net, 'contact',
-            ((0.9675,3.7125),(1.0325,3.7125),(1.0325,3.7775),(0.9675,3.7775),(0.9675,3.7125)),
-        )
-        createRL(
-            tech, net, 'contact',
-            ((0.1675,3.6075),(0.2325,3.6075),(0.2325,3.6725),(0.1675,3.6725),(0.1675,3.6075)),
-        )
+            net.setExternal(True)
+            NetExternalComponents.setExternal(pin)
+            createRL(
+                tech, net, 'active',
+                ((0.52,3.6),(0.52,3.76),(0.68,3.76),(0.68,3.6),(0.52,3.6)),
+            )
+            createRL(
+                tech, net, 'active',
+                ((0.9625,3.5675),(1.0375,3.5675),(1.0375,3.7825),(0.9625,3.7825),(0.9625,3.5675)),
+            )
+            createRL(
+                tech, net, 'active',
+                ((0.1625,3.6025),(0.2375,3.6025),(0.2375,3.6775),(0.1625,3.6775),(0.1625,3.6025)),
+            )
+            createRL(
+                tech, net, 'contact',
+                ((0.5675,3.6475),(0.6325,3.6475),(0.6325,3.7125),(0.5675,3.7125),(0.5675,3.6475)),
+            )
+            createRL(
+                tech, net, 'contact',
+                ((0.9675,3.5725),(1.0325,3.5725),(1.0325,3.6375),(0.9675,3.6375),(0.9675,3.5725)),
+            )
+            createRL(
+                tech, net, 'contact',
+                ((0.9675,3.7125),(1.0325,3.7125),(1.0325,3.7775),(0.9675,3.7775),(0.9675,3.7125)),
+            )
+            createRL(
+                tech, net, 'contact',
+                ((0.1675,3.6075),(0.2325,3.6075),(0.2325,3.6725),(0.1675,3.6725),(0.1675,3.6075)),
+            )
         net = nets['*']
         createRL(
             tech, net, 'active',

diff --git a/experiments9/coriolis2/settings.py b/experiments9/coriolis2/settings.py
index c938abe158e23b9a030c41f547e2d2bfb8612e3e..8ed5fad0b4fab45e0f11cecc2d746c61907b4e9b 100644 (file)
--- a/experiments9/coriolis2/settings.py
+++ b/experiments9/coriolis2/settings.py
@@ -11,7 +11,6 @@ import symbolic.cmos45  # do not remove
 import os
 
 import LibreSOCMem
-
 LibreSOCMem.setup()
 
 if os.environ.has_key('CELLS_TOP'):
@@ -35,7 +34,10 @@ def createSramBlackbox ():
                                 'SRAM Cell "{}" not found.' \
                                .format(sramName) )
     sram.setAbstractedSupply( True )
-    blackboxeNames = [ 'spblock_512w64b8w'
+    blackboxeNames = [ 'spblock_512w64b8w_0',
+                       'spblock_512w64b8w_1',
+                       'spblock_512w64b8w_2',
+                       'spblock_512w64b8w_3',
                      ]
     for blackboxName in blackboxeNames:
         cell     = Cell.create( lib, blackboxName )
@@ -125,8 +127,8 @@ Viewer.Graphics.setStyle('Alliance.Classic [black]')
 # XXX cannot run this in non-NDA'd mode because there is no
 # equivalent to NDA.node180.tsmc_c018.LibreSOCMem (or PLL)
 # TODO: create a fake one
-#with overlay.UpdateSession():
-#    createSramBlackbox()
+with overlay.UpdateSession():
+    createSramBlackbox()
 
 print( '  o  Successfully run "<>/coriolis2/settings.py".' )
 print( '     - CELLS_TOP = "{}"'.format(cellsTop) )

diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
index d504dacb718747f10a5eef328afa01bb87d07d83..77cd9a94f069f6a4c2727c0af0561a1de94f9683 100644 (file)
--- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v
+++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v
@@ -193401,7 +193401,7 @@ module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ac
   assign \$1  = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb;
   always @(posedge clk)
     sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
-  spblock_512w64b8w spblock_512w64b8w (
+  spblock_512w64b8w spblock_512w64b8w_3 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193545,7 +193545,7 @@ module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ac
   assign \$1  = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb;
   always @(posedge clk)
     sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
-   spblock_512w64b8w spblock_512w64b8w  (
+   spblock_512w64b8w spblock_512w64b8w_0 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193689,7 +193689,7 @@ module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ac
   assign \$1  = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb;
   always @(posedge clk)
     sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
-   spblock_512w64b8w spblock_512w64b8w (
+   spblock_512w64b8w spblock_512w64b8w_1 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193833,7 +193833,7 @@ module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ac
   assign \$1  = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb;
   always @(posedge clk)
     sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
-   spblock_512w64b8w spblock_512w64b8w (
+   spblock_512w64b8w spblock_512w64b8w_2 (
     .a(a),
     .clk(clk),
     .d(d),