From: Luke Kenneth Casson Leighton Date: Sat, 22 Feb 2020 11:35:29 +0000 (+0000) Subject: move Makefile3/4 to experiments3 X-Git-Tag: partial-core-ls180-gdsii~219 X-Git-Url: https://git.libre-soc.org/?p=soclayout.git;a=commitdiff_plain;h=6149c8598580e025b636d28a5de5f2bf7183cc98 move Makefile3/4 to experiments3 --- diff --git a/Makefile3 b/Makefile3 deleted file mode 100755 index f7f0e15..0000000 --- a/Makefile3 +++ /dev/null @@ -1,26 +0,0 @@ -# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*- - - LOGICAL_SYNTHESIS = Yosys - PHYSICAL_SYNTHESIS = Coriolis - DESIGN_KIT = sxlib - -# YOSYS_FLATTEN = Yes - USE_CLOCKTREE = Yes - USE_DEBUG = No - USE_KITE = No - - NETLISTS = $(shell cat nets3.txt) - - VST_FLAGS = --vst-use-concat - - include ./mk/design-flow.mk - - -blif: test_part_add.blif -vst: test_part_add.vst -layout: test_part_add_cts_r.ap -gds: test_part_add_cts_r.gds - -lvx: lvx-test_part_add_cts_r -druc: druc-test_part_add_cts_r -view: cgt-test_part_add_cts_r diff --git a/examples/test_part_add.py b/examples/test_part_add.py deleted file mode 100644 index 19527e4..0000000 --- a/examples/test_part_add.py +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/env python3 -# SPDX-License-Identifier: LGPL-2.1-or-later -# See Notices.txt for copyright information - -from nmigen import Signal, Module, Elaboratable -from nmigen.cli import rtlil - -from ieee754.part.partsig import PartitionedSignal - -def create_ilang(dut, traces, test_name): - vl = rtlil.convert(dut, ports=traces, name=test_name) - with open("%s.il" % test_name, "w") as f: - f.write(vl) - - - -class TestAddMod(Elaboratable): - def __init__(self, width, partpoints): - self.partpoints = partpoints - self.a = PartitionedSignal(partpoints, width) - self.b = PartitionedSignal(partpoints, width) - self.add_output = Signal(width) - self.carry_in = Signal(len(partpoints)+1) - self.add_carry_out = Signal(len(partpoints)+1) - - def elaborate(self, platform): - m = Module() - comb = m.d.comb - sync = m.d.sync - self.a.set_module(m) - self.b.set_module(m) - # add - add_out, add_carry = self.a.add_op(self.a, self.b, - self.carry_in) - sync += self.add_output.eq(add_out) - sync += self.add_carry_out.eq(add_carry) - - return m - -if __name__ == '__main__': - width = 16 - pmask = Signal(3) # divide into 4-bits - module = TestAddMod(width, pmask) - - create_ilang(module, - [pmask, - module.a.sig, - module.b.sig, - module.add_output, - module.carry_in, - module.add_carry_out, - ], - "test_part_add") - print (dir(module)) - add_1 = module.a.m.submodules.add_1 - print (dir(add_1.part_pts)) - create_ilang(add_1, - [pmask, - add_1.a, - add_1.b, - add_1.output, - add_1.carry_in, - add_1.carry_out, - ], - "test_add") diff --git a/experiments3/Makefile3 b/experiments3/Makefile3 new file mode 100755 index 0000000..f7f0e15 --- /dev/null +++ b/experiments3/Makefile3 @@ -0,0 +1,26 @@ +# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*- + + LOGICAL_SYNTHESIS = Yosys + PHYSICAL_SYNTHESIS = Coriolis + DESIGN_KIT = sxlib + +# YOSYS_FLATTEN = Yes + USE_CLOCKTREE = Yes + USE_DEBUG = No + USE_KITE = No + + NETLISTS = $(shell cat nets3.txt) + + VST_FLAGS = --vst-use-concat + + include ./mk/design-flow.mk + + +blif: test_part_add.blif +vst: test_part_add.vst +layout: test_part_add_cts_r.ap +gds: test_part_add_cts_r.gds + +lvx: lvx-test_part_add_cts_r +druc: druc-test_part_add_cts_r +view: cgt-test_part_add_cts_r diff --git a/experiments3/Makefile4 b/experiments3/Makefile4 new file mode 100755 index 0000000..d23ee75 --- /dev/null +++ b/experiments3/Makefile4 @@ -0,0 +1,26 @@ +# -*- explicit-buffer-name: "Makefile<6502/cmos45>" -*- + + LOGICAL_SYNTHESIS = Yosys + PHYSICAL_SYNTHESIS = Coriolis + DESIGN_KIT = sxlib + +# YOSYS_FLATTEN = Yes + USE_CLOCKTREE = Yes + USE_DEBUG = No + USE_KITE = No + + NETLISTS = $(shell cat nets4.txt) + + VST_FLAGS = --vst-use-concat + + include ./mk/design-flow.mk + + +blif: test_add.blif +vst: test_add.vst +layout: test_add_cts_r.ap +gds: test_add_cts_r.gds + +lvx: lvx-test_add_cts_r +druc: druc-test_add_cts_r +view: cgt-test_add_cts_r diff --git a/experiments3/coriolis2/__init__.py b/experiments3/coriolis2/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/experiments3/coriolis2/katana.py b/experiments3/coriolis2/katana.py new file mode 100644 index 0000000..442b2fc --- /dev/null +++ b/experiments3/coriolis2/katana.py @@ -0,0 +1,12 @@ + +from Hurricane import DebugSession + +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n543' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'dl(6)' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'n0_dl_7_0_6' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n822' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n734' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12509_n1386' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n763' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12494_n800' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'abc_12491_n428_1' ) ) diff --git a/experiments3/coriolis2/settings.py b/experiments3/coriolis2/settings.py new file mode 100644 index 0000000..95cc039 --- /dev/null +++ b/experiments3/coriolis2/settings.py @@ -0,0 +1,56 @@ +# -*- Mode:Python -*- + +import os +import Cfg +import CRL +import Viewer +#import node180.scn6m_deep_09 +import symbolic.cmos +from helpers import l, u, n + + +Cfg.Configuration.pushDefaultPriority( Cfg.Parameter.Priority.UserFile ) + + +Viewer.Graphics.setStyle( 'Alliance.Classic [black]' ) + +Cfg.getParamBool ( 'misc.catchCore' ).setBool ( False ) +Cfg.getParamBool ( 'misc.info' ).setBool ( False ) +Cfg.getParamBool ( 'misc.paranoid' ).setBool ( False ) +Cfg.getParamBool ( 'misc.bug' ).setBool ( False ) +Cfg.getParamBool ( 'misc.logMode' ).setBool ( True ) +Cfg.getParamBool ( 'misc.verboseLevel1' ).setBool ( True ) +Cfg.getParamBool ( 'misc.verboseLevel2' ).setBool ( True ) +Cfg.getParamInt ( 'misc.minTraceLevel' ).setInt ( 159 ) +Cfg.getParamInt ( 'misc.maxTraceLevel' ).setInt ( 160 ) +Cfg.getParamEnumerate ( 'etesian.effort' ).setInt ( 2 ) +Cfg.getParamPercentage( 'etesian.spaceMargin' ).setPercentage( 20.0 ) +Cfg.getParamPercentage( 'etesian.aspectRatio' ).setPercentage( 100.0 ) +Cfg.getParamBool ( 'etesian.uniformDensity' ).setBool ( True ) +Cfg.getParamInt ( 'anabatic.edgeLenght' ).setInt ( 24 ) +Cfg.getParamInt ( 'anabatic.edgeWidth' ).setInt ( 8 ) +Cfg.getParamString ( 'anabatic.topRoutingLayer' ).setString ( 'METAL5') +Cfg.getParamInt ( 'katana.eventsLimit' ).setInt ( 1000000 ) +Cfg.getParamInt ( 'katana.hTracksReservedLocal' ).setInt ( 7 ) +Cfg.getParamInt ( 'katana.vTracksReservedLocal' ).setInt ( 6 ) +#Cfg.getParamInt ( 'clockTree.minimumSide' ).setInt ( l(1000) ) + +Cfg.Configuration.popDefaultPriority() + +#cellsTop = os.path.abspath( os.getcwd()+'/../cells' ) +if os.environ.has_key('CELLS_TOP'): + cellsTop = os.environ['CELLS_TOP'] +else: + cellsTop = '../../../cells' + +af = CRL.AllianceFramework.get() +env = af.getEnvironment() +env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend ) +env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend ) +env.setCLOCK( '^clk$|m_clock' ) +env.setPOWER( 'vdd' ) +env.setGROUND( 'vss' ) + + +print 'Successfully read user configuration' + diff --git a/experiments3/mksym.sh b/experiments3/mksym.sh new file mode 120000 index 0000000..645c607 --- /dev/null +++ b/experiments3/mksym.sh @@ -0,0 +1 @@ +../mksym.sh \ No newline at end of file diff --git a/experiments3/nets3.txt b/experiments3/nets3.txt new file mode 100644 index 0000000..886cd9c --- /dev/null +++ b/experiments3/nets3.txt @@ -0,0 +1 @@ +test_part_add add_1 ripple diff --git a/experiments3/nets4.txt b/experiments3/nets4.txt new file mode 100644 index 0000000..5d96404 --- /dev/null +++ b/experiments3/nets4.txt @@ -0,0 +1 @@ +test_add ripple diff --git a/experiments3/test_part_add.py b/experiments3/test_part_add.py new file mode 100644 index 0000000..19527e4 --- /dev/null +++ b/experiments3/test_part_add.py @@ -0,0 +1,65 @@ +#!/usr/bin/env python3 +# SPDX-License-Identifier: LGPL-2.1-or-later +# See Notices.txt for copyright information + +from nmigen import Signal, Module, Elaboratable +from nmigen.cli import rtlil + +from ieee754.part.partsig import PartitionedSignal + +def create_ilang(dut, traces, test_name): + vl = rtlil.convert(dut, ports=traces, name=test_name) + with open("%s.il" % test_name, "w") as f: + f.write(vl) + + + +class TestAddMod(Elaboratable): + def __init__(self, width, partpoints): + self.partpoints = partpoints + self.a = PartitionedSignal(partpoints, width) + self.b = PartitionedSignal(partpoints, width) + self.add_output = Signal(width) + self.carry_in = Signal(len(partpoints)+1) + self.add_carry_out = Signal(len(partpoints)+1) + + def elaborate(self, platform): + m = Module() + comb = m.d.comb + sync = m.d.sync + self.a.set_module(m) + self.b.set_module(m) + # add + add_out, add_carry = self.a.add_op(self.a, self.b, + self.carry_in) + sync += self.add_output.eq(add_out) + sync += self.add_carry_out.eq(add_carry) + + return m + +if __name__ == '__main__': + width = 16 + pmask = Signal(3) # divide into 4-bits + module = TestAddMod(width, pmask) + + create_ilang(module, + [pmask, + module.a.sig, + module.b.sig, + module.add_output, + module.carry_in, + module.add_carry_out, + ], + "test_part_add") + print (dir(module)) + add_1 = module.a.m.submodules.add_1 + print (dir(add_1.part_pts)) + create_ilang(add_1, + [pmask, + add_1.a, + add_1.b, + add_1.output, + add_1.carry_in, + add_1.carry_out, + ], + "test_add") diff --git a/nets3.txt b/nets3.txt deleted file mode 100644 index 886cd9c..0000000 --- a/nets3.txt +++ /dev/null @@ -1 +0,0 @@ -test_part_add add_1 ripple