argh, found the blackbox problem: yosys is "doing the right thing" and
[soclayout.git] / experiments10 /
7 days ago Luke Kenneth Casso... rename JTAG port in adder test experiments10_verilog...
2021-04-01 Luke Kenneth Casso... run doChipFloorplan in experiments10
2021-04-01 Luke Kenneth Casso... increase experiment10 JTAG tap width to 4
2020-11-12 Luke Kenneth Casso... remove io_in/io_out from niolib experiments10
2020-11-04 Luke Kenneth Casso... minor reformat of spec, whitespace
2020-11-02 Jean-Paul ChaputCompleted experiment10, adder with JTAG (dual clocks...
2020-10-25 Jean-Paul ChaputAdded one-clock generated add.vst.
2020-10-25 Jean-Paul ChaputExperiment10 switched to the new chip2core module.
2020-10-25 Luke Kenneth Casso... update non_generated add.il for convenience
2020-10-24 Luke Kenneth Casso... add feedback shift register back in
2020-10-22 Luke Kenneth Casso... add non-generated add.il
2020-10-22 Luke Kenneth Casso... add jtag IO to experiment10
2020-10-22 Luke Kenneth Casso... add JTAG test
2020-10-22 Luke Kenneth Casso... add experiments10, to add C4M JTAG