argh, found the blackbox problem: yosys is "doing the right thing" and
[soclayout.git] / experiments12 /
2021-03-14 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-14 Jean-Paul ChaputAdjusted doDesign.py scripts to use Chip.doChipFloorplan().
2021-03-02 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-02 Jean-Paul ChaputFirst working power plane in experiment12.
2021-02-17 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-02-17 Jean-Paul ChaputFirst working integration of a SRAM block.
2021-02-02 Luke Kenneth Casso... whitespace
2021-02-02 Luke Kenneth Casso... whitespace
2021-02-01 Jean-Paul ChaputNetlist integration of the SRAM OK. Layout in progress.
2021-01-28 Jean-Paul ChaputWorking bench design with SRAM in top block.
2021-01-27 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2020-12-22 Luke Kenneth Casso... add SPBlock_512W64B8W to memory.py
2020-12-22 Luke Kenneth Casso... rename to memory from add
2020-12-22 Luke Kenneth Casso... add copy of experiments4 to create memory example