argh, found the blackbox problem: yosys is "doing the right thing" and
[soclayout.git] / experiments2 /
2020-02-24 Luke Kenneth Casso... whoops yes use clocktree
2020-02-24 Luke Kenneth Casso... add missing mksym.sh
2020-02-24 Luke Kenneth Casso... continue experimentation
2020-02-23 Luke Kenneth Casso... add sm3 to nets
2020-02-22 Luke Kenneth Casso... correct nets for experiment2
2020-02-22 Luke Kenneth Casso... track down module in which vdd / vss error exists ...
2020-02-22 Luke Kenneth Casso... remove working code, shrink "fail" case
2020-02-22 Luke Kenneth Casso... add test_partsig.py directly to experiment2
2020-02-22 Luke Kenneth Casso... move part_sig_add to its own directory