argh, found the blackbox problem: yosys is "doing the right thing" and
[soclayout.git] / experiments9 /
13 hours ago Luke Kenneth Casso... argh, found the blackbox problem: yosys is "doing the... master
14 hours ago Luke Kenneth Casso... try renaming spblock without the underscore
14 hours ago Luke Kenneth Casso... try changing layout of blackbox spblock_512w64b8w
15 hours ago Luke Kenneth Casso... experimenting with blackboxes
15 hours ago Luke Kenneth Casso... rename spblock_512w64b8w, and vco_test_ana for pll
16 hours ago Luke Kenneth Casso... rename blackboxes to lowercase, spblock_512w64b8w, pll
16 hours ago Luke Kenneth Casso... update ls180 sram4k
22 hours ago Luke Kenneth Casso... add yosys BLACKBOX SPBlock_512W64B8W - still blif2vst...
23 hours ago Luke Kenneth Casso... must use VST_FLAGS uniquify uppercase
23 hours ago Luke Kenneth Casso... sort out adding SPBlock_512 SRAM verilog to ls180
25 hours ago Luke Kenneth Casso... update tsmc_018 4k build script
25 hours ago Luke Kenneth Casso... use correct arguments to litex build to create 4k srams...
26 hours ago Luke Kenneth Casso... rename ls180sram4k to ls180
26 hours ago Luke Kenneth Casso... add full core variant including 4k sram of ls180
26 hours ago Luke Kenneth Casso... update libresoc.v, c4m-jtag fsm was renamed
26 hours ago Luke Kenneth Casso... update libresoc.v, c4m-jtag fsm was renamed
6 days ago Luke Kenneth Casso... update PLL signal output names
7 days ago Staf VerhaegendoDesign.py: Disable SRAM placement
7 days ago Staf VerhaegenReduce core size.
7 days ago Luke Kenneth Casso... another attempt to get 100% completed route
7 days ago Luke Kenneth Casso... good grief, increasing ls180 core size to 70,000, 100...
7 days ago Luke Kenneth Casso... increase core size to see if global routing can be...
7 days ago Luke Kenneth Casso... whitespace cleanup
7 days ago Luke Kenneth Casso... use auto-generated pinmux ioPadsSpecs
7 days ago Luke Kenneth Casso... use verilog version of ls180 in FreePDK_c4m45
7 days ago Luke Kenneth Casso... crank up the numbers (again)
7 days ago Staf VerhaegenWip of P&R of ls180 with C4M FreePDK45.
7 days ago Staf Verhaegenexperiments9: Ignore pinmux generated files.
7 days ago Staf Verhaegenmksym.sh: Check exitence of alliance-check-toolkit
8 days ago Luke Kenneth Casso... crank up the numbers to see if routing completion can...
8 days ago Luke Kenneth Casso... increase katana tracks reserved
8 days ago Luke Kenneth Casso... use verilog for ls180 instead of ilang
9 days ago Luke Kenneth Casso... make VST names unique, for GHDL to cope
9 days ago Luke Kenneth Casso... whitespace
9 days ago Luke Kenneth Casso... whitespace cleanup
10 days ago Luke Kenneth Casso... rename design of experiments10 to match ls180 chip...
2021-04-01 Luke Kenneth Casso... update / refresh full core DFF
2021-04-01 Luke Kenneth Casso... update / refresh full core DFF
2021-03-30 Luke Kenneth Casso... update 4k SRAM ls180.il
2021-03-30 Luke Kenneth Casso... add yosys version number
2021-03-29 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-29 Jean-Paul ChaputAdd a placeholder for the PLL in the doDesign.py for...
2021-03-29 Luke Kenneth Casso... Revert "enable high fanout in ls180 experiment9 doDesig...
2021-03-29 Luke Kenneth Casso... enable high fanout in ls180 experiment9 doDesign.py
2021-03-29 Luke Kenneth Casso... aaagh found bug in litex setup, 64 bit WB bus was truncated
2021-03-28 Luke Kenneth Casso... reduce SPR regfile size considerably
2021-03-28 Luke Kenneth Casso... reduce INT and FAST regfile sizes by sharing ports
2021-03-27 Luke Kenneth Casso... add missing floorplan function call
2021-03-27 Luke Kenneth Casso... hooray, corrected pinouts
2021-03-27 Luke Kenneth Casso... really weird error "unsupported direction for eint...
2021-03-23 Jean-Paul ChaputUodated doDesign for the latest ls180 (sram variant).
2021-03-22 Luke Kenneth Casso... increase DFF RAM size slightly
2021-03-22 Luke Kenneth Casso... add very small DFF srams variant
2021-03-22 Luke Kenneth Casso... create small dff with 4x 4k SRAMs
2021-03-22 Luke Kenneth Casso... ls180.il update
2021-03-22 Luke Kenneth Casso... argh pinmux generating bi-directional SDR DM when it...
2021-03-18 Luke Kenneth Casso... update ls180.il
2021-03-16 Luke Kenneth Casso... update ls180.il 4ksram with correct sdram connections
2021-03-16 Jean-Paul ChaputAdd experiment9/symbolic to test the multiple drivers...
2021-03-14 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-14 Jean-Paul ChaputAdjusted doDesign.py scripts to use Chip.doChipFloorplan().
2021-03-11 Luke Kenneth Casso... try alternative pad/core connection
2021-03-09 Jean-Paul ChaputForgot the Makefile, stupid!
2021-03-09 Jean-Paul ChaputFirst working version of the Flexlib + P&R flow for...
2021-03-06 Luke Kenneth Casso... add blackbox SPBlock 4k SRAM module
2021-03-05 Luke Kenneth Casso... remove sram 4k wb bte/cti
2021-03-05 Luke Kenneth Casso... litex expects wishbone "err" signals, added to sram 4k
2021-03-05 Luke Kenneth Casso... rename sram_4k wishbone interface to actually like...
2021-03-05 Jean-Paul ChaputAdded support files for ls180+SRAM on TSMC 180nm.
2021-03-03 Luke Kenneth Casso... add blackbox attribute manually to SPBlock_512W64B8W
2021-03-02 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-02-20 Luke Kenneth Casso... add 4k sram build
2021-02-20 Luke Kenneth Casso... increase core size to 50000 (DFF SRAMs)
2021-02-20 Luke Kenneth Casso... expand core size to 28000
2021-01-27 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-01-27 Jean-Paul ChaputPinmux loading is now integrated in Coriolis.
2020-12-04 Luke Kenneth Casso... increase core size (again) to cope with DFFs currently...
2020-12-04 Luke Kenneth Casso... Revert "very weird bug where CoreToChip.buildChip canno...
2020-12-03 Luke Kenneth Casso... very weird bug where CoreToChip.buildChip cannot find...
2020-12-03 Luke Kenneth Casso... increase size to 45,000 to cope with 3x extra SRAMs
2020-12-03 Luke Kenneth Casso... experiment adding 3x extra SRAMs back in but still...
2020-12-03 Luke Kenneth Casso... wtf does 32/64 bit bus have to do with gpio_o(8) disapp...
2020-12-03 Luke Kenneth Casso... reduce mem width due to yosys bugs. sigh
2020-12-03 Luke Kenneth Casso... added 3 more 4k SRAMs
2020-12-02 Luke Kenneth Casso... increase size to 40,000
2020-12-02 Luke Kenneth Casso... begin random search for appropriate core size. start...
2020-12-02 Luke Kenneth Casso... add full core back in
2020-11-27 Luke Kenneth Casso... add comment do not use build.sh
2020-11-14 Luke Kenneth Casso... update ls180 litex interfaces
2020-11-14 Luke Kenneth Casso... get rid of ibus/dbus/xics advanced wishbone tags
2020-11-14 Luke Kenneth Casso... update litex direction of iopads in ls180
2020-11-13 Luke Kenneth Casso... corona-core gap too small
2020-11-13 Luke Kenneth Casso... increase core size yet again, shrink gap
2020-11-13 Luke Kenneth Casso... increase core size, reduce corona gap again
2020-11-13 Luke Kenneth Casso... reduce nc ls180 pins to match
2020-11-13 Luke Kenneth Casso... increase chip size by 100, make chipSize closer to...
2020-11-13 Luke Kenneth Casso... fix clk_sel width (2 not 3)
2020-11-13 Luke Kenneth Casso... trying to get yosys to stop destroying pll_lck_o signal
2020-11-13 Luke Kenneth Casso... trying to get yosys to stop destroying pll_lck_o signal
2020-11-13 Luke Kenneth Casso... update full core ls180 (actually with litex peripherals...
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