soclayout.git
99 min agolitex expects wishbone "err" signals, added to sram 4k master
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 21:09:25 +0000 (21:09 +0000)]
litex expects wishbone "err" signals, added to sram 4k

3 hours agorename sram_4k wishbone interface to actually like include "wishbone"?
Luke Kenneth Casson Leighton [Fri, 5 Mar 2021 19:19:18 +0000 (19:19 +0000)]
rename sram_4k wishbone interface to actually like include "wishbone"?

12 hours agoAdded support files for ls180+SRAM on TSMC 180nm.
Jean-Paul Chaput [Fri, 5 Mar 2021 10:14:02 +0000 (11:14 +0100)]
Added support files for ls180+SRAM on TSMC 180nm.

2 days agoadd blackbox attribute manually to SPBlock_512W64B8W
Luke Kenneth Casson Leighton [Wed, 3 Mar 2021 22:03:40 +0000 (22:03 +0000)]
add blackbox attribute manually to SPBlock_512W64B8W

3 days agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Tue, 2 Mar 2021 12:02:14 +0000 (13:02 +0100)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

3 days agoFirst working power plane in experiment12.
Jean-Paul Chaput [Tue, 2 Mar 2021 11:23:36 +0000 (12:23 +0100)]
First working power plane in experiment12.

13 days agoadd 4k sram build
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 15:25:29 +0000 (15:25 +0000)]
add 4k sram build

13 days agoincrease core size to 50000 (DFF SRAMs)
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 15:24:02 +0000 (15:24 +0000)]
increase core size to 50000 (DFF SRAMs)

13 days agoexpand core size to 28000
Luke Kenneth Casson Leighton [Sat, 20 Feb 2021 12:37:54 +0000 (12:37 +0000)]
expand core size to 28000

2 weeks agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Wed, 17 Feb 2021 23:12:50 +0000 (00:12 +0100)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

2 weeks agoFirst working integration of a SRAM block.
Jean-Paul Chaput [Wed, 17 Feb 2021 23:10:43 +0000 (00:10 +0100)]
First working integration of a SRAM block.

The placement itself is completely goofy in order to stress the P&R system
to flush out bugs.

4 weeks agowhitespace
Luke Kenneth Casson Leighton [Tue, 2 Feb 2021 17:53:12 +0000 (17:53 +0000)]
whitespace

4 weeks agowhitespace
Luke Kenneth Casson Leighton [Tue, 2 Feb 2021 17:47:03 +0000 (17:47 +0000)]
whitespace

4 weeks agoNetlist integration of the SRAM OK. Layout in progress.
Jean-Paul Chaput [Mon, 1 Feb 2021 16:04:38 +0000 (17:04 +0100)]
Netlist integration of the SRAM OK. Layout in progress.

5 weeks agoWorking bench design with SRAM in top block.
Jean-Paul Chaput [Thu, 28 Jan 2021 14:02:22 +0000 (15:02 +0100)]
Working bench design with SRAM in top block.

5 weeks agoMerge branch 'master' of ssh://libre-riscv.org:922/soclayout
Jean-Paul Chaput [Wed, 27 Jan 2021 13:04:54 +0000 (14:04 +0100)]
Merge branch 'master' of ssh://libre-riscv.org:922/soclayout

Conflicts:
experiments9/doDesign.py

5 weeks agoPinmux loading is now integrated in Coriolis.
Jean-Paul Chaput [Wed, 27 Jan 2021 13:02:55 +0000 (14:02 +0100)]
Pinmux loading is now integrated in Coriolis.

7 weeks agoadd new Memory experiments13 ls180-24jan2020
Luke Kenneth Casson Leighton [Fri, 15 Jan 2021 13:35:45 +0000 (13:35 +0000)]
add new Memory experiments13

2 months agoadd SPBlock_512W64B8W to memory.py
Luke Kenneth Casson Leighton [Tue, 22 Dec 2020 15:02:32 +0000 (15:02 +0000)]
add SPBlock_512W64B8W to memory.py

2 months agorename to memory from add
Luke Kenneth Casson Leighton [Tue, 22 Dec 2020 14:54:36 +0000 (14:54 +0000)]
rename to memory from add

2 months agoadd copy of experiments4 to create memory example
Luke Kenneth Casson Leighton [Tue, 22 Dec 2020 14:52:01 +0000 (14:52 +0000)]
add copy of experiments4 to create memory example

2 months agoincrease core size (again) to cope with DFFs currently being made
Luke Kenneth Casson Leighton [Fri, 4 Dec 2020 22:30:16 +0000 (22:30 +0000)]
increase core size (again) to cope with DFFs currently being made
instead of SRAM

2 months agoRevert "very weird bug where CoreToChip.buildChip cannot find gpio_o(8)"
Luke Kenneth Casson Leighton [Fri, 4 Dec 2020 22:29:28 +0000 (22:29 +0000)]
Revert "very weird bug where CoreToChip.buildChip cannot find gpio_o(8)"

This reverts commit a4ac6b9543939ffea583be44cfba1141bdaeb7e6.

3 months agovery weird bug where CoreToChip.buildChip cannot find gpio_o(8)
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 18:30:12 +0000 (18:30 +0000)]
very weird bug where CoreToChip.buildChip cannot find gpio_o(8)

3 months agoincrease size to 45,000 to cope with 3x extra SRAMs
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 17:12:05 +0000 (17:12 +0000)]
increase size to 45,000 to cope with 3x extra SRAMs

3 months agoexperiment adding 3x extra SRAMs back in but still @ 32-bit WB
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 16:51:30 +0000 (16:51 +0000)]
experiment adding 3x extra SRAMs back in but still @ 32-bit WB

3 months agowtf does 32/64 bit bus have to do with gpio_o(8) disappearing??
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 16:27:01 +0000 (16:27 +0000)]
wtf does 32/64 bit bus have to do with gpio_o(8) disappearing??

3 months agoreduce mem width due to yosys bugs. sigh
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 16:18:19 +0000 (16:18 +0000)]
reduce mem width due to yosys bugs.  sigh

3 months agoadded 3 more 4k SRAMs
Luke Kenneth Casson Leighton [Thu, 3 Dec 2020 15:36:00 +0000 (15:36 +0000)]
added 3 more 4k SRAMs

3 months agoincrease size to 40,000
Luke Kenneth Casson Leighton [Wed, 2 Dec 2020 23:44:51 +0000 (23:44 +0000)]
increase size to 40,000

3 months agobegin random search for appropriate core size. start at 36000
Luke Kenneth Casson Leighton [Wed, 2 Dec 2020 23:36:41 +0000 (23:36 +0000)]
begin random search for appropriate core size.  start at 36000

3 months agoadd full core back in
Luke Kenneth Casson Leighton [Wed, 2 Dec 2020 23:34:30 +0000 (23:34 +0000)]
add full core back in

3 months agoupdate submodule for ls180 pinmux, iopad vss/vdd inversion corrected partial-core-ls180-gdsii
Luke Kenneth Casson Leighton [Mon, 30 Nov 2020 15:04:46 +0000 (15:04 +0000)]
update submodule for ls180 pinmux, iopad vss/vdd inversion corrected

3 months agoAdded experiments11, base for full chip with FlexLib & LibreSOCIO.
Jean-Paul Chaput [Mon, 30 Nov 2020 11:13:07 +0000 (12:13 +0100)]
Added experiments11, base for full chip with FlexLib & LibreSOCIO.

3 months agoadd comment do not use build.sh
Luke Kenneth Casson Leighton [Fri, 27 Nov 2020 17:50:53 +0000 (17:50 +0000)]
add comment do not use build.sh

3 months agoupdate ls180 litex interfaces
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 18:42:50 +0000 (18:42 +0000)]
update ls180 litex interfaces

3 months agoget rid of ibus/dbus/xics advanced wishbone tags
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 16:07:14 +0000 (16:07 +0000)]
get rid of ibus/dbus/xics advanced wishbone tags

3 months agoupdate litex direction of iopads in ls180
Luke Kenneth Casson Leighton [Sat, 14 Nov 2020 14:28:28 +0000 (14:28 +0000)]
update litex direction of iopads in ls180

3 months agocorona-core gap too small
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 20:18:17 +0000 (20:18 +0000)]
corona-core gap too small

3 months agoincrease core size yet again, shrink gap
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 18:39:44 +0000 (18:39 +0000)]
increase core size yet again, shrink gap

3 months agoincrease core size, reduce corona gap again
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 18:25:07 +0000 (18:25 +0000)]
increase core size, reduce corona gap again

3 months agoreduce nc ls180 pins to match
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 18:04:41 +0000 (18:04 +0000)]
reduce nc ls180 pins to match

3 months agoincrease chip size by 100, make chipSize closer to ring
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 18:02:05 +0000 (18:02 +0000)]
increase chip size by 100, make chipSize closer to ring

3 months agofix clk_sel width (2 not 3)
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 17:48:28 +0000 (17:48 +0000)]
fix clk_sel width (2 not 3)

3 months agotrying to get yosys to stop destroying pll_lck_o signal
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 17:43:51 +0000 (17:43 +0000)]
trying to get yosys to stop destroying pll_lck_o signal

3 months agotrying to get yosys to stop destroying pll_lck_o signal
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 17:41:38 +0000 (17:41 +0000)]
trying to get yosys to stop destroying pll_lck_o signal

3 months agoupdate full core ls180 (actually with litex peripherals but not core)
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 16:11:20 +0000 (16:11 +0000)]
update full core ls180 (actually with litex peripherals but not core)

3 months agotest of litex peripherals back in (not full core)
Luke Kenneth Casson Leighton [Fri, 13 Nov 2020 16:08:28 +0000 (16:08 +0000)]
test of litex peripherals back in (not full core)

3 months agoget core size big enough to fit pads along width
Luke Kenneth Casson Leighton [Thu, 12 Nov 2020 23:23:02 +0000 (23:23 +0000)]
get core size big enough to fit pads along width

3 months agoremove niolib io_in/out signal, no longer needed
Luke Kenneth Casson Leighton [Thu, 12 Nov 2020 21:54:10 +0000 (21:54 +0000)]
remove niolib io_in/out signal, no longer needed

3 months agoremove io_in/io_out from niolib experiments10
Luke Kenneth Casson Leighton [Thu, 12 Nov 2020 21:50:31 +0000 (21:50 +0000)]
remove io_in/io_out from niolib experiments10

3 months agosubmodule update
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 14:46:50 +0000 (14:46 +0000)]
submodule update

3 months agoadjust chip/core size to try to fit ls180 core/pads
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 14:40:08 +0000 (14:40 +0000)]
adjust chip/core size to try to fit ls180 core/pads

3 months agoadd power/ground pads
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 14:26:23 +0000 (14:26 +0000)]
add power/ground pads

3 months agoupdate CLKSEL / PLLOCK pins for ls180
Luke Kenneth Casson Leighton [Wed, 11 Nov 2020 13:58:14 +0000 (13:58 +0000)]
update CLKSEL / PLLOCK pins for ls180

3 months agoadd code comments for ioring-to-niolib conversion of JSON pinspec files
Luke Kenneth Casson Leighton [Mon, 9 Nov 2020 12:00:04 +0000 (12:00 +0000)]
add code comments for ioring-to-niolib conversion of JSON pinspec files

3 months agostart conversion of ls180 to new niolib
Luke Kenneth Casson Leighton [Sun, 8 Nov 2020 13:33:39 +0000 (13:33 +0000)]
start conversion of ls180 to new niolib

3 months agoadd io_in/io_out zero/one to help transition to new niolib ioring
Luke Kenneth Casson Leighton [Sat, 7 Nov 2020 12:07:33 +0000 (12:07 +0000)]
add io_in/io_out zero/one to help transition to new niolib ioring

3 months agomessing about to get non_generated ls180.vst running again
Luke Kenneth Casson Leighton [Sat, 7 Nov 2020 11:47:10 +0000 (11:47 +0000)]
messing about to get non_generated ls180.vst running again

3 months agoupdate full ls180 core
Luke Kenneth Casson Leighton [Sat, 7 Nov 2020 11:39:24 +0000 (11:39 +0000)]
update full ls180 core

3 months agoupdate to "full" core
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 12:12:52 +0000 (12:12 +0000)]
update to "full" core

3 months agoadd build scripts for ls180
Luke Kenneth Casson Leighton [Thu, 5 Nov 2020 12:11:43 +0000 (12:11 +0000)]
add build scripts for ls180

3 months agominor reformat of spec, whitespace
Luke Kenneth Casson Leighton [Wed, 4 Nov 2020 19:25:01 +0000 (19:25 +0000)]
minor reformat of spec, whitespace

4 months agoadd cmos45 to mksyms.sh
Luke Kenneth Casson Leighton [Mon, 2 Nov 2020 17:25:34 +0000 (17:25 +0000)]
add cmos45 to mksyms.sh

4 months agoCompleted experiment10, adder with JTAG (dual clocks) and GPIO pads.
Jean-Paul Chaput [Mon, 2 Nov 2020 17:06:39 +0000 (18:06 +0100)]
Completed experiment10, adder with JTAG (dual clocks) and GPIO pads.

4 months agoAdded one-clock generated add.vst.
Jean-Paul Chaput [Sun, 25 Oct 2020 20:40:22 +0000 (21:40 +0100)]
Added one-clock generated add.vst.

4 months agoExperiment10 switched to the new chip2core module.
Jean-Paul Chaput [Sun, 25 Oct 2020 20:39:29 +0000 (21:39 +0100)]
Experiment10 switched to the new chip2core module.

4 months agoupdate non_generated add.il for convenience
Luke Kenneth Casson Leighton [Sun, 25 Oct 2020 15:50:42 +0000 (15:50 +0000)]
update non_generated add.il for convenience

4 months agoadd feedback shift register back in
Luke Kenneth Casson Leighton [Sat, 24 Oct 2020 18:41:21 +0000 (18:41 +0000)]
add feedback shift register back in

4 months agoadd non-generated add.il
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 18:05:54 +0000 (18:05 +0000)]
add non-generated add.il

4 months agoadd jtag IO to experiment10
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 18:03:12 +0000 (18:03 +0000)]
add jtag IO to experiment10

4 months agoadd JTAG test
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 17:19:18 +0000 (17:19 +0000)]
add JTAG test

4 months agoadd experiments10, to add C4M JTAG
Luke Kenneth Casson Leighton [Thu, 22 Oct 2020 16:55:05 +0000 (16:55 +0000)]
add experiments10, to add C4M JTAG

5 months agomatch up power/gnd numbers with pinmux
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 13:19:16 +0000 (13:19 +0000)]
match up power/gnd numbers with pinmux

5 months agosubmodule update
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 13:10:15 +0000 (13:10 +0000)]
submodule update

5 months agouse new extpower/intpower and pads.useCoreSize params
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 13:10:06 +0000 (13:10 +0000)]
use new extpower/intpower and pads.useCoreSize params

5 months agoreduce number of not-connected
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 13:09:46 +0000 (13:09 +0000)]
reduce number of not-connected

5 months agoupdate experiment4 to use pads.useCoreSize
Luke Kenneth Casson Leighton [Sun, 4 Oct 2020 13:08:43 +0000 (13:08 +0000)]
update experiment4 to use pads.useCoreSize

5 months agosubmodule update
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 11:33:50 +0000 (11:33 +0000)]
submodule update

5 months agoupdate build.sh
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 10:54:21 +0000 (10:54 +0000)]
update build.sh

5 months agoadd really cut down version of ls180.vst
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 10:03:18 +0000 (10:03 +0000)]
add really cut down version of ls180.vst

5 months agoreally really cut down core
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 10:02:53 +0000 (10:02 +0000)]
really really cut down core

5 months agosubmodule update
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 09:30:34 +0000 (09:30 +0000)]
submodule update

5 months agomove ioring to pinmux
Luke Kenneth Casson Leighton [Fri, 2 Oct 2020 09:30:20 +0000 (09:30 +0000)]
move ioring to pinmux

5 months agoupdate to new ls180.il (no core yet) with PLL I/O and I2C
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 15:12:44 +0000 (15:12 +0000)]
update to new ls180.il (no core yet) with PLL I/O and I2C

5 months agosort sys_* pad names
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 15:11:40 +0000 (15:11 +0000)]
sort sys_* pad names

5 months agoadd I2C, allow sys_clk_i and sys_pll_48_o out
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 14:56:37 +0000 (14:56 +0000)]
add I2C, allow sys_clk_i and sys_pll_48_o out

5 months agoincrease core.size to 27500x27500
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 20:45:21 +0000 (20:45 +0000)]
increase core.size to 27500x27500

5 months agoadd full core ilang file
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 17:15:15 +0000 (17:15 +0000)]
add full core ilang file

5 months agocommented-out core.size and chip.size which would allow the
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 17:14:09 +0000 (17:14 +0000)]
commented-out core.size and chip.size which would allow the
full core to fit

5 months agouse publicly-accessible submodule
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 16:49:01 +0000 (16:49 +0000)]
use publicly-accessible submodule

5 months agoadd build script for convenience
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 15:36:29 +0000 (15:36 +0000)]
add build script for convenience

5 months agoURL of submodule pinmux needs to use ssh/port 922.
Jean-Paul Chaput [Wed, 30 Sep 2020 14:33:11 +0000 (16:33 +0200)]
URL of submodule pinmux needs to use ssh/port 922.

5 months agoadd cki and ck to clock settings
Luke Kenneth Casson Leighton [Tue, 29 Sep 2020 09:32:53 +0000 (09:32 +0000)]
add cki and ck to clock settings

5 months agoupdated ls180 (no core, testing)
Luke Kenneth Casson Leighton [Tue, 29 Sep 2020 09:32:13 +0000 (09:32 +0000)]
updated ls180 (no core, testing)

5 months agoadd sdram_dm_1 back in
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 15:59:52 +0000 (15:59 +0000)]
add sdram_dm_1 back in

5 months agoiopad pads.instances mapping
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 13:45:36 +0000 (13:45 +0000)]
iopad pads.instances mapping

5 months agoworked out how to do pad instances in experiment4
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 13:09:38 +0000 (13:09 +0000)]
worked out how to do pad instances in experiment4

5 months agosubmodule update
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:35:18 +0000 (11:35 +0000)]
submodule update

5 months agoremove unused cells for now
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:35:10 +0000 (11:35 +0000)]
remove unused cells for now