From 4db0152749234d6975b2d1c18bf21aefacaf833d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 9 Jun 2021 15:41:47 +0000 Subject: [PATCH] pllclk_o is renamed to pllclk_clk --- .../full_core_4_4ksram_litex_ls180_recon.v | 44 +++++++++---------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v index 8415590..3988af2 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v @@ -1,5 +1,5 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-06-09 16:10:24 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-06-09 16:40:53 //-------------------------------------------------------------------------------- module ls180( input wire uart_tx, @@ -8,16 +8,6 @@ module ls180( input wire i2c_sda_i, output wire i2c_sda_o, output wire i2c_sda_oe, - output wire spimaster_clk, - output wire spimaster_mosi, - output wire spimaster_cs_n, - input wire spimaster_miso, - input wire [15:0] gpio_i, - output wire [15:0] gpio_o, - output wire [15:0] gpio_oe, - input wire eint_0, - input wire eint_1, - input wire eint_2, output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, @@ -30,6 +20,16 @@ module ls180( output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, + output wire spimaster_clk, + output wire spimaster_mosi, + output wire spimaster_cs_n, + input wire spimaster_miso, + input wire [15:0] gpio_i, + output wire [15:0] gpio_o, + output wire [15:0] gpio_oe, + input wire eint_0, + input wire eint_1, + input wire eint_2, input wire sys_rst, input wire [1:0] sys_clksel_i, output wire sys_pll_testout_o, @@ -166,16 +166,6 @@ wire main_libresocsim_libresoc_constraintmanager_i2c_scl; wire main_libresocsim_libresoc_constraintmanager_i2c_sda_i; wire main_libresocsim_libresoc_constraintmanager_i2c_sda_o; wire main_libresocsim_libresoc_constraintmanager_i2c_sda_oe; -reg main_libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; -reg main_libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; -reg main_libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; -wire main_libresocsim_libresoc_constraintmanager_spimaster_miso; -wire [15:0] main_libresocsim_libresoc_constraintmanager_gpio_i; -reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; -reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; -wire main_libresocsim_libresoc_constraintmanager_eint_0; -wire main_libresocsim_libresoc_constraintmanager_eint_1; -wire main_libresocsim_libresoc_constraintmanager_eint_2; reg [12:0] main_libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] main_libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] main_libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; @@ -188,6 +178,16 @@ reg main_libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] main_libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] main_libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg main_libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; +reg main_libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; +reg main_libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; +reg main_libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; +wire main_libresocsim_libresoc_constraintmanager_spimaster_miso; +wire [15:0] main_libresocsim_libresoc_constraintmanager_gpio_i; +reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; +reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; +wire main_libresocsim_libresoc_constraintmanager_eint_0; +wire main_libresocsim_libresoc_constraintmanager_eint_1; +wire main_libresocsim_libresoc_constraintmanager_eint_2; reg [29:0] main_libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] main_libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] main_libresocsim_interface0_converted_interface_dat_r; @@ -6092,7 +6092,7 @@ test_issuer test_issuer( .pc_o(main_libresocsim_libresoc3), .pll_test_o(main_libresocsim_libresoc_pll_test_o), .pll_vco_o(main_libresocsim_libresoc_pll_vco_o), - .pllclk_o(pll_clk), + .pllclk_clk(pll_clk), .sdr_a_0__pad__o(sdram_a[0]), .sdr_a_10__pad__o(sdram_a[10]), .sdr_a_11__pad__o(sdram_a[11]), -- 2.30.2