From 6ac9ce3702f51288e5f558c7bfe557a4cd276946 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 20 Feb 2020 00:21:03 +0000 Subject: [PATCH] remove clock --- examples/alu_hier.py | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/examples/alu_hier.py b/examples/alu_hier.py index 52ca05a..b42fb1d 100644 --- a/examples/alu_hier.py +++ b/examples/alu_hier.py @@ -32,8 +32,6 @@ class ALU(Elaboratable): self.a = Signal(width) self.b = Signal(width) self.o = Signal(width) - self.m_clock = Signal(reset_less=True) - self.p_reset = Signal(reset_less=True) self.add = Adder(width) self.sub = Subtractor(width) @@ -41,8 +39,8 @@ class ALU(Elaboratable): def elaborate(self, platform): m = Module() - m.domains.sync = ClockDomain() - m.d.comb += ClockSignal().eq(self.m_clock) + #m.domains.sync = ClockDomain() + #m.d.comb += ClockSignal().eq(self.m_clock) m.submodules.add = self.add m.submodules.sub = self.sub @@ -66,5 +64,5 @@ def create_ilang(dut, ports, test_name): if __name__ == "__main__": alu = ALU(width=16) - create_ilang(alu, [alu.m_clock, alu.p_reset, + create_ilang(alu, [#alu.m_clock, alu.p_reset, alu.op, alu.a, alu.b, alu.o], "alu_hier") -- 2.30.2