examples/counter.sv

   1 module up_counter(input logic clk,
   2                   input logic reset,
   3                   output[3:0] counter
   4                   );
   5    reg [3:0] counter_up;
   6    // up counter
   7    always @(posedge clk or posedge reset)
   8      begin
   9         if(reset)
  10           counter_up <= 4'd0;
  11         else
  12           counter_up <= counter_up + 4'd1;
  13      end
  14    assign counter = counter_up;
  15 endmodule