self.outputfile = None
self.assign = []
self.ports = []
+ self.wires = []
def open(self):
if(self.outputfile is None):
self.ports += [port]
return port
+ def isPort(self, name):
+ for p in self.ports:
+ if(str(p.name) == str(name)):
+ return True
+ return False
+
def initFunc(self, ports, params):
params = [Leaf(token.LPAR, '('), Leaf(
token.NAME, "self")] + [Leaf(token.RPAR, ')')]
stmts.children.append(Leaf(token.STRING, "m = Module()"))
stmts.children.append(self.nl())
+ for w in self.wires:
+ wirename = w[0]
+ hasdims = (len(w) >= 4)
+ stmts.children.append(self.indent(2))
+ stmts.children.append(Leaf(token.STRING, wirename))
+ stmts.children.append(Leaf(token.STRING, " = Signal("))
+ if(hasdims):
+ stmts.children.append(Leaf(token.STRING, str(w[3])))
+ stmts.children.append(Leaf(token.STRING, ")"))
+ stmts.children.append(self.nl())
+
for a in self.assign:
stmts.children.append(self.indent(2))
# m.d.sync += self.left.eq(right)
- stmts.children.append(Leaf(token.STRING, "m.d.comb += self."))
+ stmts.children.append(Leaf(token.STRING, "m.d.comb += "))
+ if(self.isPort(a.left)):
+ stmts.children.append(Leaf(token.STRING, "self."))
stmts.children.append(Leaf(token.STRING, a.left))
- stmts.children.append(Leaf(token.STRING, ".eq(self."))
+ stmts.children.append(Leaf(token.STRING, ".eq("))
+ if(self.isPort(a.right)):
+ stmts.children.append(Leaf(token.STRING, "self."))
stmts.children.append(Leaf(token.STRING, a.right))
stmts.children.append(Leaf(token.STRING, ")"))
stmts.children.append(self.nl())
self.printpy(str(clsdecl))
return clsdecl
+ def module_item_2(self, signaltype, dims, mlist):
+ if(signaltype == "wire"):
+ for m in mlist:
+ if(dims):
+ self.wires.append(m+dims)
+ else:
+ self.wires.append(m)
+
def appendComments(self, data):
self.open()
self.outputfile.write(data)