add port/net defs

[sv2nmigen.git] / parse_sv.py

diff --git a/parse_sv.py b/parse_sv.py
index b61df9ea51d41e06f73a82aeffa0583b2e569554..e039650ea3749ce04f2b4981251b4c19f8617604 100644 (file)
--- a/parse_sv.py
+++ b/parse_sv.py
@@ -57,9 +57,34 @@ precedence = [\
     ]
 
 
-IVL_VT_NO_TYPE = 0
-IVL_VT_BOOL = 1
-IVL_VT_LOGIC = 2
+IVL_VT_NO_TYPE = 'VT_NO_TYPE'
+IVL_VT_BOOL = 'VT_BOOL'
+IVL_VT_LOGIC = 'VT_LOGIC'
+
+NN_NONE = 'NONE'
+NN_IMPLICIT = 'IMPLICIT'
+NN_IMPLICIT_REG = 'IMPLICIT_REG'
+NN_INTEGER = 'INTEGER'
+NN_WIRE = 'WIRE'
+NN_TRI = 'TRI'
+NN_TRI1 = 'TRI1'
+NN_SUPPLY0 = 'SUPPLY0'
+NN_SUPPLY1 = 'SUPPLY1'
+NN_WAND = 'WAND'
+NN_TRIAND = 'TRIAND'
+NN_TRI0 = 'TRI0'
+NN_WOR = 'WOR'
+NN_TRIOR = 'TRIOR'
+NN_REG = 'REG'
+NN_UNRESOLVED_WIRE = 'UNRESOLVED_WIRE'
+
+NP_NOT_A_PORT = 'NOT_A_PORT'
+NP_PIMPLICIT = 'PIMPLICIT'
+NP_PINPUT = 'PINPUT'
+NP_POUTPUT = 'POUTPUT'
+NP_PINOUT = 'PINOUT'
+NP_PREF = 'PREF'
+
 
 # -------------- RULES ----------------
 ()