From c2475e188a965c7f34e28d3d022205f9a97ed215 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sun, 27 Oct 2019 16:02:15 +0100 Subject: [PATCH] comb assignment now working --- absyn.py | 76 +++++++++++++++++++++++++++--------------- examples/assignment.py | 4 +-- examples/assignment.sv | 4 +-- parse_sv.py | 12 ------- 4 files changed, 53 insertions(+), 43 deletions(-) diff --git a/absyn.py b/absyn.py index 12f1c0a..d522502 100644 --- a/absyn.py +++ b/absyn.py @@ -10,13 +10,40 @@ from nmigen import Signal, Module, Const, Cat, Elaboratable """ +def port_decl_do_not_use(comment, dt, name): + if dt is None or dt.dims is None: + width = '' # width: 1 + else: + width = dt.dims + # XXX TODO, better checking, should be using data structure... *sigh* + width = width[1:-1] # strip brackets + width = width.split(':') + assert width[0] == '0' + width = width[1] + return 'self.%s = Signal(%s) # %s' % (name, width, comment) + indent_debug = 0 +class PortDecl: + def __init__(self,comment,dt,name): + self.comment = comment + self.dt=dt + self.name=name + def initNode(self): + return port_decl_do_not_use(self.comment,self.dt,self.name) + +class Assignment: + def __init__(self,left,op,right): + self.left = left + self.op = op + self.right = right + class Absyn: def __init__(self): self.outputfile = open("output.py","w") self.outputfile.write(preamble) self.assign = [] + self.ports = [] def printpy(self,p): self.outputfile.write(str(p)+"\n") def assign(self,p): @@ -36,28 +63,9 @@ class Absyn: return Leaf(token.NEWLINE, '\n') def port_decl(self,comment, dt, name): - return None # TODO - - def initPorts(self,params,ports): - pass_stmt = Node(syms.pass_stmt ,[Leaf(token.NAME, "def __init__(self):#FIXME")]) - if params: - params = [Leaf(token.LPAR, '(')] + params + [Leaf(token.RPAR, ')')] - fn = [Leaf(token.NAME, 'def'), - Leaf(token.NAME, '__initXXX__', prefix=' '), - Node(syms.parameters, params), - Leaf(token.COLON, ':')] - fndef = Node(syms.funcdef, fn) - stmts = Node(syms.stmt, [fndef]) - else: - stmts = Node(syms.small_stmt, [pass_stmt, Leaf(token.NEWLINE, '\n')]) - stmts = Node(syms.stmt, [stmts]) - - for port in ports: - stmts.children.append(self.indent(2)) - stmts.children.append(port) - stmts.children.append(self.nl()) - - return stmts + port = PortDecl(comment,dt,name) + self.ports += [port] + return port def initFunc(self,ports,params): params = [Leaf(token.LPAR, '('),Leaf(token.NAME,"self")] + [Leaf(token.RPAR, ')')] @@ -72,7 +80,7 @@ class Absyn: stmts = Node(syms.stmt, [fndef]) for port in ports: stmts.children.append(self.indent(2)) - stmts.children.append(port) + stmts.children.append(port.initNode()) stmts.children.append(self.nl()) return stmts @@ -89,11 +97,23 @@ class Absyn: stmts.children.append(self.indent(2)) stmts.children.append(Leaf(token.STRING,"m = Module()")) stmts.children.append(self.nl()) - ## + + for a in self.assign: stmts.children.append(self.indent(2)) - stmts.children.append(Leaf(token.STRING,"#FIXME_ASSIGN"+str(list(a[8])))) + # m.d.sync += self.left.eq(right) + stmts.children.append(Leaf(token.STRING,"m.d.comb += self.")) + stmts.children.append(Leaf(token.STRING,a.left)) + stmts.children.append(Leaf(token.STRING,".eq(self.")) + stmts.children.append(Leaf(token.STRING,a.right)) + stmts.children.append(Leaf(token.STRING,")")) stmts.children.append(self.nl()) + + #for a in self.assign: + # + # + #ports = a[8] + # stmts.children.append(self.indent(2)) stmts.children.append(Leaf(token.STRING,"return m")) @@ -123,9 +143,11 @@ class Absyn: clsdecl = Node(syms.compound_stmt, [clsdecl]) self.printpy(str(clsdecl)) + print("=====================") + print(str(clsdecl)) return clsdecl # combinatorical assign def cont_assign_1(self,p): - #self.printpy("#ASSIGN"+str(list(p))) - self.assign += [p] + print("#ASSIGN:BROKEN"+str(list(p))) + self.assign += [Assignment(p[1],p[2],p[3])] diff --git a/examples/assignment.py b/examples/assignment.py index c338a6b..d70d850 100644 --- a/examples/assignment.py +++ b/examples/assignment.py @@ -4,13 +4,13 @@ from nmigen import Signal, Module, Const, Cat, Elaboratable -#ASSIGN[None, Leaf(1, 'o'), '=', Leaf(1, 'i')] class assignment(Elaboratable): def __init__(self): - self.i = Signal() # input self.o = Signal() # output + self.i = Signal() # input def elaborate(self, platform=None): m = Module() + m.d.comb += self.o.eq(self.i) return m diff --git a/examples/assignment.sv b/examples/assignment.sv index e3e326e..81831a2 100644 --- a/examples/assignment.sv +++ b/examples/assignment.sv @@ -1,6 +1,6 @@ module assignment( - input i, - output o + output o, + input i ); assign o = i; endmodule diff --git a/parse_sv.py b/parse_sv.py index bd760f5..fd25dbf 100644 --- a/parse_sv.py +++ b/parse_sv.py @@ -109,18 +109,6 @@ class DataType: self.typ = typ self.signed = signed -def port_decl_do_not_use(comment, dt, name): - if dt is None or dt.dims is None: - width = '' # width: 1 - else: - width = dt.dims - # XXX TODO, better checking, should be using data structure... *sigh* - width = width[1:-1] # strip brackets - width = width.split(':') - assert width[0] == '0' - width = width[1] - return 'self.%s = Signal(%s) # %s' % (name, width, comment) - # -------------- RULES ---------------- () def p_source_text_1(p): -- 2.30.2