3 traits::{ConvertFrom, ConvertTo, Float},
7 ops::{Add, AddAssign, Div, DivAssign, Mul, MulAssign, Neg, Rem, RemAssign, Sub, SubAssign},
10 #[cfg(feature = "f16")]
11 use half::f16 as F16Impl;
13 #[cfg(not(feature = "f16"))]
16 #[derive(Clone, Copy, PartialEq, PartialOrd)]
18 pub struct F16(F16Impl);
20 #[cfg(not(feature = "f16"))]
22 pub(crate) fn panic_f16_feature_disabled() -> ! {
23 panic!("f16 feature is not enabled")
26 #[cfg(feature = "f16")]
27 macro_rules! f16_impl {
28 ($v:expr, [$($vars:ident),*]) => {
33 #[cfg(not(feature = "f16"))]
34 macro_rules! f16_impl {
35 ($v:expr, [$($vars:ident),*]) => {
38 panic_f16_feature_disabled()
43 impl fmt::Display for F16 {
44 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
45 f16_impl!(self.0.fmt(f), [f])
49 impl fmt::Debug for F16 {
50 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
51 f16_impl!(self.0.fmt(f), [f])
55 impl Default for F16 {
56 fn default() -> Self {
57 f16_impl!(F16(F16Impl::default()), [])
61 impl From<F16Impl> for F16 {
62 fn from(v: F16Impl) -> Self {
67 impl From<F16> for F16Impl {
68 fn from(v: F16) -> Self {
73 macro_rules! impl_f16_from {
76 impl From<$ty> for F16 {
77 fn from(v: $ty) -> Self {
78 f16_impl!(F16(F16Impl::from(v)), [v])
82 impl ConvertFrom<$ty> for F16 {
83 fn cvt_from(v: $ty) -> F16 {
91 macro_rules! impl_from_f16 {
94 impl From<F16> for $ty {
95 fn from(v: F16) -> Self {
96 f16_impl!(v.0.into(), [v])
100 impl ConvertFrom<F16> for $ty {
101 fn cvt_from(v: F16) -> Self {
109 impl_f16_from![i8, u8,];
111 impl_from_f16![f32, f64,];
113 macro_rules! impl_int_to_f16 {
114 ($($int:ident),*) => {
116 impl ConvertFrom<$int> for F16 {
117 fn cvt_from(v: $int) -> Self {
118 // f32 has enough mantissa bits such that f16 overflows to
119 // infinity before f32 stops being able to properly
120 // represent integer values, making the below conversion correct.
121 F16::cvt_from(v as f32)
128 macro_rules! impl_f16_to_int {
129 ($($int:ident),*) => {
131 impl ConvertFrom<F16> for $int {
132 fn cvt_from(v: F16) -> Self {
140 impl_int_to_f16![i16, u16, i32, u32, i64, u64, i128, u128];
141 impl_f16_to_int![i8, u8, i16, u16, i32, u32, i64, u64, i128, u128];
143 impl ConvertFrom<f32> for F16 {
144 fn cvt_from(v: f32) -> Self {
145 f16_impl!(F16(F16Impl::from_f32(v)), [v])
149 impl ConvertFrom<f64> for F16 {
150 fn cvt_from(v: f64) -> Self {
151 f16_impl!(F16(F16Impl::from_f64(v)), [v])
158 fn neg(self) -> Self::Output {
159 f16_impl!(Self::from_bits(self.to_bits() ^ 0x8000), [])
163 macro_rules! impl_bin_op_using_f32 {
164 ($($op:ident, $op_fn:ident, $op_assign:ident, $op_assign_fn:ident;)*) => {
169 fn $op_fn(self, rhs: Self) -> Self::Output {
170 f32::from(self).$op_fn(f32::from(rhs)).to()
174 impl $op_assign for F16 {
175 fn $op_assign_fn(&mut self, rhs: Self) {
176 *self = (*self).$op_fn(rhs);
183 impl_bin_op_using_f32! {
184 Add, add, AddAssign, add_assign;
185 Sub, sub, SubAssign, sub_assign;
186 Mul, mul, MulAssign, mul_assign;
187 Div, div, DivAssign, div_assign;
188 Rem, rem, RemAssign, rem_assign;
192 pub fn from_bits(v: u16) -> Self {
193 #[cfg(feature = "f16")]
194 return F16(F16Impl::from_bits(v));
195 #[cfg(not(feature = "f16"))]
198 pub fn to_bits(self) -> u16 {
199 #[cfg(feature = "f16")]
200 return self.0.to_bits();
201 #[cfg(not(feature = "f16"))]
204 pub fn abs(self) -> Self {
205 f16_impl!(Self::from_bits(self.to_bits() & 0x7FFF), [])
207 pub fn trunc(self) -> Self {
208 #[cfg(feature = "std")]
209 return f32::from(self).trunc().to();
210 #[cfg(not(feature = "std"))]
213 pub fn ceil(self) -> Self {
214 #[cfg(feature = "std")]
215 return f32::from(self).ceil().to();
216 #[cfg(not(feature = "std"))]
219 pub fn floor(self) -> Self {
220 #[cfg(feature = "std")]
221 return f32::from(self).floor().to();
222 #[cfg(not(feature = "std"))]
225 pub fn round(self) -> Self {
226 #[cfg(feature = "std")]
227 return f32::from(self).round().to();
228 #[cfg(not(feature = "std"))]
231 #[cfg(feature = "fma")]
232 pub fn fma(self, a: Self, b: Self) -> Self {
233 (f64::from(self) * f64::from(a) + f64::from(b)).to()
236 pub fn is_nan(self) -> bool {
237 f16_impl!(self.0.is_nan(), [])
240 pub fn is_infinite(self) -> bool {
241 f16_impl!(self.0.is_infinite(), [])
244 pub fn is_finite(self) -> bool {
245 f16_impl!(self.0.is_finite(), [])
249 impl Float for Value<F16> {
250 type PrimFloat = F16;
251 type BitsType = Value<u16>;
252 type SignedBitsType = Value<i16>;
254 fn abs(self) -> Self {
258 fn trunc(self) -> Self {
259 Value(self.0.trunc())
262 fn ceil(self) -> Self {
266 fn floor(self) -> Self {
267 Value(self.0.floor())
270 fn round(self) -> Self {
271 Value(self.0.round())
274 #[cfg(feature = "fma")]
275 fn fma(self, a: Self, b: Self) -> Self {
276 Value(self.0.fma(a.0, b.0))
279 fn is_nan(self) -> Self::Bool {
280 Value(self.0.is_nan())
283 fn is_infinite(self) -> Self::Bool {
284 Value(self.0.is_infinite())
287 fn is_finite(self) -> Self::Bool {
288 Value(self.0.is_finite())
291 fn from_bits(v: Self::BitsType) -> Self {
292 Value(F16::from_bits(v.0))
295 fn to_bits(self) -> Self::BitsType {
296 Value(self.0.to_bits())
303 use core::cmp::Ordering;
307 not(feature = "f16"),
308 should_panic(expected = "f16 feature is not enabled")
311 assert_eq!(F16::from_bits(0x8000).abs().to_bits(), 0);
312 assert_eq!(F16::from_bits(0).abs().to_bits(), 0);
313 assert_eq!(F16::from_bits(0x8ABC).abs().to_bits(), 0xABC);
314 assert_eq!(F16::from_bits(0xFE00).abs().to_bits(), 0x7E00);
315 assert_eq!(F16::from_bits(0x7E00).abs().to_bits(), 0x7E00);
320 not(feature = "f16"),
321 should_panic(expected = "f16 feature is not enabled")
324 assert_eq!(F16::from_bits(0x8000).neg().to_bits(), 0);
325 assert_eq!(F16::from_bits(0).neg().to_bits(), 0x8000);
326 assert_eq!(F16::from_bits(0x8ABC).neg().to_bits(), 0xABC);
327 assert_eq!(F16::from_bits(0xFE00).neg().to_bits(), 0x7E00);
328 assert_eq!(F16::from_bits(0x7E00).neg().to_bits(), 0xFE00);
333 not(feature = "f16"),
334 should_panic(expected = "f16 feature is not enabled")
336 fn test_int_to_f16() {
337 assert_eq!(F16::to_bits(0u32.to()), 0);
338 for v in 1..0x20000u32 {
339 let leading_zeros = u32::leading_zeros(v);
340 let shifted_v = v << leading_zeros;
341 // round to nearest, ties to even
342 let round_up = match (shifted_v & 0x1FFFFF).cmp(&0x100000) {
343 Ordering::Less => false,
344 Ordering::Equal => (shifted_v & 0x200000) != 0,
345 Ordering::Greater => true,
347 let (rounded, carry) =
348 (shifted_v & !0x1FFFFF).overflowing_add(round_up.then(|| 0x200000).unwrap_or(0));
351 mantissa = (rounded >> 22) as u16 + 0x400;
353 mantissa = (rounded >> 21) as u16;
355 assert_eq!((mantissa & !0x3FF), 0x400);
356 let exponent = 31 - leading_zeros as u16 + 15 + carry as u16;
357 let expected = if exponent < 0x1F {
358 (mantissa & 0x3FF) + (exponent << 10)
362 let actual = F16::to_bits(v.to());
365 "actual = {:#X}, expected = {:#X}, v = {:#X}",