From: Jacob Lifshay Date: Tue, 4 May 2021 05:02:08 +0000 (-0700) Subject: start adding stdsimd support X-Git-Url: https://git.libre-soc.org/?p=vector-math.git;a=commitdiff_plain;h=d7ab57e9fd9e6682dd7e8c20772f22e7450eef1f;ds=sidebyside start adding stdsimd support --- diff --git a/Cargo.toml b/Cargo.toml index 3cf9665..5f82460 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -8,6 +8,7 @@ license = "MIT OR Apache-2.0" [dependencies] half = { version = "1.7.1", optional = true } typed-arena = { version = "2.0.1", optional = true } +core_simd = { version = "0.1.0", git = "https://github.com/rust-lang/stdsimd", optional = true } [features] default = ["f16", "fma"] @@ -15,3 +16,4 @@ f16 = ["half"] fma = ["std"] std = [] ir = ["std", "typed-arena"] +stdsimd = ["core_simd"] diff --git a/src/lib.rs b/src/lib.rs index 1b3add3..cecc2e4 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -10,4 +10,6 @@ pub mod ieee754; #[cfg(feature = "ir")] pub mod ir; pub mod scalar; +#[cfg(feature = "stdsimd")] +pub mod stdsimd; pub mod traits; diff --git a/src/stdsimd.rs b/src/stdsimd.rs new file mode 100644 index 0000000..4e76d8f --- /dev/null +++ b/src/stdsimd.rs @@ -0,0 +1,45 @@ +use crate::{f16::F16, traits::Context}; +use core::marker::PhantomData; +use core_simd::SimdF32; + +#[derive(Clone, Copy, PartialEq, Eq, Hash, Debug, Default)] +pub struct StdSimd(PhantomData<[(); LANES]>); + +#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, Debug, Default)] +pub struct Scalar(pub T, PhantomData<[(); LANES]>); + +impl From for Scalar { + fn from(v: T) -> Self { + Scalar(v, PhantomData) + } +} + +/* +TODO(programmerjake): finish after splitting Context::VecBool +impl Context for StdSimd { + type Bool = Scalar; + type U8 = Scalar; + type I8 = Scalar; + type U16 = Scalar; + type I16 = Scalar; + type F16 = Scalar; + type U32 = Scalar; + type I32 = Scalar; + type F32 = Scalar; + type U64 = Scalar; + type I64 = Scalar; + type F64 = Scalar; + type VecBool; + type VecU8; + type VecI8; + type VecU16; + type VecI16; + type VecF16; + type VecU32; + type VecI32; + type VecF32; + type VecU64; + type VecI64; + type VecF64; +} +*/