1 Spike RISC-V ISA Simulator
2 ============================
7 Spike, the RISC-V ISA Simulator, implements a functional model of one or more
10 Spike is named after the golden spike used to celebrate the completion of the
11 US transcontinental railway.
16 We assume that the RISCV environment variable is set to the RISC-V tools
17 install path, and that the riscv-fesvr package is installed there.
19 $ apt-get install device-tree-compiler
22 $ ../configure --prefix=$RISCV --with-fesvr=$RISCV
26 Compiling and Running a Simple C Program
27 -------------------------------------------
29 Install spike (see Build Steps), riscv-gnu-toolchain, and riscv-pk.
31 Write a short C program and name it hello.c. Then, compile it into a RISC-V
32 ELF binary named hello:
34 $ riscv64-unknown-elf-gcc -o hello hello.c
36 Now you can simulate the program atop the proxy kernel:
40 Simulating a New Instruction
41 ------------------------------------
43 Adding an instruction to the simulator requires two steps:
45 1. Describe the instruction's functional behavior in the file
46 riscv/insns/<new_instruction_name>.h. Examine other instructions
47 in that directory as a starting point.
49 2. Add the opcode and opcode mask to riscv/opcodes.h. Alternatively,
50 add it to the riscv-opcodes package, and it will do so for you:
53 $ vi opcodes // add a line for the new instruction
56 3. Rebuild the simulator.
58 Interactive Debug Mode
59 ---------------------------
61 To invoke interactive debug mode, launch spike with -d:
65 To see the contents of an integer register (0 is for core 0):
69 To see the contents of a floating point register:
77 depending upon whether you wish to print the register as single- or double-precision.
79 To see the contents of a memory location (physical address in hex):
83 To see the contents of memory with a virtual address (0 for core 0):
87 You can advance by one instruction by pressing <enter>. You can also
88 execute until a desired equality is reached:
90 : until pc 0 2020 (stop when pc=2020)
91 : until mem 2020 50a9907311096993 (stop when mem[2020]=50a9907311096993)
93 Alternatively, you can execute as long as an equality is true:
95 : while mem 2020 50a9907311096993
97 You can continue execution indefinitely by:
101 At any point during execution (even without -d), you can enter the
102 interactive debug mode with `<control>-<c>`.
104 To end the simulation from the debug prompt, press `<control>-<c>` or:
111 An alternative to interactive debug mode is to attach using gdb. Because spike
112 tries to be like real hardware, you also need OpenOCD to do that. OpenOCD
113 doesn't currently know about address translation, so it's not possible to
114 easily debug programs that are run under `pk`. We'll use the following test
118 char text[] = "Vafgehpgvba frgf jnag gb or serr!";
120 // Don't use the stack, because sp isn't set up.
121 volatile int wait = 1;
128 // Doesn't actually go on the stack, because there are lots of GPRs.
131 char lower = text[i] | 32;
132 if (lower >= 'a' && lower <= 'm')
134 else if (lower > 'm' && lower <= 'z')
143 OUTPUT_ARCH( "riscv" )
151 $ riscv64-unknown-elf-gcc -g -Og -o rot13-64.o -c rot13.c
152 $ riscv64-unknown-elf-gcc -g -Og -T spike.lds -nostartfiles -o rot13-64 rot13-64.o
155 To debug this program, first run spike telling it to listen for OpenOCD:
157 $ spike --rbb-port=9824 -m0x10000000:0x20000 rot13-64
158 Listening for remote bitbang connection on port 9824.
161 In a separate shell run OpenOCD with the appropriate configuration file:
164 interface remote_bitbang
165 remote_bitbang_host localhost
166 remote_bitbang_port 9824
169 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
171 set _TARGETNAME $_CHIPNAME.cpu
172 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
174 gdb_report_data_abort enable
178 $ openocd -f spike.cfg
179 Open On-Chip Debugger 0.10.0-dev-00002-gc3b344d (2017-06-08-12:14)
181 riscv.cpu: target state: halted
184 In yet another shell, start your gdb debug session:
186 tnewsome@compy-vm:~/SiFive/spike-test$ riscv64-unknown-elf-gdb rot13-64
187 GNU gdb (GDB) 7.12.50.20170505-git
188 Copyright (C) 2016 Free Software Foundation, Inc.
189 License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
190 This is free software: you are free to change and redistribute it.
191 There is NO WARRANTY, to the extent permitted by law. Type "show copying"
192 and "show warranty" for details.
193 This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv64-unknown-elf".
194 Type "show configuration" for configuration details.
195 For bug reporting instructions, please see:
196 <http://www.gnu.org/software/gdb/bugs/>.
197 Find the GDB manual and other documentation resources online at:
198 <http://www.gnu.org/software/gdb/documentation/>.
199 For help, type "help".
200 Type "apropos word" to search for commands related to "word"...
201 Reading symbols from rot13-64...done.
202 (gdb) target remote localhost:3333
203 Remote debugging using localhost:3333
204 0x000000001001000a in main () at rot13.c:8
211 $3 = "Vafgehpgvba frgf jnag gb or serr!"
213 Breakpoint 1 at 0x10010064: file rot13.c, line 23.
217 Breakpoint 1, main () at rot13.c:23