TLB/TLB.py

   1 from nmigen import Signal, Memory, Module, Case, If
   2 from nmigen.cli import main
   3 from PermissionValidator import PermissionValidator
   4
   5 class TLB():
   6     def __init__(self):
   7         # Inputs
   8         self.xwr = Signal(3) # Execute, Write, Read
   9         self.super = Signal(1) # Supervisor Mode
  10         self.super_access = Signal(1) # Supervisor Access
  11         self.command = Signal(2) # 00=None, 01=Search, 10=Write PTE, 11=Reset
  12         self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64
  13         self.asid = Signal(15) # Address Space IDentifier (ASID)
  14         self.vma = Signal(36) # Virtual Memory Address (VMA)
  15         self.pte_in = Signal(64) # To be saved Page Table Entry (PTE)
  16
  17         # Outputs
  18         self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
  19         self.valid = Signal(1) # Denotes if the permissions are correct
  20         self.pteOut = Signal(64) # PTE that was mapped to by the VMA
  21
  22         # Cam simulations
  23         mem_l1 = Memory(113, 32) # L1 TLB cache
  24         read_port_l1 = mem_l1.read_port
  25         write_port_l1 = mem_l1.write_port
  26
  27         mem_l2 = Memory(113, 128) # L2 TLB cache
  28         read_port_l2 = mem_l2.read_port
  29         write_port_l2 = mem_l2.write_port
  30
  31         def elaborate(self, platform):
  32             m = Module()
  33             m.d.submodules.perm_valid = perm_valid = PermissionValidator(113)
  34             m.d.sync += [
  35                 Case(self.command, {
  36                    # Search for PTE
  37                    1: [
  38                        # Check first entry in set
  39                        # TODO make module?
  40                        read_port_l1.addr.eq(vma[0,2]),
  41                        If(read_port_l1.data[0] == 1,
  42                           perm_valid.data.eq(read_port_l1.data),
  43                           perm_valid.xwr.eq(self.xwr),
  44                           perm_valid.super.eq(self.super),
  45                           perm_valid.super_access.eq(self.super_access),
  46                           perm_valid.asid.eq(self.asid),
  47                           self.valid,eq(perm_valid.valid)
  48                        ),
  49                        If(self.valid == 0,
  50                           read_port_l1.addr.eq(vma[0,2] + 1),
  51                           If(read_port_l1.data[0] == 1,
  52                              perm_valid.data.eq(read_port_l1.data),
  53                              perm_valid.xwr.eq(self.xwr),
  54                              perm_valid.super.eq(self.super),
  55                              perm_valid.super_access.eq(self.super_access),
  56                              perm_valid.asid.eq(self.asid),
  57                              self.valid,eq(perm_valid.valid)
  58                           )
  59                        )
  60                        ]
  61                 })
  62             ]
  63
  64 thing = TLB()
  65 print("Gottem")