c19a6b101b6adf74ea3f6d94a344927fdf737433
2 # Copyright 2018 ETH Zurich and University of Bologna.
3 # Copyright and related rights are licensed under the Solderpad Hardware
4 # License, Version 0.51 (the "License"); you may not use this file except in
5 # compliance with the License. You may obtain a copy of the License at
6 # http:#solderpad.org/licenses/SHL-0.51. Unless required by applicable law
7 # or agreed to in writing, software, hardware and materials distributed under
8 # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
9 # CONDITIONS OF ANY KIND, either express or implied. See the License for the
10 # specific language governing permissions and limitations under the License.
12 # Author: David Schaffenrath, TU Graz
13 # Author: Florian Zaruba, ETH Zurich
15 # Description: Hardware-PTW
17 /* verilator lint_off WIDTH */
20 see linux kernel source:
22 * "arch/riscv/include/asm/page.h"
23 * "arch/riscv/include/asm/mmu_context.h"
24 * "arch/riscv/Kconfig" (CONFIG_PAGE_OFFSET)
28 from nmigen
import Const
, Signal
, Cat
, Module
29 from nmigen
.hdl
.ast
import ArrayProxy
30 from nmigen
.cli
import verilog
, rtlil
35 CONFIG_L1D_SIZE
= 32*1024
36 DCACHE_INDEX_WIDTH
= int(log2(CONFIG_L1D_SIZE
/ DCACHE_SET_ASSOC
))
37 DCACHE_TAG_WIDTH
= 56 - DCACHE_INDEX_WIDTH
44 self
.address_index
= Signal(DCACHE_INDEX_WIDTH
)
45 self
.address_tag
= Signal(DCACHE_TAG_WIDTH
)
46 self
.data_wdata
= Signal(64)
47 self
.data_req
= Signal()
48 self
.data_we
= Signal()
49 self
.data_be
= Signal(8)
50 self
.data_size
= Signal(2)
51 self
.kill_req
= Signal()
52 self
.tag_valid
= Signal()
55 return [self
.address_index
, self
.address_tag
,
56 self
.data_wdata
, self
.data_req
,
57 self
.data_we
, self
.data_be
, self
.data_size
,
58 self
.kill_req
, self
.tag_valid
,
63 self
.data_gnt
= Signal()
64 self
.data_rvalid
= Signal()
65 self
.data_rdata
= Signal(64) # actually in PTE object format
68 return [ self
.data_gnt
, self
.data_rvalid
, self
.data_rdata
]
71 class PTE
: #(RecordObject):
73 self
.reserved
= Signal(10)
86 return Cat(*self
.ports())
89 if isinstance(x
, ArrayProxy
):
91 for o
in self
.ports():
92 i
= getattr(x
, o
.name
)
97 return self
.flatten().eq(x
)
100 return [self
.reserved
, self
.ppn
, self
.rsw
, self
.d
, self
.a
, self
.g
,
101 self
.u
, self
.x
, self
.w
, self
.r
, self
.v
]
106 self
.valid
= Signal() # valid flag
107 self
.is_2M
= Signal()
108 self
.is_1G
= Signal()
109 self
.vpn
= Signal(27)
110 self
.asid
= Signal(ASID_WIDTH
)
114 return Cat(*self
.ports())
117 return self
.flatten().eq(x
.flatten())
120 return [self
.valid
, self
.is_2M
, self
.is_1G
, self
.vpn
, self
.asid
] + \
124 # SV39 defines three levels of page tables
125 LVL1
= Const(0, 2) # defined to 0 so that ptw_lvl default-resets to LVL1
132 self
.flush_i
= Signal() # flush everything, we need to do this because
133 # actually everything we do is speculative at this stage
134 # e.g.: there could be a CSR instruction that changes everything
135 self
.ptw_active_o
= Signal(reset
=1) # active if not IDLE
136 self
.walking_instr_o
= Signal() # set when walking for TLB
137 self
.ptw_error_o
= Signal() # set when an error occurred
138 self
.enable_translation_i
= Signal() # CSRs indicate to enable SV39
139 self
.en_ld_st_translation_i
= Signal() # enable VM translation for ld/st
141 self
.lsu_is_store_i
= Signal() # translation triggered by store
142 # PTW memory interface
143 self
.req_port_i
= DCacheReqO()
144 self
.req_port_o
= DCacheReqI()
146 # to TLBs, update logic
147 self
.itlb_update_o
= TLBUpdate()
148 self
.dtlb_update_o
= TLBUpdate()
150 self
.update_vaddr_o
= Signal(39)
152 self
.asid_i
= Signal(ASID_WIDTH
)
155 self
.itlb_access_i
= Signal()
156 self
.itlb_hit_i
= Signal()
157 self
.itlb_vaddr_i
= Signal(64)
159 self
.dtlb_access_i
= Signal()
160 self
.dtlb_hit_i
= Signal()
161 self
.dtlb_vaddr_i
= Signal(64)
163 self
.satp_ppn_i
= Signal(44) # ppn from satp
164 self
.mxr_i
= Signal()
165 # Performance counters
166 self
.itlb_miss_o
= Signal()
167 self
.dtlb_miss_o
= Signal()
170 return [self
.ptw_active_o
, self
.walking_instr_o
, self
.ptw_error_o
,
173 self
.enable_translation_i
, self
.en_ld_st_translation_i
,
174 self
.lsu_is_store_i
, self
.req_port_i
, self
.req_port_o
,
177 self
.itlb_access_i
, self
.itlb_hit_i
, self
.itlb_vaddr_i
,
178 self
.dtlb_access_i
, self
.dtlb_hit_i
, self
.dtlb_vaddr_i
,
179 self
.satp_ppn_i
, self
.mxr_i
,
180 self
.itlb_miss_o
, self
.dtlb_miss_o
181 ] + self
.itlb_update_o
.ports() + self
.dtlb_update_o
.ports()
183 def elaborate(self
, platform
):
187 data_rvalid
= Signal()
188 data_rdata
= Signal(64)
190 # NOTE: pte decodes the incoming bit-field (data_rdata). data_rdata
191 # is spec'd in 64-bit binary-format: better to spec as Record?
193 m
.d
.comb
+= pte
.flatten().eq(data_rdata
)
195 # SV39 defines three levels of page tables
196 ptw_lvl
= Signal(2) # default=0=LVL1 on reset (see above)
200 m
.d
.comb
+= [ptw_lvl1
.eq(ptw_lvl
== LVL1
),
201 ptw_lvl2
.eq(ptw_lvl
== LVL2
),
202 ptw_lvl3
.eq(ptw_lvl
== LVL3
)]
204 # is this an instruction page table walk?
205 is_instr_ptw
= Signal()
206 global_mapping
= Signal()
210 tlb_update_asid
= Signal(ASID_WIDTH
)
211 # register VPN we need to walk, SV39 defines a 39 bit virtual addr
213 # 4 byte aligned physical pointer
214 ptw_pptr
= Signal(56)
216 end
= DCACHE_INDEX_WIDTH
+ DCACHE_TAG_WIDTH
219 self
.update_vaddr_o
.eq(vaddr
),
221 self
.walking_instr_o
.eq(is_instr_ptw
),
222 # directly output the correct physical address
223 self
.req_port_o
.address_index
.eq(ptw_pptr
[0:DCACHE_INDEX_WIDTH
]),
224 self
.req_port_o
.address_tag
.eq(ptw_pptr
[DCACHE_INDEX_WIDTH
:end
]),
225 # we are never going to kill this request
226 self
.req_port_o
.kill_req
.eq(0), # XXX assign comb?
227 # we are never going to write with the HPTW
228 self
.req_port_o
.data_wdata
.eq(Const(0, 64)), # XXX assign comb?
232 self
.itlb_update_o
.vpn
.eq(vaddr
[12:39]),
233 self
.dtlb_update_o
.vpn
.eq(vaddr
[12:39]),
234 # update the correct page table level
235 self
.itlb_update_o
.is_2M
.eq(ptw_lvl2
),
236 self
.itlb_update_o
.is_1G
.eq(ptw_lvl1
),
237 self
.dtlb_update_o
.is_2M
.eq(ptw_lvl2
),
238 self
.dtlb_update_o
.is_1G
.eq(ptw_lvl1
),
239 # output the correct ASID
240 self
.itlb_update_o
.asid
.eq(tlb_update_asid
),
241 self
.dtlb_update_o
.asid
.eq(tlb_update_asid
),
242 # set the global mapping bit
243 self
.itlb_update_o
.content
.eq(pte
),
244 self
.itlb_update_o
.content
.g
.eq(global_mapping
),
245 self
.dtlb_update_o
.content
.eq(pte
),
246 self
.dtlb_update_o
.content
.g
.eq(global_mapping
),
248 self
.req_port_o
.tag_valid
.eq(tag_valid
),
254 # A virtual address va is translated into a physical address pa as
256 # 1. Let a be sptbr.ppn × PAGESIZE, and let i = LEVELS-1. (For Sv39,
257 # PAGESIZE=2^12 and LEVELS=3.)
258 # 2. Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE.
259 # (For Sv32, PTESIZE=4.)
260 # 3. If pte.v = 0, or if pte.r = 0 and pte.w = 1, stop and raise an
262 # 4. Otherwise, the PTE is valid. If pte.r = 1 or pte.x = 1, go to
263 # step 5. Otherwise, this PTE is a pointer to the next level of
265 # Let i=i-1. If i < 0, stop and raise an access exception.
266 # Otherwise, let a = pte.ppn × PAGESIZE and go to step 2.
267 # 5. A leaf PTE has been found. Determine if the requested memory
268 # access is allowed by the pte.r, pte.w, and pte.x bits. If not,
269 # stop and raise an access exception. Otherwise, the translation is
270 # successful. Set pte.a to 1, and, if the memory access is a
271 # store, set pte.d to 1.
272 # The translated physical address is given as follows:
273 # - pa.pgoff = va.pgoff.
274 # - If i > 0, then this is a superpage translation and
275 # pa.ppn[i-1:0] = va.vpn[i-1:0].
276 # - pa.ppn[LEVELS-1:i] = pte.ppn[LEVELS-1:i].
277 # 6. If i > 0 and pa.ppn[i − 1 : 0] != 0, this is a misaligned
278 # superpage stop and raise a page-fault exception.
280 m
.d
.sync
+= tag_valid
.eq(0)
282 # default assignments
284 # PTW memory interface
285 self
.req_port_o
.data_req
.eq(0),
286 self
.req_port_o
.data_be
.eq(Const(0xFF, 8)),
287 self
.req_port_o
.data_size
.eq(Const(0b11, 2)),
288 self
.req_port_o
.data_we
.eq(0),
289 self
.ptw_error_o
.eq(0),
290 self
.itlb_update_o
.valid
.eq(0),
291 self
.dtlb_update_o
.valid
.eq(0),
293 self
.itlb_miss_o
.eq(0),
294 self
.dtlb_miss_o
.eq(0),
303 with m
.State("IDLE"):
304 self
.idle(m
, is_instr_ptw
, ptw_lvl
, global_mapping
,
305 ptw_pptr
, vaddr
, tlb_update_asid
)
307 with m
.State("WAIT_GRANT"):
308 self
.grant(m
, tag_valid
, data_rvalid
)
310 with m
.State("PTE_LOOKUP"):
311 # we wait for the valid signal
312 with m
.If(data_rvalid
):
313 self
.lookup(m
, pte
, ptw_lvl
, ptw_lvl1
, ptw_lvl2
, ptw_lvl3
,
314 data_rvalid
, global_mapping
,
315 is_instr_ptw
, ptw_pptr
)
317 # Propagate error to MMU/LSU
318 with m
.State("PROPAGATE_ERROR"):
320 m
.d
.comb
+= self
.ptw_error_o
.eq(1)
322 # wait for the rvalid before going back to IDLE
323 with m
.State("WAIT_RVALID"):
324 with m
.If(data_rvalid
):
327 m
.d
.sync
+= [data_rdata
.eq(self
.req_port_i
.data_rdata
),
328 data_rvalid
.eq(self
.req_port_i
.data_rvalid
)
333 def set_grant_state(self
, m
):
334 # should we have flushed before we got an rvalid,
335 # wait for it until going back to IDLE
336 with m
.If(self
.flush_i
):
337 with m
.If (self
.req_port_i
.data_gnt
):
338 m
.next
= "WAIT_RVALID"
342 m
.next
= "WAIT_GRANT"
344 def idle(self
, m
, is_instr_ptw
, ptw_lvl
, global_mapping
,
345 ptw_pptr
, vaddr
, tlb_update_asid
):
346 # by default we start with the top-most page table
347 m
.d
.sync
+= [is_instr_ptw
.eq(0),
349 global_mapping
.eq(0),
350 self
.ptw_active_o
.eq(0), # deactive (IDLE)
352 # work out itlb/dtlb miss
353 m
.d
.comb
+= self
.itlb_miss_o
.eq(self
.enable_translation_i
& \
354 self
.itlb_access_i
& \
357 m
.d
.comb
+= self
.dtlb_miss_o
.eq(self
.en_ld_st_translation_i
& \
358 self
.dtlb_access_i
& \
360 # we got an ITLB miss?
361 with m
.If(self
.itlb_miss_o
):
362 pptr
= Cat(Const(0, 3), self
.itlb_vaddr_i
[30:39],
364 m
.d
.sync
+= [ptw_pptr
.eq(pptr
),
366 vaddr
.eq(self
.itlb_vaddr_i
),
367 tlb_update_asid
.eq(self
.asid_i
),
369 self
.set_grant_state(m
)
371 # we got a DTLB miss?
372 with m
.Elif(self
.dtlb_miss_o
):
373 pptr
= Cat(Const(0, 3), self
.dtlb_vaddr_i
[30:39],
375 m
.d
.sync
+= [ptw_pptr
.eq(pptr
),
376 vaddr
.eq(self
.dtlb_vaddr_i
),
377 tlb_update_asid
.eq(self
.asid_i
),
379 self
.set_grant_state(m
)
381 def grant(self
, m
, tag_valid
, data_rvalid
):
382 # we've got a data WAIT_GRANT so tell the
383 # cache that the tag is valid
386 m
.d
.comb
+= self
.req_port_o
.data_req
.eq(1)
387 # wait for the WAIT_GRANT
388 with m
.If(self
.req_port_i
.data_gnt
):
389 # send the tag valid signal one cycle later
390 m
.d
.sync
+= tag_valid
.eq(1)
391 # should we have flushed before we got an rvalid,
392 # wait for it until going back to IDLE
393 with m
.If(self
.flush_i
):
394 with m
.If (~data_rvalid
):
395 m
.next
= "WAIT_RVALID"
399 m
.next
= "PTE_LOOKUP"
401 def lookup(self
, m
, pte
, ptw_lvl
, ptw_lvl1
, ptw_lvl2
, ptw_lvl3
,
402 data_rvalid
, global_mapping
,
403 is_instr_ptw
, ptw_pptr
):
405 pte_rx
= Signal(reset_less
=True)
406 pte_exe
= Signal(reset_less
=True)
407 pte_inv
= Signal(reset_less
=True)
408 pte_a
= Signal(reset_less
=True)
409 st_wd
= Signal(reset_less
=True)
410 m
.d
.comb
+= [pte_rx
.eq(pte
.r | pte
.x
),
411 pte_exe
.eq(~pte
.x | ~pte
.a
),
412 pte_inv
.eq(~pte
.v |
(~pte
.r
& pte
.w
)),
413 pte_a
.eq(pte
.a
& (pte
.r |
(pte
.x
& self
.mxr_i
))),
414 st_wd
.eq(self
.lsu_is_store_i
& (~pte
.w | ~pte
.d
))]
416 l1err
= Signal(reset_less
=True)
417 l2err
= Signal(reset_less
=True)
418 m
.d
.comb
+= [l2err
.eq((ptw_lvl2
) & pte
.ppn
[0:9] != Const(0, 9)),
419 l1err
.eq((ptw_lvl1
) & pte
.ppn
[0:18] != Const(0, 18)) ]
421 # check if the global mapping bit is set
423 m
.d
.sync
+= global_mapping
.eq(1)
430 # If pte.v = 0, or if pte.r = 0 and pte.w = 1,
431 # stop and raise a page-fault exception.
433 m
.next
= "PROPAGATE_ERROR"
440 # if pte.r = 1 or pte.x = 1 it is a valid PTE
441 with m
.Elif (pte_rx
):
442 # Valid translation found (either 1G, 2M or 4K)
443 with m
.If(is_instr_ptw
):
447 # If page not executable, we can directly raise error.
448 # This doesn't put a useless entry into the TLB.
449 # The same idea applies to the access flag since we let
450 # the access flag be managed by SW.
454 m
.d
.comb
+= self
.itlb_update_o
.valid
.eq(1)
460 # Check if the access flag has been set, otherwise
461 # throw page-fault and let software handle those bits.
462 # If page not readable (there are no write-only pages)
463 # directly raise an error. This doesn't put a useless
464 # entry into the TLB.
466 m
.d
.comb
+= self
.dtlb_update_o
.valid
.eq(1)
468 m
.next
= "PROPAGATE_ERROR"
469 # Request is a store: perform additional checks
470 # If the request was a store and the page not
471 # write-able, raise an error
472 # the same applies if the dirty flag is not set
474 m
.d
.comb
+= self
.dtlb_update_o
.valid
.eq(0)
475 m
.next
= "PROPAGATE_ERROR"
477 # check if the ppn is correctly aligned: Case (6)
478 with m
.If(l1err | l2err
):
479 m
.next
= "PROPAGATE_ERROR"
480 m
.d
.comb
+= [self
.dtlb_update_o
.valid
.eq(0),
481 self
.itlb_update_o
.valid
.eq(0)]
483 # this is a pointer to the next TLB level
485 # pointer to next level of page table
486 with m
.If (ptw_lvl1
):
487 # we are in the second level now
488 pptr
= Cat(Const(0, 3), self
.dtlb_vaddr_i
[21:30], pte
.ppn
)
489 m
.d
.sync
+= [ptw_pptr
.eq(pptr
),
493 # here we received a pointer to the third level
494 pptr
= Cat(Const(0, 3), self
.dtlb_vaddr_i
[12:21], pte
.ppn
)
495 m
.d
.sync
+= [ptw_pptr
.eq(pptr
),
498 self
.set_grant_state(m
)
500 with m
.If (ptw_lvl3
):
501 # Should already be the last level
502 # page table => Error
503 m
.d
.sync
+= ptw_lvl
.eq(LVL3
)
504 m
.next
= "PROPAGATE_ERROR"
507 if __name__
== '__main__':
509 vl
= rtlil
.convert(ptw
, ports
=ptw
.ports())
510 with
open("test_ptw.il", "w") as f
: