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Merge branch 'master' of github.com:ucb-bar/riscv-tests
[riscv-tests.git]
/
benchmarks
/
common
/
crt-mt.S
1
#include "pcr.h"
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.data
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.globl _heapend
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.globl environ
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_heapend:
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.word 0
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environ:
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.word 0
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.text
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.globl _start
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_start:
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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# enable fp
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setpcr status, SR_EF
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# enable vec
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setpcr t0, status, SR_EV
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## if that didn't stick, we don't have an FPU, so don't initialize it
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and t0, t0, SR_EF
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beqz t0, 1f
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fssr x0
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fmv.s.x f0, x0
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fmv.s.x f1, x0
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fmv.s.x f2, x0
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fmv.s.x f3, x0
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fmv.s.x f4, x0
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fmv.s.x f5, x0
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fmv.s.x f6, x0
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fmv.s.x f7, x0
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fmv.s.x f8, x0
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fmv.s.x f9, x0
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fmv.s.x f10,x0
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fmv.s.x f11,x0
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fmv.s.x f12,x0
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fmv.s.x f13,x0
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fmv.s.x f14,x0
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fmv.s.x f15,x0
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fmv.s.x f16,x0
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fmv.s.x f17,x0
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fmv.s.x f18,x0
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fmv.s.x f19,x0
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fmv.s.x f20,x0
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fmv.s.x f21,x0
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fmv.s.x f22,x0
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fmv.s.x f23,x0
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fmv.s.x f24,x0
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fmv.s.x f25,x0
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fmv.s.x f26,x0
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fmv.s.x f27,x0
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fmv.s.x f28,x0
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fmv.s.x f29,x0
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fmv.s.x f30,x0
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fmv.s.x f31,x0
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1:
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# get core id and number of cores
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mfpcr a0,hartid
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lw a1, 4(zero)
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slli a2, a0, 13
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la sp, stacktop
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sub sp, sp, a2
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la tp, tlstop
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sub tp, tp, a2
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jal thread_entry
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.bss
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.globl stacktop
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.globl tlstop
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.align 4
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.skip 32768
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stacktop:
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.skip 65536
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tlstop: