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HEAD
benchmarks initial commit
[riscv-tests.git]
/
benchmarks
/
common
/
crt.S
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.data
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.globl _heapend
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.globl environ
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_heapend:
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.word 0
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environ:
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.word 0
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.text
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.globl _start
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_start:
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li x1, 0
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li x2, 0
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li x3, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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li x13,0
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li x14,0
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li x15,0
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li x16,0
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li x17,0
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li x18,0
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li x19,0
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li x20,0
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li x21,0
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li x22,0
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li x23,0
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li x24,0
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li x25,0
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li x26,0
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li x27,0
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li x28,0
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li x29,0
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li x30,0
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li x31,0
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# enable fp
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mfpcr x1,cr0
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ori x1,x1,0x2
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mtpcr x1,cr0
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# enable vec
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mfpcr x1,cr0
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ori x1,x1,0x4
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mtpcr x1,cr0
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## if that didn't stick, we don't have an FPU, so don't initialize it
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mfpcr x1,cr0
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andi x1,x1,0x2
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beqz x1,1f
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mtfsr x0
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mxtf.s f0, x0
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mxtf.s f1, x0
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mxtf.s f2, x0
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mxtf.s f3, x0
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mxtf.s f4, x0
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mxtf.s f5, x0
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mxtf.s f6, x0
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mxtf.s f7, x0
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mxtf.s f8, x0
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mxtf.s f9, x0
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mxtf.s f10,x0
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mxtf.s f11,x0
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mxtf.s f12,x0
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mxtf.s f13,x0
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mxtf.s f14,x0
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mxtf.s f15,x0
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mxtf.s f16,x0
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mxtf.s f17,x0
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mxtf.s f18,x0
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mxtf.s f19,x0
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mxtf.s f20,x0
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mxtf.s f21,x0
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mxtf.s f22,x0
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mxtf.s f23,x0
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mxtf.s f24,x0
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mxtf.s f25,x0
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mxtf.s f26,x0
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mxtf.s f27,x0
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mxtf.s f28,x0
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mxtf.s f29,x0
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mxtf.s f30,x0
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mxtf.s f31,x0
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1:
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# only allow core 0 to proceed
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1:mfpcr a0, cr10
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bnez a0, 1b
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la sp,stacktop
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jal main
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1:b 1b
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.bss
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.globl stacktop
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.align 4
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.skip 131072
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stacktop: