c4m/nmigen/jtag/tap.py

   1 #!/usr/bin/env python3
   2 import os, textwrap
   3 from enum import Enum, auto
   4
   5 from nmigen import (Elaboratable, Signal, Module, ClockDomain, Cat, Record,
   6                     Const, Mux)
   7 from nmigen.hdl.rec import Direction, Layout
   8 from nmigen.tracer import get_var_name
   9
  10 from nmigen_soc.wishbone import Interface as WishboneInterface
  11
  12 from .bus import Interface
  13
  14 __all__ = [
  15     "TAP", "ShiftReg", "IOType", "IOConn",
  16 ]
  17
  18
  19 class _FSM(Elaboratable):
  20     """TAP subblock for the FSM"""
  21     def __init__(self, *, bus):
  22         self.isir = Signal()
  23         self.isdr = Signal()
  24         self.capture = Signal()
  25         self.shift = Signal()
  26         self.update = Signal()
  27
  28         # JTAG uses both edges of the incoming clock (TCK). set them up here
  29         self.posjtag = ClockDomain("posjtag", local=True)
  30         self.negjtag = ClockDomain("negjtag", local=True, clk_edge="neg")
  31
  32         self._bus = bus
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36
  37         rst = Signal()
  38         m.d.comb += [
  39             self.posjtag.clk.eq(self._bus.tck),
  40             self.posjtag.rst.eq(rst),
  41             self.negjtag.clk.eq(self._bus.tck),
  42             self.negjtag.rst.eq(rst),
  43         ]
  44
  45         # Make local clock domain optionally using trst of JTAG bus as reset
  46         if hasattr(self._bus, "trst"):
  47             m.domains.local = local = ClockDomain(local=True)
  48             m.d.comb += local.rst.eq(self._bus.trst)
  49         else:
  50             m.domains.local = local = ClockDomain(local=True, reset_less=True)
  51         m.d.comb += local.clk.eq(self._bus.tck)
  52
  53         with m.FSM(domain="local") as fsm:
  54             with m.State("TestLogicReset"):
  55                 # Be sure to reset isir, isdr
  56                 m.d.local += [
  57                     self.isir.eq(0),
  58                     self.isdr.eq(0),
  59                 ]
  60                 with m.If(self._bus.tms == 0):
  61                     m.next = "RunTestIdle"
  62             with m.State("RunTestIdle"):
  63                 # Be sure to reset isir, isdr
  64                 m.d.local += [
  65                     self.isir.eq(0),
  66                     self.isdr.eq(0),
  67                 ]
  68                 with m.If(self._bus.tms == 1):
  69                     m.next = "SelectDRScan"
  70             with m.State("SelectDRScan"):
  71                 with m.If(self._bus.tms == 0):
  72                     m.d.local += self.isdr.eq(1)
  73                     m.next = "CaptureState"
  74                 with m.Else():
  75                     m.next = "SelectIRScan"
  76             with m.State("SelectIRScan"):
  77                 with m.If(self._bus.tms == 0):
  78                     m.d.local += self.isir.eq(1)
  79                     m.next = "CaptureState"
  80                 with m.Else():
  81                     m.next = "TestLogicReset"
  82             with m.State("CaptureState"):
  83                 with m.If(self._bus.tms == 0):
  84                     m.next = "ShiftState"
  85                 with m.Else():
  86                     m.next = "Exit1"
  87             with m.State("ShiftState"):
  88                 with m.If(self._bus.tms == 1):
  89                     m.next = "Exit1"
  90             with m.State("Exit1"):
  91                 with m.If(self._bus.tms == 0):
  92                     m.next = "Pause"
  93                 with m.Else():
  94                     m.next = "UpdateState"
  95             with m.State("Pause"):
  96                 with m.If(self._bus.tms == 1):
  97                     m.next = "Exit2"
  98             with m.State("Exit2"):
  99                 with m.If(self._bus.tms == 0):
 100                     m.next = "ShiftState"
 101                 with m.Else():
 102                     m.next = "UpdateState"
 103             with m.State("UpdateState"):
 104                 m.d.local += [
 105                     self.isir.eq(0),
 106                     self.isdr.eq(0),
 107                 ]
 108                 with m.If(self._bus.tms == 0):
 109                     m.next = "RunTestIdle"
 110                 with m.Else():
 111                     m.next = "SelectDRScan"
 112
 113             m.d.comb += [
 114                 rst.eq(fsm.ongoing("TestLogicReset")),
 115                 self.capture.eq(fsm.ongoing("CaptureState")),
 116                 self.shift.eq(fsm.ongoing("ShiftState")),
 117                 self.update.eq(fsm.ongoing("UpdateState")),
 118             ]
 119
 120         return m
 121
 122 class _IRBlock(Elaboratable):
 123     """TAP subblock for handling the IR shift register"""
 124     def __init__(self, *, ir_width, cmd_idcode,
 125                  tdi, capture, shift, update,
 126                  name):
 127         self.name = name
 128         self.ir = Signal(ir_width, reset=cmd_idcode)
 129         self.tdo = Signal()
 130
 131         self._tdi = tdi
 132         self._capture = capture
 133         self._shift = shift
 134         self._update = update
 135
 136     def elaborate(self, platform):
 137         m = Module()
 138
 139         shift_ir = Signal(len(self.ir), reset_less=True)
 140
 141         m.d.comb += self.tdo.eq(self.ir[0])
 142         with m.If(self._capture):
 143             m.d.posjtag += shift_ir.eq(self.ir)
 144         with m.Elif(self._shift):
 145             m.d.posjtag += shift_ir.eq(Cat(shift_ir[1:], self._tdi))
 146         with m.Elif(self._update):
 147             # For ir we only update it on the rising edge of clock
 148             # to avoid that we already have the new ir value when still in
 149             # Update state
 150             m.d.posjtag += self.ir.eq(shift_ir)
 151
 152         return m
 153
 154 class IOType(Enum):
 155     In = auto()
 156     Out = auto()
 157     TriOut = auto()
 158     InTriOut = auto()
 159
 160 class IOConn(Record):
 161     """TAP subblock representing the interface for an JTAG IO cell.
 162     It contains signal to connect to the core and to the pad
 163
 164     This object is normally only allocated and returned from ``TAP.add_io``
 165     It is a Record subclass.
 166
 167     Attributes
 168     ----------
 169     core: subrecord with signals for the core
 170         i: Signal(1), present only for IOType.In and IOType.InTriOut.
 171             Signal input to core with pad input value.
 172         o: Signal(1), present only for IOType.Out, IOType.TriOut and
 173             IOType.InTriOut.
 174             Signal output from core with the pad output value.
 175         oe: Signal(1), present only for IOType.TriOut and IOType.InTriOut.
 176             Signal output from core with the pad output enable value.
 177     pad: subrecord with for the pad
 178         i: Signal(1), present only for IOType.In and IOType.InTriOut
 179             Output from pad with pad input value for core.
 180         o: Signal(1), present only for IOType.Out, IOType.TriOut and
 181             IOType.InTriOut.
 182             Input to pad with pad output value.
 183         oe: Signal(1), present only for IOType.TriOut and IOType.InTriOut.
 184             Input to pad with pad output enable value.
 185     """
 186     @staticmethod
 187     def layout(iotype):
 188         sigs = []
 189         if iotype in (IOType.In, IOType.InTriOut):
 190             sigs.append(("i", 1))
 191         if iotype in (IOType.Out, IOType.TriOut, IOType.InTriOut):
 192             sigs.append(("o", 1))
 193         if iotype in (IOType.TriOut, IOType.InTriOut):
 194             sigs.append(("oe", 1))
 195
 196         return Layout((("core", sigs), ("pad", sigs)))
 197
 198     def __init__(self, *, iotype, name=None, src_loc_at=0):
 199         super().__init__(self.__class__.layout(iotype), name=name,
 200                          src_loc_at=src_loc_at+1)
 201
 202         self._iotype = iotype
 203
 204 class _IDBypassBlock(Elaboratable):
 205     """TAP subblock for the ID shift register"""
 206     def __init__(self, *, manufacturer_id, part_number, version,
 207                  tdi, capture, shift, update, bypass,
 208                  name):
 209         self.name = name
 210         if (not isinstance(manufacturer_id, Const) and
 211             len(manufacturer_id) != 11):
 212             raise ValueError("manufacturer_id has to be Const of length 11")
 213         if not isinstance(part_number, Const) and len(manufacturer_id) != 16:
 214             raise ValueError("part_number has to be Const of length 16")
 215         if not isinstance(version, Const) and len(version) != 4:
 216             raise ValueError("version has to be Const of length 4")
 217         self._id = Cat(Const(1,1), manufacturer_id, part_number, version)
 218
 219         self.tdo = Signal(name=name+"_tdo")
 220
 221         self._tdi = tdi
 222         self._capture = capture
 223         self._shift = shift
 224         self._update = update
 225         self._bypass = bypass
 226
 227     def elaborate(self, platform):
 228         m = Module()
 229
 230         sr = Signal(32, reset_less=True, name=self.name+"_sr")
 231
 232         # Local signals for the module
 233         _tdi = Signal()
 234         _capture = Signal()
 235         _shift = Signal()
 236         _update = Signal()
 237         _bypass = Signal()
 238
 239         m.d.comb += [
 240             _tdi.eq(self._tdi),
 241             _capture.eq(self._capture),
 242             _shift.eq(self._shift),
 243             _update.eq(self._update),
 244             _bypass.eq(self._bypass),
 245             self.tdo.eq(sr[0]),
 246         ]
 247
 248         with m.If(_capture):
 249             m.d.posjtag += sr.eq(self._id)
 250         with m.Elif(_shift):
 251             with m.If(_bypass):
 252                 m.d.posjtag += sr[0].eq(_tdi)
 253             with m.Else():
 254                 m.d.posjtag += sr.eq(Cat(sr[1:], _tdi))
 255
 256         return m
 257
 258
 259 class ShiftReg(Record):
 260     """Object with interface for extra shift registers on a TAP.
 261
 262     Parameters
 263     ----------
 264     sr_length : int
 265     cmds : int, default=1
 266         The number of corresponding JTAG instructions
 267
 268     This object is normally only allocated and returned from ``TAP.add_shiftreg``
 269     It is a Record subclass.
 270
 271     Attributes
 272     ----------
 273     i: length=sr_length, FANIN
 274         The input data sampled during capture state of the TAP
 275     ie: length=cmds, FANOUT
 276         Indicates that data is to be sampled by the JTAG TAP and
 277         should be held stable. The bit indicates the corresponding
 278         instruction for which data is asked.
 279         This signal is kept high for a whole JTAG TAP clock cycle
 280         and may thus be kept higher for more than one clock cycle
 281         on the domain where ShiftReg is used.
 282         The JTAG protocol does not allow insertion of wait states
 283         so data need to be provided before ie goes down. The speed
 284         of the response will determine the max. frequency for the
 285         JTAG interface.
 286     o: length=sr_length, FANOUT
 287         The value of the shift register.
 288     oe: length=cmds, FANOUT
 289         Indicates that output is stable and can be sampled downstream because
 290         JTAG TAP is in the Update state. The bit indicates the corresponding
 291         instruction. The bit is only kept high for one clock cycle.
 292     """
 293     def __init__(self, *, sr_length, cmds=1, name=None, src_loc_at=0):
 294         layout = [
 295             ("i", sr_length, Direction.FANIN),
 296             ("ie", cmds, Direction.FANOUT),
 297             ("o", sr_length, Direction.FANOUT),
 298             ("oe", cmds, Direction.FANOUT),
 299         ]
 300         super().__init__(layout, name=name, src_loc_at=src_loc_at+1)
 301
 302
 303 class TAP(Elaboratable):
 304     #TODO: Document TAP
 305     def __init__(
 306         self, *, with_reset=False, ir_width=None,
 307         manufacturer_id=Const(0b10001111111, 11), part_number=Const(1, 16),
 308         version=Const(0, 4),
 309         name=None, src_loc_at=0
 310     ):
 311         assert((ir_width is None) or (isinstance(ir_width, int) and
 312                ir_width >= 2))
 313         assert(len(version) == 4)
 314
 315         if name is None:
 316             name = get_var_name(depth=src_loc_at+2, default="TAP")
 317         self.name = name
 318         self.bus = Interface(with_reset=with_reset, name=self.name+"_bus",
 319                              src_loc_at=src_loc_at+1)
 320
 321         ##
 322
 323         self._ir_width = ir_width
 324         self._manufacturer_id = manufacturer_id
 325         self._part_number = part_number
 326         self._version = version
 327
 328         self._ircodes = [0, 1, 2] # Already taken codes, all ones added at end
 329
 330         self._ios = []
 331         self._srs = []
 332         self._wbs = []
 333
 334     def elaborate(self, platform):
 335         m = Module()
 336
 337         # Determine ir_width if not fixed.
 338         ir_max = max(self._ircodes) + 1 # One extra code needed with all ones
 339         ir_width = len("{:b}".format(ir_max))
 340         if self._ir_width is not None:
 341             assert self._ir_width >= ir_width, "Specified JTAG IR width " \
 342                    "not big enough for allocated shiift registers"
 343             ir_width = self._ir_width
 344
 345         # TODO: Make commands numbers configurable
 346         cmd_extest = 0
 347         cmd_intest = 0
 348         cmd_idcode = 1
 349         cmd_sample = 2
 350         cmd_preload = 2
 351         cmd_bypass = 2**ir_width - 1 # All ones
 352
 353         m.submodules._fsm = fsm = _FSM(bus=self.bus)
 354         m.domains.posjtag = fsm.posjtag
 355         m.domains.negjtag = fsm.negjtag
 356
 357         # IR block
 358         select_ir = fsm.isir
 359         m.submodules._irblock = irblock = _IRBlock(
 360             ir_width=ir_width, cmd_idcode=cmd_idcode, tdi=self.bus.tdi,
 361             capture=(fsm.isir & fsm.capture),
 362             shift=(fsm.isir & fsm.shift),
 363             update=(fsm.isir & fsm.update),
 364             name=self.name+"_ir",
 365         )
 366         ir = irblock.ir
 367
 368         # ID block
 369         select_id = fsm.isdr & ((ir == cmd_idcode) | (ir == cmd_bypass))
 370         m.submodules._idblock = idblock = _IDBypassBlock(
 371             manufacturer_id=self._manufacturer_id,
 372             part_number=self._part_number,
 373             version=self._version, tdi=self.bus.tdi,
 374             capture=(select_id & fsm.capture),
 375             shift=(select_id & fsm.shift),
 376             update=(select_id & fsm.update),
 377             bypass=(ir == cmd_bypass),
 378             name=self.name+"_id",
 379         )
 380
 381         # IO (Boundary scan) block
 382         io_capture = Signal()
 383         io_shift = Signal()
 384         io_update = Signal()
 385         io_bd2io = Signal()
 386         io_bd2core = Signal()
 387         sample = (ir == cmd_extest) | (ir == cmd_sample)
 388         preload = (ir == cmd_preload)
 389         select_io = fsm.isdr & (sample | preload)
 390         m.d.comb += [
 391             io_capture.eq(sample & fsm.capture), # Don't capture if not sample
 392                                                  # (like for PRELOAD)
 393             io_shift.eq(select_io & fsm.shift),
 394             io_update.eq(select_io & fsm.update),
 395             io_bd2io.eq(ir == cmd_extest),
 396             io_bd2core.eq(ir == cmd_intest),
 397         ]
 398         io_tdo = self._elaborate_ios(
 399             m=m,
 400             capture=io_capture, shift=io_shift, update=io_update,
 401             bd2io=io_bd2io, bd2core=io_bd2core,
 402         )
 403
 404         # chain tdo: select as appropriate, to go into into shiftregs
 405         tdo = Signal(name=self.name+"_tdo")
 406         with m.If(select_ir):
 407             m.d.comb += tdo.eq(irblock.tdo)
 408         with m.Elif(select_id):
 409             m.d.comb += tdo.eq(idblock.tdo)
 410         with m.Elif(select_io):
 411             m.d.comb += tdo.eq(io_tdo)
 412
 413         # shiftregs block
 414         self._elaborate_shiftregs(
 415             m, capture=fsm.capture, shift=fsm.shift, update=fsm.update,
 416             ir=irblock.ir, tdo_jtag=tdo
 417         )
 418
 419         # wishbone
 420         self._elaborate_wishbones(m)
 421
 422         return m
 423
 424
 425     def add_io(self, *, iotype, name=None, src_loc_at=0):
 426         """Add a io cell to the boundary scan chain
 427
 428         Parameters:
 429         - iotype: :class:`IOType` enum.
 430
 431         Returns:
 432         - :class:`IOConn`
 433         """
 434         if name is None:
 435             name = "ioconn" + str(len(self._ios))
 436
 437         ioconn = IOConn(iotype=iotype, name=name, src_loc_at=src_loc_at+1)
 438         self._ios.append(ioconn)
 439         return ioconn
 440
 441     def _elaborate_ios(self, *, m, capture, shift, update, bd2io, bd2core):
 442         connlength = {
 443             IOType.In: 1,
 444             IOType.Out: 1,
 445             IOType.TriOut: 2,
 446             IOType.InTriOut: 3,
 447         }
 448         length = sum(connlength[conn._iotype] for conn in self._ios)
 449         if length == 0:
 450             return self.bus.tdi
 451
 452         io_sr = Signal(length)
 453         io_bd = Signal(length)
 454
 455         with m.If(capture):
 456             idx = 0
 457             for conn in self._ios:
 458                 if conn._iotype == IOType.In:
 459                     m.d.posjtag += io_sr[idx].eq(conn.pad.i)
 460                     idx += 1
 461                 elif conn._iotype == IOType.Out:
 462                     m.d.posjtag += io_sr[idx].eq(conn.core.o)
 463                     idx += 1
 464                 elif conn._iotype == IOType.TriOut:
 465                     m.d.posjtag += [
 466                         io_sr[idx].eq(conn.core.o),
 467                         io_sr[idx+1].eq(conn.core.oe),
 468                     ]
 469                     idx += 2
 470                 elif conn._iotype == IOType.InTriOut:
 471                     m.d.posjtag += [
 472                         io_sr[idx].eq(conn.pad.i),
 473                         io_sr[idx+1].eq(conn.core.o),
 474                         io_sr[idx+2].eq(conn.core.oe),
 475                     ]
 476                     idx += 3
 477                 else:
 478                     raise("Internal error")
 479             assert idx == length, "Internal error"
 480         with m.Elif(shift):
 481             m.d.posjtag += io_sr.eq(Cat(self.bus.tdi, io_sr[:-1]))
 482         with m.Elif(update):
 483             m.d.negjtag += io_bd.eq(io_sr)
 484
 485         idx = 0
 486         for conn in self._ios:
 487             if conn._iotype == IOType.In:
 488                 m.d.comb += conn.core.i.eq(Mux(bd2core, io_bd[idx], conn.pad.i))
 489                 idx += 1
 490             elif conn._iotype == IOType.Out:
 491                 m.d.comb += conn.pad.o.eq(Mux(bd2io, io_bd[idx], conn.core.o))
 492                 idx += 1
 493             elif conn._iotype == IOType.TriOut:
 494                 m.d.comb += [
 495                     conn.pad.o.eq(Mux(bd2io, io_bd[idx], conn.core.o)),
 496                     conn.pad.oe.eq(Mux(bd2io, io_bd[idx+1], conn.core.oe)),
 497                 ]
 498                 idx += 2
 499             elif conn._iotype == IOType.InTriOut:
 500                 m.d.comb += [
 501                     conn.core.i.eq(Mux(bd2core, io_bd[idx], conn.pad.i)),
 502                     conn.pad.o.eq(Mux(bd2io, io_bd[idx+1], conn.core.o)),
 503                     conn.pad.oe.eq(Mux(bd2io, io_bd[idx+2], conn.core.oe)),
 504                 ]
 505                 idx += 3
 506             else:
 507                 raise("Internal error")
 508         assert idx == length, "Internal error"
 509
 510         return io_sr[-1]
 511
 512     def add_shiftreg(self, *, ircode, length, domain="sync", name=None,
 513                      src_loc_at=0):
 514         """Add a shift register to the JTAG interface
 515
 516         Parameters:
 517         - ircode: code(s) for the IR; int or sequence of ints. In the latter
 518           case this shiftreg is shared between different IR codes.
 519         - length: the length of the shift register
 520         - domain: the domain on which the signal will be used"""
 521
 522         try:
 523             ir_it = iter(ircode)
 524             ircodes = ircode
 525         except TypeError:
 526             ir_it = ircodes = (ircode,)
 527         for _ircode in ir_it:
 528             if not isinstance(_ircode, int) or _ircode <= 0:
 529                 raise ValueError("IR code '{}' is not an int "
 530                                  "greater than 0".format(_ircode))
 531             if _ircode in self._ircodes:
 532                 raise ValueError("IR code '{}' already taken".format(_ircode))
 533
 534         self._ircodes.extend(ircodes)
 535
 536         if name is None:
 537             name = "sr{}".format(len(self._srs))
 538         sr = ShiftReg(sr_length=length, cmds=len(ircodes), name=name,
 539                       src_loc_at=src_loc_at+1)
 540         self._srs.append((ircodes, domain, sr))
 541
 542         return sr
 543
 544     def _elaborate_shiftregs(self, m, capture, shift, update, ir, tdo_jtag):
 545         # tdos is tuple of (tdo, tdo_en) for each shiftreg
 546         tdos = []
 547         for ircodes, domain, sr in self._srs:
 548             reg = Signal(len(sr.o), name=sr.name+"_reg")
 549             m.d.comb += sr.o.eq(reg)
 550
 551             isir = Signal(len(ircodes), name=sr.name+"_isir")
 552             sr_capture = Signal(name=sr.name+"_capture")
 553             sr_shift = Signal(name=sr.name+"_shift")
 554             sr_update = Signal(name=sr.name+"_update")
 555             m.d.comb += [
 556                 isir.eq(Cat(ir == ircode for ircode in ircodes)),
 557                 sr_capture.eq((isir != 0) & capture),
 558                 sr_shift.eq((isir != 0) & shift),
 559                 sr_update.eq((isir != 0) & update),
 560             ]
 561
 562             # update signal is on the JTAG clockdomain, sr.oe is on `domain`
 563             # clockdomain latch update in `domain` clockdomain and see when
 564             # it has falling edge.
 565             # At that edge put isir in sr.oe for one `domain` clockdomain
 566             update_core = Signal(name=sr.name+"_update_core")
 567             update_core_prev = Signal(name=sr.name+"_update_core_prev")
 568             m.d[domain] += [
 569                 update_core.eq(sr_update), # This is CDC from JTAG domain
 570                                            # to given domain
 571                 update_core_prev.eq(update_core)
 572             ]
 573             with m.If(update_core_prev & ~update_core):
 574                 # Falling edge of update
 575                 m.d[domain] += sr.oe.eq(isir)
 576             with m.Else():
 577                 m.d[domain] += sr.oe.eq(0)
 578
 579             with m.If(sr_shift):
 580                 m.d.posjtag += reg.eq(Cat(reg[1:], self.bus.tdi))
 581             with m.If(sr_capture):
 582                 m.d.posjtag += reg.eq(sr.i)
 583
 584             # tdo = reg[0], tdo_en = shift
 585             tdos.append((reg[0], sr_shift))
 586
 587
 588         # Assign the right tdo to the bus tdo
 589         for i, (tdo, tdo_en) in enumerate(tdos):
 590             if i == 0:
 591                 with m.If(tdo_en):
 592                     m.d.comb += self.bus.tdo.eq(tdo)
 593             else:
 594                 with m.Elif(tdo_en):
 595                     m.d.comb += self.bus.tdo.eq(tdo)
 596
 597         if len(tdos) > 0:
 598             with m.Else():
 599                 m.d.comb += self.bus.tdo.eq(tdo_jtag)
 600         else:
 601             # Always connect tdo_jtag to
 602             m.d.comb += self.bus.tdo.eq(tdo_jtag)
 603
 604
 605     def add_wishbone(self, *, ircodes, address_width, data_width,
 606                      granularity=None, domain="sync",
 607                      name=None, src_loc_at=0):
 608         """Add a wishbone interface
 609
 610         In order to allow high JTAG clock speed, data will be cached.
 611         This means that if data is output the value of the next address
 612         will be read automatically.
 613
 614         Parameters:
 615         -----------
 616         ircodes: sequence of three integer for the JTAG IR codes;
 617           they represent resp. WBADDR, WBREAD and WBREADWRITE. First code
 618           has a shift register of length 'address_width', the two other codes
 619           share a shift register of length data_width.
 620         address_width: width of the address
 621         data_width: width of the data
 622
 623         Returns:
 624         wb: nmigen_soc.wishbone.bus.Interface
 625             The Wishbone interface, is pipelined and has stall field.
 626         """
 627         if len(ircodes) != 3:
 628             raise ValueError("3 IR Codes have to be provided")
 629
 630         if name is None:
 631             name = "wb" + str(len(self._wbs))
 632         sr_addr = self.add_shiftreg(
 633             ircode=ircodes[0], length=address_width, domain=domain,
 634             name=name+"_addrsr"
 635         )
 636         sr_data = self.add_shiftreg(
 637             ircode=ircodes[1:], length=data_width, domain=domain,
 638             name=name+"_datasr"
 639         )
 640
 641         wb = WishboneInterface(data_width=data_width, addr_width=address_width,
 642                                granularity=granularity,
 643                                features={"stall", "lock", "err", "rty"},
 644                                name=name, src_loc_at=src_loc_at+1)
 645
 646         self._wbs.append((sr_addr, sr_data, wb, domain))
 647
 648         return wb
 649
 650     def _elaborate_wishbones(self, m):
 651         for sr_addr, sr_data, wb, domain in self._wbs:
 652             m.d.comb += sr_addr.i.eq(wb.adr)
 653
 654             if hasattr(wb, "sel"):
 655                 # Always selected
 656                 m.d.comb += [s.eq(1) for s in wb.sel]
 657
 658             with m.FSM(domain=domain) as fsm:
 659                 with m.State("IDLE"):
 660                     with m.If(sr_addr.oe): # WBADDR code
 661                         m.d[domain] += wb.adr.eq(sr_addr.o)
 662                         m.next = "READ"
 663                     with m.Elif(sr_data.oe[0]): # WBREAD code
 664                         # If data is
 665                         m.d[domain] += wb.adr.eq(wb.adr + 1)
 666                         m.next = "READ"
 667                     with m.Elif(sr_data.oe[1]): # WBWRITE code
 668                         m.d[domain] += wb.dat_w.eq(sr_data.o)
 669                         m.next = "WRITEREAD"
 670                 with m.State("READ"):
 671                     with m.If(~wb.stall):
 672                         m.next = "READACK"
 673                 with m.State("READACK"):
 674                     with m.If(wb.ack):
 675                         # Store read data in sr_data.i
 676                         # and keep it there til next read
 677                         m.d[domain] += sr_data.i.eq(wb.dat_r)
 678                         m.next = "IDLE"
 679                 with m.State("WRITEREAD"):
 680                     with m.If(~wb.stall):
 681                         m.next = "WRITEREADACK"
 682                 with m.State("WRITEREADACK"):
 683                     with m.If(wb.ack):
 684                         m.d[domain] += wb.adr.eq(wb.adr + 1)
 685                         m.next = "READ"
 686
 687                 m.d.comb += [
 688                     wb.cyc.eq(~fsm.ongoing("IDLE")),
 689                     wb.stb.eq(fsm.ongoing("READ") | fsm.ongoing("WRITEREAD")),
 690                     wb.we.eq(fsm.ongoing("WRITEREAD")),
 691                 ]