configs: Specify cache, dir, and mem cntrl interleaving
[gem5.git] / configs / common / Caches.py
1 # Copyright (c) 2012 ARM Limited
2 # Copyright (c) 2020 Barkhausen Institut
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14 # Copyright (c) 2006-2007 The Regents of The University of Michigan
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39
40 from __future__ import print_function
41 from __future__ import absolute_import
42
43 from m5.defines import buildEnv
44 from m5.objects import *
45
46 # Base implementations of L1, L2, IO and TLB-walker caches. There are
47 # used in the regressions and also as base components in the
48 # system-configuration scripts. The values are meant to serve as a
49 # starting point, and specific parameters can be overridden in the
50 # specific instantiations.
51
52 class L1Cache(Cache):
53 assoc = 2
54 tag_latency = 2
55 data_latency = 2
56 response_latency = 2
57 mshrs = 4
58 tgts_per_mshr = 20
59
60 class L1_ICache(L1Cache):
61 is_read_only = True
62 # Writeback clean lines as well
63 writeback_clean = True
64
65 class L1_DCache(L1Cache):
66 pass
67
68 class L2Cache(Cache):
69 assoc = 8
70 tag_latency = 20
71 data_latency = 20
72 response_latency = 20
73 mshrs = 20
74 tgts_per_mshr = 12
75 write_buffers = 8
76
77 class IOCache(Cache):
78 assoc = 8
79 tag_latency = 50
80 data_latency = 50
81 response_latency = 50
82 mshrs = 20
83 size = '1kB'
84 tgts_per_mshr = 12
85
86 class PageTableWalkerCache(Cache):
87 assoc = 2
88 tag_latency = 2
89 data_latency = 2
90 response_latency = 2
91 mshrs = 10
92 size = '1kB'
93 tgts_per_mshr = 12
94
95 # the x86 table walker actually writes to the table-walker cache
96 if buildEnv['TARGET_ISA'] in ['x86', 'riscv']:
97 is_read_only = False
98 else:
99 is_read_only = True
100 # Writeback clean lines as well
101 writeback_clean = True