1 # Copyright (c) 2012 ARM Limited
2 # Copyright (c) 2020 Barkhausen Institut
5 # The license below extends only to copyright in the software and shall
6 # not be construed as granting a license to any other intellectual
7 # property including but not limited to intellectual property relating
8 # to a hardware implementation of the functionality of the software
9 # licensed hereunder. You may use the software subject to the license
10 # terms below provided that you ensure that this notice is replicated
11 # unmodified and in its entirety in all distributions of the software,
12 # modified or unmodified, in source code or in binary form.
14 # Copyright (c) 2006-2007 The Regents of The University of Michigan
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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40 from __future__
import print_function
41 from __future__
import absolute_import
43 from m5
.defines
import buildEnv
44 from m5
.objects
import *
46 # Base implementations of L1, L2, IO and TLB-walker caches. There are
47 # used in the regressions and also as base components in the
48 # system-configuration scripts. The values are meant to serve as a
49 # starting point, and specific parameters can be overridden in the
50 # specific instantiations.
60 class L1_ICache(L1Cache
):
62 # Writeback clean lines as well
63 writeback_clean
= True
65 class L1_DCache(L1Cache
):
86 class PageTableWalkerCache(Cache
):
95 # the x86 table walker actually writes to the table-walker cache
96 if buildEnv
['TARGET_ISA'] in ['x86', 'riscv']:
100 # Writeback clean lines as well
101 writeback_clean
= True