configs: Specify cache, dir, and mem cntrl interleaving

This changeset allows setting a variable for interleaving.
That value is used together with the number of directories to
calculate numa_high_bit, which is in turn used to set up
cache, directory, and memory controller interleaving.
A similar approach is used to set xor_low_bit, and calculate
xor_high_bit for address hashing.

Change-Id: Ia342c77c59ca2e3438db218b5c399c3373618320
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28134
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 9443520ae350005e928b63902c587929adb53f4c..b530145240dba7000cd10a92b08b7fd7297dc380 100644 (file)
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -40,7 +40,8 @@ import m5.objects
 from common import ObjectList
 from common import HMC
 
-def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
+def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size,\
+                    xor_low_bit):
     """
     Helper function for creating a single memoy controller from the given
     options.  This function is invoked multiple times in config_mem function
@@ -55,7 +56,10 @@ def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
     # the details of the caches here, make an educated guess. 4 MByte
     # 4-way associative with 64 byte cache lines is 6 offset bits and
     # 14 index bits.
-    xor_low_bit = 20
+    if (xor_low_bit):
+        xor_high_bit = xor_low_bit + intlv_bits - 1
+    else:
+        xor_high_bit = 0
 
     # Create an instance so we can figure out the address
     # mapping and row-buffer size
@@ -81,8 +85,7 @@ def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
     ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
                                       intlvHighBit = \
                                           intlv_low_bit + intlv_bits - 1,
-                                      xorHighBit = \
-                                          xor_low_bit + intlv_bits - 1,
+                                      xorHighBit = xor_high_bit,
                                       intlvBits = intlv_bits,
                                       intlvMatch = i)
     return ctrl
@@ -110,6 +113,7 @@ def config_mem(options, system):
     opt_mem_ranks = getattr(options, "mem_ranks", None)
     opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
     opt_mem_channels_intlv = getattr(options, "mem_channels_intlv", 128)
+    opt_xor_low_bit = getattr(options, "xor_low_bit", 0)
 
     if opt_mem_type == "HMC_2500_1x32":
         HMChost = HMC.config_hmc_host_ctrl(options, system)
@@ -163,7 +167,7 @@ def config_mem(options, system):
     for r in system.mem_ranges:
         for i in range(nbr_mem_ctrls):
             mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
-                                       intlv_size)
+                                       intlv_size, opt_xor_low_bit)
             # Set the number of ranks based on the command-line
             # options if it was explicitly set
             if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:

diff --git a/configs/ruby/Ruby.py b/configs/ruby/Ruby.py
index e69784f9789371e708bfb69dd29a0126e4befaef..9bceaa3465b2c59c6289f9f8c9c263c5f963794b 100644 (file)
--- a/configs/ruby/Ruby.py
+++ b/configs/ruby/Ruby.py
@@ -76,6 +76,15 @@ def define_options(parser):
     parser.add_option("--numa-high-bit", type="int", default=0,
                       help="high order address bit to use for numa mapping. " \
                            "0 = highest bit, not specified = lowest bit")
+    parser.add_option("--interleaving-bits", type="int", default=0,
+                      help="number of bits to specify interleaving " \
+                           "in directory, memory controllers and caches. "
+                           "0 = not specified")
+    parser.add_option("--xor-low-bit", type="int", default=20,
+                      help="hashing bit for channel selection" \
+                           "see MemConfig for explanation of the default"\
+                           "parameter. If set to 0, xor_high_bit is also"\
+                           "set to 0.")
 
     parser.add_option("--recycle-latency", type="int", default=10,
                       help="Recycle latency for ruby controller input buffers")
@@ -86,7 +95,13 @@ def define_options(parser):
     Network.define_options(parser)
 
 def setup_memory_controllers(system, ruby, dir_cntrls, options):
-    ruby.block_size_bytes = options.cacheline_size
+    if (options.numa_high_bit):
+        block_size_bits = options.numa_high_bit + 1 - \
+                          int(math.log(options.num_dirs, 2))
+        ruby.block_size_bytes = 2 ** (block_size_bits)
+    else:
+        ruby.block_size_bytes = options.cacheline_size
+
     ruby.memory_size_bits = 48
 
     index = 0
@@ -117,7 +132,7 @@ def setup_memory_controllers(system, ruby, dir_cntrls, options):
             mem_type = ObjectList.mem_list.get(options.mem_type)
             mem_ctrl = MemConfig.create_mem_ctrl(mem_type, r, index,
                 options.num_dirs, int(math.log(options.num_dirs, 2)),
-                intlv_size)
+                intlv_size, options.xor_low_bit)
 
             if options.access_backing_store:
                 mem_ctrl.kvm_map=False