configs/common/GPUTLBConfig.py

   1 # Copyright (c) 2011-2015 Advanced Micro Devices, Inc.
   2 # All rights reserved.
   3 #
   4 # For use for simulation and test purposes only
   5 #
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  20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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  30 # POSSIBILITY OF SUCH DAMAGE.
  31
  32 from __future__ import print_function
  33 from __future__ import absolute_import
  34
  35 # Configure the TLB hierarchy
  36 # Places which would probably need to be modified if you
  37 # want a different hierarchy are specified by a <Modify here .. >'
  38 # comment
  39 import m5
  40 from m5.objects import *
  41
  42 def TLB_constructor(level):
  43
  44     constructor_call = "X86GPUTLB(size = options.L%(level)dTLBentries, \
  45             assoc = options.L%(level)dTLBassoc, \
  46             hitLatency = options.L%(level)dAccessLatency,\
  47             missLatency2 = options.L%(level)dMissLatency,\
  48             maxOutstandingReqs = options.L%(level)dMaxOutstandingReqs,\
  49             accessDistance = options.L%(level)dAccessDistanceStat,\
  50             clk_domain = SrcClockDomain(\
  51                 clock = options.GPUClock,\
  52                 voltage_domain = VoltageDomain(\
  53                     voltage = options.gpu_voltage)))" % locals()
  54     return constructor_call
  55
  56 def Coalescer_constructor(level):
  57
  58     constructor_call = "TLBCoalescer(probesPerCycle = \
  59                 options.L%(level)dProbesPerCycle, \
  60                 coalescingWindow = options.L%(level)dCoalescingWindow,\
  61                 disableCoalescing = options.L%(level)dDisableCoalescing,\
  62                 clk_domain = SrcClockDomain(\
  63                     clock = options.GPUClock,\
  64                     voltage_domain = VoltageDomain(\
  65                         voltage = options.gpu_voltage)))" % locals()
  66     return constructor_call
  67
  68 def create_TLB_Coalescer(options, my_level, my_index, TLB_name, Coalescer_name):
  69     # arguments: options, TLB level, number of private structures for this Level,
  70     # TLB name and  Coalescer name
  71     for i in range(my_index):
  72         TLB_name.append(eval(TLB_constructor(my_level)))
  73         Coalescer_name.append(eval(Coalescer_constructor(my_level)))
  74
  75 def config_tlb_hierarchy(options, system, shader_idx):
  76     n_cu = options.num_compute_units
  77     # Make this configurable now, instead of the hard coded val.  The dispatcher
  78     # is always the last item in the system.cpu list.
  79     dispatcher_idx = len(system.cpu) - 1
  80
  81     if options.TLB_config == "perLane":
  82         num_TLBs = 64 * n_cu
  83     elif options.TLB_config == "mono":
  84         num_TLBs = 1
  85     elif options.TLB_config == "perCU":
  86         num_TLBs = n_cu
  87     elif options.TLB_config == "2CU":
  88         num_TLBs = n_cu >> 1
  89     else:
  90         print("Bad option for TLB Configuration.")
  91         sys.exit(1)
  92
  93     #----------------------------------------------------------------------------------------
  94     # A visual representation of the TLB hierarchy
  95     # for ease of configuration
  96     # < Modify here the width and the number of levels if you want a different configuration >
  97     # width is the number of TLBs of the given type (i.e., D-TLB, I-TLB etc) for this level
  98     L1 = [{'name': 'sqc', 'width': options.num_sqc, 'TLBarray': [], 'CoalescerArray': []},
  99           {'name': 'dispatcher', 'width': 1, 'TLBarray': [], 'CoalescerArray': []},
 100           {'name': 'l1', 'width': num_TLBs, 'TLBarray': [], 'CoalescerArray': []}]
 101
 102     L2 = [{'name': 'l2', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}]
 103     L3 = [{'name': 'l3', 'width': 1, 'TLBarray': [], 'CoalescerArray': []}]
 104
 105     TLB_hierarchy = [L1, L2, L3]
 106
 107     #----------------------------------------------------------------------------------------
 108     # Create the hiearchy
 109     # Call the appropriate constructors and add objects to the system
 110
 111     for i in range(len(TLB_hierarchy)):
 112         hierarchy_level = TLB_hierarchy[i]
 113         level = i+1
 114         for TLB_type in hierarchy_level:
 115             TLB_index = TLB_type['width']
 116             TLB_array = TLB_type['TLBarray']
 117             Coalescer_array = TLB_type['CoalescerArray']
 118             # If the sim calls for a fixed L1 TLB size across CUs,
 119             # override the TLB entries option
 120             if options.tot_L1TLB_size:
 121                 options.L1TLBentries = options.tot_L1TLB_size / num_TLBs
 122                 if options.L1TLBassoc > options.L1TLBentries:
 123                     options.L1TLBassoc = options.L1TLBentries
 124             # call the constructors for the TLB and the Coalescer
 125             create_TLB_Coalescer(options, level, TLB_index,\
 126                 TLB_array, Coalescer_array)
 127
 128             system_TLB_name = TLB_type['name'] + '_tlb'
 129             system_Coalescer_name = TLB_type['name'] + '_coalescer'
 130
 131             # add the different TLB levels to the system
 132             # Modify here if you want to make the TLB hierarchy a child of
 133             # the shader.
 134             exec('system.%s = TLB_array' % system_TLB_name)
 135             exec('system.%s = Coalescer_array' % system_Coalescer_name)
 136
 137     #===========================================================
 138     # Specify the TLB hierarchy (i.e., port connections)
 139     # All TLBs but the last level TLB need to have a memSidePort (master)
 140     #===========================================================
 141
 142     # Each TLB is connected with its Coalescer through a single port.
 143     # There is a one-to-one mapping of TLBs to Coalescers at a given level
 144     # This won't be modified no matter what the hierarchy looks like.
 145     for i in range(len(TLB_hierarchy)):
 146         hierarchy_level = TLB_hierarchy[i]
 147         level = i+1
 148         for TLB_type in hierarchy_level:
 149             name = TLB_type['name']
 150             for index in range(TLB_type['width']):
 151                 exec('system.%s_coalescer[%d].master[0] = \
 152                         system.%s_tlb[%d].slave[0]' % \
 153                         (name, index, name, index))
 154
 155     # Connect the cpuSidePort (slave) of all the coalescers in level 1
 156     # < Modify here if you want a different configuration >
 157     for TLB_type in L1:
 158         name = TLB_type['name']
 159         num_TLBs = TLB_type['width']
 160         if name == 'l1':     # L1 D-TLBs
 161             tlb_per_cu = num_TLBs // n_cu
 162             for cu_idx in range(n_cu):
 163                 if tlb_per_cu:
 164                     for tlb in range(tlb_per_cu):
 165                         exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
 166                                 system.l1_coalescer[%d].slave[%d]' % \
 167                                 (shader_idx, cu_idx, tlb, cu_idx*tlb_per_cu+tlb, 0))
 168                 else:
 169                     exec('system.cpu[%d].CUs[%d].translation_port[%d] = \
 170                             system.l1_coalescer[%d].slave[%d]' % \
 171                             (shader_idx, cu_idx, tlb_per_cu, cu_idx / (n_cu / num_TLBs), cu_idx % (n_cu / num_TLBs)))
 172
 173         elif name == 'dispatcher': # Dispatcher TLB
 174             for index in range(TLB_type['width']):
 175                 exec('system.cpu[%d].translation_port = \
 176                         system.dispatcher_coalescer[%d].slave[0]' % \
 177                         (dispatcher_idx, index))
 178         elif name == 'sqc': # I-TLB
 179             for index in range(n_cu):
 180                 sqc_tlb_index = index / options.cu_per_sqc
 181                 sqc_tlb_port_id = index % options.cu_per_sqc
 182                 exec('system.cpu[%d].CUs[%d].sqc_tlb_port = \
 183                         system.sqc_coalescer[%d].slave[%d]' % \
 184                         (shader_idx, index, sqc_tlb_index, sqc_tlb_port_id))
 185
 186
 187     # Connect the memSidePorts (masters) of all the TLBs with the
 188     # cpuSidePorts (slaves) of the Coalescers of the next level
 189     # < Modify here if you want a different configuration >
 190     # L1 <-> L2
 191     l2_coalescer_index = 0
 192     for TLB_type in L1:
 193         name = TLB_type['name']
 194         for index in range(TLB_type['width']):
 195             exec('system.%s_tlb[%d].master[0] = \
 196                     system.l2_coalescer[0].slave[%d]' % \
 197                     (name, index, l2_coalescer_index))
 198             l2_coalescer_index += 1
 199     # L2 <-> L3
 200     system.l2_tlb[0].master[0] = system.l3_coalescer[0].slave[0]
 201
 202     return system