13 def ihex_line(address
, record_type
, data
):
14 assert len(data
) < 128
15 line
= ":%02X%04X%02X" % (len(data
), address
, record_type
)
17 check
+= address
% 256
23 line
+= "%02X" % value
24 line
+= "%02X\n" % ((256-check
)%256)
28 assert line
.startswith(":")
30 data_len
= int(line
[:2], 16)
31 address
= int(line
[2:6], 16)
32 record_type
= int(line
[6:8], 16)
34 for i
in range(data_len
):
35 data
+= "%c" % int(line
[8+2*i
:10+2*i
], 16)
36 return record_type
, address
, data
38 class DeleteServer(unittest
.TestCase
):
42 class SimpleRegisterTest(DeleteServer
):
44 self
.server
= target
.server()
45 self
.gdb
= testlib
.Gdb()
46 self
.gdb
.command("target extended-remote localhost:%d" % self
.server
.port
)
49 self
.gdb
.command("p *((int*) 0x%x)=0x13" % target
.ram
)
50 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 4))
51 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 8))
52 self
.gdb
.p("$pc=0x%x" % target
.ram
)
54 def check_reg(self
, name
):
55 a
= random
.randrange(1<<target
.xlen
)
56 b
= random
.randrange(1<<target
.xlen
)
57 self
.gdb
.p("$%s=0x%x" % (name
, a
))
59 self
.assertEqual(self
.gdb
.p("$%s" % name
), a
)
60 self
.gdb
.p("$%s=0x%x" % (name
, b
))
62 self
.assertEqual(self
.gdb
.p("$%s" % name
), b
)
65 # S0 is saved/restored in DSCRATCH
69 # S1 is saved/restored in Debug RAM
73 # T0 is not saved/restored at all
77 # T2 is not saved/restored at all
80 class SimpleMemoryTest(DeleteServer
):
82 self
.server
= target
.server()
83 self
.gdb
= testlib
.Gdb()
84 self
.gdb
.command("target extended-remote localhost:%d" % self
.server
.port
)
86 def access_test(self
, size
, data_type
):
87 a
= 0x86753095555aaaa & ((1<<(size
*8))-1)
88 b
= 0xdeadbeef12345678 & ((1<<(size
*8))-1)
89 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, target
.ram
, a
))
90 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, target
.ram
+ size
, b
))
91 self
.assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, target
.ram
)), a
)
92 self
.assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, target
.ram
+ size
)), b
)
95 self
.access_test(1, 'char')
98 self
.access_test(2, 'short')
101 self
.access_test(4, 'long')
104 self
.access_test(8, 'long long')
106 def test_block(self
):
109 fd
= file("write.ihex", "w")
111 for i
in range(length
/ line_length
):
112 line_data
= "".join(["%c" % random
.randrange(256) for _
in range(line_length
)])
114 fd
.write(ihex_line(i
* line_length
, 0, line_data
))
117 self
.gdb
.command("restore write.ihex 0x%x" % target
.ram
)
118 for offset
in range(0, length
, 19*4) + [length
-4]:
119 value
= self
.gdb
.p("*((long*)0x%x)" % (target
.ram
+ offset
))
120 written
= ord(data
[offset
]) | \
121 (ord(data
[offset
+1]) << 8) | \
122 (ord(data
[offset
+2]) << 16) | \
123 (ord(data
[offset
+3]) << 24)
124 self
.assertEqual(value
, written
)
126 self
.gdb
.command("dump ihex memory read.ihex 0x%x 0x%x" % (target
.ram
,
127 target
.ram
+ length
))
128 for line
in file("read.ihex"):
129 record_type
, address
, line_data
= ihex_parse(line
)
130 if (record_type
== 0):
131 self
.assertEqual(line_data
, data
[address
:address
+len(line_data
)])
133 class InstantHaltTest(DeleteServer
):
135 self
.server
= target
.server()
136 self
.gdb
= testlib
.Gdb()
137 self
.gdb
.command("target extended-remote localhost:%d" % self
.server
.port
)
139 def test_instant_halt(self
):
140 self
.assertEqual(0x1000, self
.gdb
.p("$pc"))
141 # For some reason instret resets to 0.
142 self
.assertLess(self
.gdb
.p("$instret"), 8)
144 self
.assertNotEqual(0x1000, self
.gdb
.p("$pc"))
146 def test_change_pc(self
):
147 """Change the PC right as we come out of reset."""
149 self
.gdb
.command("p *((int*) 0x%x)=0x13" % target
.ram
)
150 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 4))
151 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (target
.ram
+ 8))
152 self
.gdb
.p("$pc=0x%x" % target
.ram
)
154 self
.assertEqual((target
.ram
+ 4), self
.gdb
.p("$pc"))
156 self
.assertEqual((target
.ram
+ 8), self
.gdb
.p("$pc"))
158 class DebugTest(DeleteServer
):
160 self
.binary
= target
.compile("programs/debug.c", "programs/checksum.c")
161 self
.server
= target
.server()
162 self
.gdb
= testlib
.Gdb()
163 self
.gdb
.command("file %s" % self
.binary
)
164 self
.gdb
.command("target extended-remote localhost:%d" % self
.server
.port
)
169 output
= self
.gdb
.c()
170 self
.assertIn("Breakpoint", output
)
171 #TODO self.assertIn("_exit", output)
172 #TODO self.assertEqual(self.gdb.p("status"), 0xc86455d4)
173 # Use a0 until gdb can resolve "status"
174 self
.assertEqual(self
.gdb
.p("$a0") & 0xffffffff, 0xc86455d4)
176 def test_turbostep(self
):
177 """Single step a bunch of times."""
178 self
.gdb
.command("p i=0");
184 pc
= self
.gdb
.p("$pc")
185 self
.assertNotEqual(last_pc
, pc
)
186 if (last_pc
and pc
> last_pc
and pc
- last_pc
<= 4):
191 # Some basic sanity that we're not running between breakpoints or
193 self
.assertGreater(jumps
, 10)
194 self
.assertGreater(advances
, 50)
199 def test_symbols(self
):
202 output
= self
.gdb
.c()
203 self
.assertIn(", main ", output
)
204 output
= self
.gdb
.c()
205 self
.assertIn(", rot13 ", output
)
207 def test_breakpoint(self
):
209 # The breakpoint should be hit exactly 2 times.
211 output
= self
.gdb
.c()
213 self
.assertIn("Breakpoint ", output
)
214 #TODO self.assertIn("rot13 ", output)
217 def test_hwbp_1(self
):
218 self
.gdb
.hbreak("rot13")
219 # The breakpoint should be hit exactly 2 times.
221 output
= self
.gdb
.c()
223 self
.assertIn("Breakpoint ", output
)
224 #TODO self.assertIn("rot13 ", output)
227 def test_hwbp_2(self
):
228 self
.gdb
.hbreak("main")
229 self
.gdb
.hbreak("rot13")
230 # We should hit 3 breakpoints.
232 output
= self
.gdb
.c()
234 self
.assertIn("Breakpoint ", output
)
235 #TODO self.assertIn("rot13 ", output)
238 def test_too_many_hwbp(self
):
240 self
.gdb
.hbreak("*rot13 + %d" % (i
* 4))
242 output
= self
.gdb
.c()
243 self
.assertIn("Cannot insert hardware breakpoint", output
)
245 def test_registers(self
):
246 # Get to a point in the code where some registers have actually been
251 # Try both forms to test gdb.
252 for cmd
in ("info all-registers", "info registers all"):
253 output
= self
.gdb
.command(cmd
)
254 self
.assertNotIn("Could not", output
)
255 for reg
in ('zero', 'ra', 'sp', 'gp', 'tp'):
256 self
.assertIn(reg
, output
)
259 # mcpuid is one of the few registers that should have the high bit set
261 # Leave this commented out until gdb and spike agree on the encoding of
262 # mcpuid (which is going to be renamed to misa in any case).
263 #self.assertRegexpMatches(output, ".*mcpuid *0x80")
266 # The instret register should always be changing.
269 # instret = self.gdb.p("$instret")
270 # self.assertNotEqual(instret, last_instret)
271 # last_instret = instret
276 def test_interrupt(self
):
277 """Sending gdb ^C while the program is running should cause it to halt."""
278 self
.gdb
.b("main:start")
281 self
.gdb
.c(wait
=False)
283 output
= self
.gdb
.interrupt()
284 #TODO: assert "main" in output
285 self
.assertGreater(self
.gdb
.p("j"), 10)
289 class StepTest(DeleteServer
):
291 self
.binary
= target
.compile("programs/step.S")
292 self
.server
= target
.server()
293 self
.gdb
= testlib
.Gdb()
294 self
.gdb
.command("file %s" % self
.binary
)
295 self
.gdb
.command("target extended-remote localhost:%d" % self
.server
.port
)
301 main
= self
.gdb
.p("$pc")
302 for expected
in (4, 0xc, 0x10, 0x18, 0x14, 0x14):
304 pc
= self
.gdb
.p("$pc")
305 self
.assertEqual(pc
- main
, expected
)
307 class RegsTest(DeleteServer
):
309 self
.binary
= target
.compile("programs/regs.S")
310 self
.server
= target
.server()
311 self
.gdb
= testlib
.Gdb()
312 self
.gdb
.command("file %s" % self
.binary
)
313 self
.gdb
.command("target extended-remote localhost:%d" % self
.server
.port
)
316 self
.gdb
.b("handle_trap")
319 def test_write_gprs(self
):
320 regs
= [("x%d" % n
) for n
in range(2, 32)]
322 self
.gdb
.p("$pc=write_regs")
323 for i
, r
in enumerate(regs
):
324 self
.gdb
.command("p $%s=%d" % (r
, (0xdeadbeef<<i
)+17))
325 self
.gdb
.command("p $x1=data")
326 self
.gdb
.command("b all_done")
327 output
= self
.gdb
.c()
328 self
.assertIn("Breakpoint ", output
)
330 # Just to get this data in the log.
331 self
.gdb
.command("x/30gx data")
332 self
.gdb
.command("info registers")
333 for n
in range(len(regs
)):
334 self
.assertEqual(self
.gdb
.x("data+%d" % (8*n
), 'g'),
335 ((0xdeadbeef<<n
)+17) & ((1<<target
.xlen
)-1))
337 def test_write_csrs(self
):
338 # As much a test of gdb as of the simulator.
339 self
.gdb
.p("$mscratch=0")
341 self
.assertEqual(self
.gdb
.p("$mscratch"), 0)
342 self
.gdb
.p("$mscratch=123")
344 self
.assertEqual(self
.gdb
.p("$mscratch"), 123)
346 self
.gdb
.command("p $pc=write_regs")
347 self
.gdb
.command("p $a0=data")
348 self
.gdb
.command("b all_done")
349 self
.gdb
.command("c")
351 self
.assertEqual(123, self
.gdb
.p("$mscratch"))
352 self
.assertEqual(123, self
.gdb
.p("$x1"))
353 self
.assertEqual(123, self
.gdb
.p("$csr832"))
355 class DownloadTest(DeleteServer
):
357 length
= min(2**20, target
.ram_size
- 2048)
358 fd
= file("download.c", "w")
359 fd
.write("#include <stdint.h>\n")
360 fd
.write("unsigned int crc32a(uint8_t *message, unsigned int size);\n")
361 fd
.write("uint32_t length = %d;\n" % length
)
362 fd
.write("uint8_t d[%d] = {\n" % length
)
364 for i
in range(length
/ 16):
365 fd
.write(" /* 0x%04x */ " % (i
* 16));
367 value
= random
.randrange(1<<8)
368 fd
.write("%d, " % value
)
369 self
.crc
= binascii
.crc32("%c" % value
, self
.crc
)
372 fd
.write("uint8_t *data = &d[0];\n");
373 fd
.write("uint32_t main() { return crc32a(data, length); }\n")
379 self
.binary
= target
.compile("download.c", "programs/checksum.c")
380 self
.server
= target
.server()
381 self
.gdb
= testlib
.Gdb()
382 self
.gdb
.command("file %s" % self
.binary
)
383 self
.gdb
.command("target extended-remote localhost:%d" % self
.server
.port
)
385 def test_download(self
):
386 output
= self
.gdb
.load()
387 self
.gdb
.command("b _exit")
389 self
.assertEqual(self
.gdb
.p("status"), self
.crc
)
391 class MprvTest(DeleteServer
):
393 self
.binary
= target
.compile("programs/mprv.S")
394 self
.server
= target
.server()
395 self
.gdb
= testlib
.Gdb()
396 self
.gdb
.command("file %s" % self
.binary
)
397 self
.gdb
.command("target extended-remote localhost:%d" % self
.server
.port
)
401 """Test that the debugger can access memory when MPRV is set."""
402 self
.gdb
.c(wait
=False)
405 output
= self
.gdb
.command("p/x *(int*)(((char*)&data)-0x80000000)")
406 self
.assertIn("0xbead", output
)
408 class Target(object):
412 raise NotImplementedError
414 def compile(self
, *sources
):
415 return testlib
.compile(sources
+
416 ("programs/entry.S", "programs/init.c",
418 "-T", "targets/%s/link.lds" % (self
.directory
or self
.name
),
420 "-mcmodel=medany"), xlen
=self
.xlen
)
422 class Spike64Target(Target
):
426 ram_size
= 5 * 1024 * 1024
429 return testlib
.Spike(parsed
.cmd
, halted
=True)
431 class Spike32Target(Target
):
436 ram_size
= 5 * 1024 * 1024
439 return testlib
.Spike(parsed
.cmd
, halted
=True, xlen
=32)
441 class MicroSemiTarget(Target
):
448 return testlib
.Openocd(cmd
=parsed
.cmd
,
449 config
="targets/%s/openocd.cfg" % self
.name
)
458 parser
= argparse
.ArgumentParser(
460 Example command line from the real world:
461 Run all RegsTest cases against a MicroSemi m2gl_m2s board, with custom openocd command:
462 ./gdbserver.py --m2gl_m2s --cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" -- -vf RegsTest
464 group
= parser
.add_mutually_exclusive_group(required
=True)
466 group
.add_argument("--%s" % t
.name
, action
="store_const", const
=t
,
468 parser
.add_argument("--cmd",
469 help="The command to use to start the debug server.")
470 parser
.add_argument("unittest", nargs
="*")
472 parsed
= parser
.parse_args()
475 target
= parsed
.target()
476 unittest
.main(argv
=[sys
.argv
[0]] + parsed
.unittest
)
478 # TROUBLESHOOTING TIPS
479 # If a particular test fails, run just that one test, eg.:
480 # ./tests/gdbserver.py MprvTest.test_mprv
481 # Then inspect gdb.log and spike.log to see what happened in more detail.
483 if __name__
== '__main__':