13 from testlib
import assertEqual
, assertNotEqual
, assertIn
, assertNotIn
14 from testlib
import assertGreater
, assertRegexpMatches
, assertLess
15 from testlib
import GdbTest
, GdbSingleHartTest
, TestFailed
, assertTrue
17 MSTATUS_UIE
= 0x00000001
18 MSTATUS_SIE
= 0x00000002
19 MSTATUS_HIE
= 0x00000004
20 MSTATUS_MIE
= 0x00000008
21 MSTATUS_UPIE
= 0x00000010
22 MSTATUS_SPIE
= 0x00000020
23 MSTATUS_HPIE
= 0x00000040
24 MSTATUS_MPIE
= 0x00000080
25 MSTATUS_SPP
= 0x00000100
26 MSTATUS_HPP
= 0x00000600
27 MSTATUS_MPP
= 0x00001800
28 MSTATUS_FS
= 0x00006000
29 MSTATUS_XS
= 0x00018000
30 MSTATUS_MPRV
= 0x00020000
31 MSTATUS_PUM
= 0x00040000
32 MSTATUS_MXR
= 0x00080000
33 MSTATUS_VM
= 0x1F000000
34 MSTATUS32_SD
= 0x80000000
35 MSTATUS64_SD
= 0x8000000000000000
37 # pylint: disable=abstract-method
39 def ihex_line(address
, record_type
, data
):
40 assert len(data
) < 128
41 line
= ":%02X%04X%02X" % (len(data
), address
, record_type
)
43 check
+= address
% 256
49 line
+= "%02X" % value
50 line
+= "%02X\n" % ((256-check
)%256)
54 assert line
.startswith(":")
56 data_len
= int(line
[:2], 16)
57 address
= int(line
[2:6], 16)
58 record_type
= int(line
[6:8], 16)
60 for i
in range(data_len
):
61 data
+= "%c" % int(line
[8+2*i
:10+2*i
], 16)
62 return record_type
, address
, data
64 def readable_binary_string(s
):
65 return "".join("%02x" % ord(c
) for c
in s
)
67 class SimpleRegisterTest(GdbTest
):
68 def check_reg(self
, name
, alias
):
69 a
= random
.randrange(1<<self
.hart
.xlen
)
70 b
= random
.randrange(1<<self
.hart
.xlen
)
71 self
.gdb
.p("$%s=0x%x" % (name
, a
))
72 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
74 assertEqual(self
.gdb
.p("$%s" % name
), a
)
75 assertEqual(self
.gdb
.p("$%s" % alias
), a
)
76 self
.gdb
.p("$%s=0x%x" % (alias
, b
))
77 assertEqual(self
.gdb
.p("$%s" % name
), b
)
79 assertEqual(self
.gdb
.p("$%s" % name
), b
)
80 assertEqual(self
.gdb
.p("$%s" % alias
), b
)
84 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
85 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
86 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
87 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 12))
88 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 16))
89 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
91 class SimpleS0Test(SimpleRegisterTest
):
93 self
.check_reg("s0", "x8")
95 class SimpleS1Test(SimpleRegisterTest
):
97 self
.check_reg("s1", "x9")
99 class SimpleT0Test(SimpleRegisterTest
):
101 self
.check_reg("t0", "x5")
103 class SimpleT1Test(SimpleRegisterTest
):
105 self
.check_reg("t1", "x6")
107 class SimpleF18Test(SimpleRegisterTest
):
108 def check_reg(self
, name
, alias
):
109 if self
.hart
.extensionSupported('F'):
110 self
.gdb
.p_raw("$mstatus=$mstatus | 0x00006000")
114 self
.gdb
.p_raw("$%s=%f" % (name
, a
))
115 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
117 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - a
), .001)
118 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - a
), .001)
119 self
.gdb
.p_raw("$%s=%f" % (alias
, b
))
120 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
122 assertLess(abs(float(self
.gdb
.p_raw("$%s" % name
)) - b
), .001)
123 assertLess(abs(float(self
.gdb
.p_raw("$%s" % alias
)) - b
), .001)
125 size
= self
.gdb
.p("sizeof($%s)" % name
)
126 if self
.hart
.extensionSupported('D'):
131 output
= self
.gdb
.p_raw("$" + name
)
132 assertEqual(output
, "void")
133 output
= self
.gdb
.p_raw("$" + alias
)
134 assertEqual(output
, "void")
137 self
.check_reg("f18", "fs2")
139 class SimpleNoExistTest(GdbTest
):
142 self
.gdb
.p("$csr2288")
143 assert False, "Reading csr2288 should have failed"
144 except testlib
.CouldNotFetch
:
147 self
.gdb
.p("$csr2288=5")
148 assert False, "Writing csr2288 should have failed"
149 except testlib
.CouldNotFetch
:
152 class SimpleMemoryTest(GdbTest
):
153 def access_test(self
, size
, data_type
):
154 assertEqual(self
.gdb
.p("sizeof(%s)" % data_type
), size
)
155 a
= 0x86753095555aaaa & ((1<<(size
*8))-1)
156 b
= 0xdeadbeef12345678 & ((1<<(size
*8))-1)
157 addrA
= self
.hart
.ram
158 addrB
= self
.hart
.ram
+ self
.hart
.ram_size
- size
159 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrA
, a
))
160 self
.gdb
.p("*((%s*)0x%x) = 0x%x" % (data_type
, addrB
, b
))
161 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrA
)), a
)
162 assertEqual(self
.gdb
.p("*((%s*)0x%x)" % (data_type
, addrB
)), b
)
164 class MemTest8(SimpleMemoryTest
):
166 self
.access_test(1, 'char')
168 class MemTest16(SimpleMemoryTest
):
170 self
.access_test(2, 'short')
172 class MemTest32(SimpleMemoryTest
):
174 self
.access_test(4, 'int')
176 class MemTest64(SimpleMemoryTest
):
178 self
.access_test(8, 'long long')
180 # FIXME: I'm not passing back invalid addresses correctly in read/write memory.
181 #class MemTestReadInvalid(SimpleMemoryTest):
183 # # This test relies on 'gdb_report_data_abort enable' being executed in
184 # # the openocd.cfg file.
186 # self.gdb.p("*((int*)0xdeadbeef)")
187 # assert False, "Read should have failed."
188 # except testlib.CannotAccess as e:
189 # assertEqual(e.address, 0xdeadbeef)
190 # self.gdb.p("*((int*)0x%x)" % self.hart.ram)
192 #class MemTestWriteInvalid(SimpleMemoryTest):
194 # # This test relies on 'gdb_report_data_abort enable' being executed in
195 # # the openocd.cfg file.
197 # self.gdb.p("*((int*)0xdeadbeef)=8675309")
198 # assert False, "Write should have failed."
199 # except testlib.CannotAccess as e:
200 # assertEqual(e.address, 0xdeadbeef)
201 # self.gdb.p("*((int*)0x%x)=6874742" % self.hart.ram)
203 class MemTestBlock(GdbTest
):
208 a
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
210 for i
in range(self
.length
/ self
.line_length
):
211 line_data
= "".join(["%c" % random
.randrange(256)
212 for _
in range(self
.line_length
)])
214 a
.write(ihex_line(i
* self
.line_length
, 0, line_data
))
217 self
.gdb
.command("shell cat %s" % a
.name
)
218 self
.gdb
.command("restore %s 0x%x" % (a
.name
, self
.hart
.ram
))
220 for offset
in range(0, self
.length
, increment
) + [self
.length
-4]:
221 value
= self
.gdb
.p("*((int*)0x%x)" % (self
.hart
.ram
+ offset
))
222 written
= ord(data
[offset
]) | \
223 (ord(data
[offset
+1]) << 8) | \
224 (ord(data
[offset
+2]) << 16) | \
225 (ord(data
[offset
+3]) << 24)
226 assertEqual(value
, written
)
228 b
= tempfile
.NamedTemporaryFile(suffix
=".ihex")
229 self
.gdb
.command("dump ihex memory %s 0x%x 0x%x" % (b
.name
,
230 self
.hart
.ram
, self
.hart
.ram
+ self
.length
))
231 self
.gdb
.command("shell cat %s" % b
.name
)
232 for line
in b
.xreadlines():
233 record_type
, address
, line_data
= ihex_parse(line
)
235 written_data
= data
[address
:address
+len(line_data
)]
236 if line_data
!= written_data
:
238 "Data mismatch at 0x%x; wrote %s but read %s" % (
239 address
, readable_binary_string(written_data
),
240 readable_binary_string(line_data
)))
242 class InstantHaltTest(GdbTest
):
244 """Assert that reset is really resetting what it should."""
245 self
.gdb
.command("monitor reset halt")
246 self
.gdb
.command("flushregs")
247 threads
= self
.gdb
.threads()
251 pcs
.append(self
.gdb
.p("$pc"))
253 assertIn(pc
, self
.hart
.reset_vectors
)
254 # mcycle and minstret have no defined reset value.
255 mstatus
= self
.gdb
.p("$mstatus")
256 assertEqual(mstatus
& (MSTATUS_MIE | MSTATUS_MPRV |
259 class InstantChangePc(GdbTest
):
261 """Change the PC right as we come out of reset."""
263 self
.gdb
.command("monitor reset halt")
264 self
.gdb
.command("flushregs")
265 self
.gdb
.command("p *((int*) 0x%x)=0x13" % self
.hart
.ram
)
266 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 4))
267 self
.gdb
.command("p *((int*) 0x%x)=0x13" % (self
.hart
.ram
+ 8))
268 self
.gdb
.p("$pc=0x%x" % self
.hart
.ram
)
270 assertEqual((self
.hart
.ram
+ 4), self
.gdb
.p("$pc"))
272 assertEqual((self
.hart
.ram
+ 8), self
.gdb
.p("$pc"))
274 class DebugTest(GdbSingleHartTest
):
275 # Include malloc so that gdb can make function calls. I suspect this malloc
276 # will silently blow through the memory set aside for it, so be careful.
277 compile_args
= ("programs/debug.c", "programs/checksum.c",
278 "programs/tiny-malloc.c", "-DDEFINE_MALLOC", "-DDEFINE_FREE")
284 def exit(self
, expected_result
=0xc86455d4):
285 output
= self
.gdb
.c()
286 assertIn("Breakpoint", output
)
287 assertIn("_exit", output
)
288 assertEqual(self
.gdb
.p("status"), expected_result
)
290 class DebugCompareSections(DebugTest
):
292 output
= self
.gdb
.command("compare-sections")
294 for line
in output
.splitlines():
295 if line
.startswith("Section"):
296 assert line
.endswith("matched.")
298 assertGreater(matched
, 1)
300 class DebugFunctionCall(DebugTest
):
302 self
.gdb
.b("main:start")
304 assertEqual(self
.gdb
.p('fib(6)'), 8)
305 assertEqual(self
.gdb
.p('fib(7)'), 13)
308 class DebugChangeString(DebugTest
):
310 text
= "This little piggy went to the market."
311 self
.gdb
.b("main:start")
313 self
.gdb
.p('fox = "%s"' % text
)
314 self
.exit(0x43b497b8)
316 class DebugTurbostep(DebugTest
):
318 """Single step a bunch of times."""
319 self
.gdb
.b("main:start")
321 self
.gdb
.command("p i=0")
327 pc
= self
.gdb
.p("$pc")
328 assertNotEqual(last_pc
, pc
)
329 if last_pc
and pc
> last_pc
and pc
- last_pc
<= 4:
334 # Some basic sanity that we're not running between breakpoints or
336 assertGreater(jumps
, 1)
337 assertGreater(advances
, 5)
339 class DebugExit(DebugTest
):
343 class DebugSymbols(DebugTest
):
347 output
= self
.gdb
.c()
348 assertIn(", main ", output
)
349 output
= self
.gdb
.c()
350 assertIn(", rot13 ", output
)
352 class DebugBreakpoint(DebugTest
):
357 # The breakpoint should be hit exactly 2 times.
359 output
= self
.gdb
.c()
361 assertIn("Breakpoint ", output
)
362 assertIn("rot13 ", output
)
365 class Hwbp1(DebugTest
):
367 if self
.hart
.instruction_hardware_breakpoint_count
< 1:
368 return 'not_applicable'
370 if not self
.hart
.honors_tdata1_hmode
:
371 # Run to main before setting the breakpoint, because startup code
372 # will otherwise clear the trigger that we set.
376 self
.gdb
.hbreak("rot13")
377 # The breakpoint should be hit exactly 2 times.
379 output
= self
.gdb
.c()
381 assertRegexpMatches(output
, r
"[bB]reakpoint")
382 assertIn("rot13 ", output
)
385 class Hwbp2(DebugTest
):
387 if self
.hart
.instruction_hardware_breakpoint_count
< 2:
388 return 'not_applicable'
390 self
.gdb
.hbreak("main")
391 self
.gdb
.hbreak("rot13")
392 # We should hit 3 breakpoints.
393 for expected
in ("main", "rot13", "rot13"):
394 output
= self
.gdb
.c()
396 assertRegexpMatches(output
, r
"[bB]reakpoint")
397 assertIn("%s " % expected
, output
)
400 class TooManyHwbp(DebugTest
):
403 self
.gdb
.hbreak("*rot13 + %d" % (i
* 4))
405 output
= self
.gdb
.c()
406 assertIn("Cannot insert hardware breakpoint", output
)
407 # Clean up, otherwise the hardware breakpoints stay set and future
409 self
.gdb
.command("D")
411 class Registers(DebugTest
):
413 # Get to a point in the code where some registers have actually been
418 # Try both forms to test gdb.
419 for cmd
in ("info all-registers", "info registers all"):
420 output
= self
.gdb
.command(cmd
)
421 for reg
in ('zero', 'ra', 'sp', 'gp', 'tp'):
422 assertIn(reg
, output
)
423 for line
in output
.splitlines():
424 assertRegexpMatches(line
, r
"^\S")
427 # mcpuid is one of the few registers that should have the high bit set
429 # Leave this commented out until gdb and spike agree on the encoding of
430 # mcpuid (which is going to be renamed to misa in any case).
431 #assertRegexpMatches(output, ".*mcpuid *0x80")
434 # The instret register should always be changing.
437 # instret = self.gdb.p("$instret")
438 # assertNotEqual(instret, last_instret)
439 # last_instret = instret
444 class UserInterrupt(DebugTest
):
446 """Sending gdb ^C while the program is running should cause it to
448 self
.gdb
.b("main:start")
451 self
.gdb
.c(wait
=False)
453 output
= self
.gdb
.interrupt()
454 assert "main" in output
455 assertGreater(self
.gdb
.p("j"), 10)
459 class InterruptTest(GdbSingleHartTest
):
460 compile_args
= ("programs/interrupt.c",)
462 def early_applicable(self
):
463 return self
.target
.supports_clint_mtime
470 output
= self
.gdb
.c()
471 assertIn(" main ", output
)
472 self
.gdb
.b("trap_entry")
473 output
= self
.gdb
.c()
474 assertIn(" trap_entry ", output
)
475 assertEqual(self
.gdb
.p("$mip") & 0x80, 0x80)
476 assertEqual(self
.gdb
.p("interrupt_count"), 0)
477 # You'd expect local to still be 0, but it looks like spike doesn't
478 # jump to the interrupt handler immediately after the write to
480 assertLess(self
.gdb
.p("local"), 1000)
481 self
.gdb
.command("delete breakpoints")
483 self
.gdb
.c(wait
=False)
486 interrupt_count
= self
.gdb
.p("interrupt_count")
487 local
= self
.gdb
.p("local")
488 if interrupt_count
> 1000 and \
492 assertGreater(interrupt_count
, 1000)
493 assertGreater(local
, 1000)
495 def postMortem(self
):
496 GdbSingleHartTest
.postMortem(self
)
497 self
.gdb
.p("*((long long*) 0x200bff8)")
498 self
.gdb
.p("*((long long*) 0x2004000)")
499 self
.gdb
.p("interrupt_count")
502 class MulticoreRegTest(GdbTest
):
503 compile_args
= ("programs/infinite_loop.S", "-DMULTICORE")
505 def early_applicable(self
):
506 return len(self
.target
.harts
) > 1
510 for hart
in self
.target
.harts
:
511 self
.gdb
.select_hart(hart
)
512 self
.gdb
.p("$pc=_start")
516 for hart
in self
.target
.harts
:
517 self
.gdb
.select_hart(hart
)
520 assertIn("main", self
.gdb
.where())
521 self
.gdb
.command("delete breakpoints")
523 # Run through the entire loop.
524 for hart
in self
.target
.harts
:
525 self
.gdb
.select_hart(hart
)
526 self
.gdb
.b("main_end")
528 assertIn("main_end", self
.gdb
.where())
531 for hart
in self
.target
.harts
:
532 self
.gdb
.select_hart(hart
)
533 # Check register values.
534 hart_id
= self
.gdb
.p("$x1")
535 assertNotIn(hart_id
, hart_ids
)
536 hart_ids
.append(hart_id
)
537 for n
in range(2, 32):
538 value
= self
.gdb
.p("$x%d" % n
)
539 assertEqual(value
, hart_ids
[-1] + n
- 1)
541 # Confirmed that we read different register values for different harts.
542 # Write a new value to x1, and run through the add sequence again.
544 for hart
in self
.target
.harts
:
545 self
.gdb
.select_hart(hart
)
546 self
.gdb
.p("$x1=0x%x" % (hart
.index
* 0x800))
547 self
.gdb
.p("$pc=main_post_csrr")
549 for hart
in self
.target
.harts
:
550 self
.gdb
.select_hart(hart
)
551 assertIn("main", self
.gdb
.where())
552 # Check register values.
553 for n
in range(1, 32):
554 value
= self
.gdb
.p("$x%d" % n
)
555 assertEqual(value
, hart
.index
* 0x800 + n
- 1)
557 class MulticoreRunHaltStepiTest(GdbTest
):
558 compile_args
= ("programs/multicore.c", "-DMULTICORE")
560 def early_applicable(self
):
561 return len(self
.target
.harts
) > 1
565 for hart
in self
.target
.harts
:
566 self
.gdb
.select_hart(hart
)
567 self
.gdb
.p("$pc=_start")
570 previous_hart_count
= [0 for h
in self
.target
.harts
]
571 previous_interrupt_count
= [0 for h
in self
.target
.harts
]
573 self
.gdb
.c(wait
=False)
578 self
.gdb
.p("$mstatus")
580 self
.gdb
.p("buf", fmt
="")
581 hart_count
= self
.gdb
.p("hart_count")
582 interrupt_count
= self
.gdb
.p("interrupt_count")
583 for i
, h
in enumerate(self
.target
.harts
):
584 assertGreater(hart_count
[i
], previous_hart_count
[i
])
585 assertGreater(interrupt_count
[i
], previous_interrupt_count
[i
])
586 self
.gdb
.select_hart(h
)
587 pc
= self
.gdb
.p("$pc")
589 stepped_pc
= self
.gdb
.p("$pc")
590 assertNotEqual(pc
, stepped_pc
)
592 class MulticoreRunAllHaltOne(GdbTest
):
593 compile_args
= ("programs/multicore.c", "-DMULTICORE")
595 def early_applicable(self
):
596 return len(self
.target
.harts
) > 1
599 self
.gdb
.select_hart(self
.target
.harts
[0])
601 for hart
in self
.target
.harts
:
602 self
.gdb
.select_hart(hart
)
603 self
.gdb
.p("$pc=_start")
606 if not self
.gdb
.one_hart_per_gdb():
607 return 'not_applicable'
609 # Run harts in reverse order
610 for h
in reversed(self
.target
.harts
):
611 self
.gdb
.select_hart(h
)
612 self
.gdb
.c(wait
=False)
615 # Give OpenOCD time to call poll() on both harts, which is what causes
618 self
.gdb
.p("buf", fmt
="")
620 class StepTest(GdbSingleHartTest
):
621 compile_args
= ("programs/step.S", )
629 main_address
= self
.gdb
.p("$pc")
630 if self
.hart
.extensionSupported("c"):
631 sequence
= (4, 8, 0xc, 0xe, 0x14, 0x18, 0x22, 0x1c, 0x24, 0x24)
633 sequence
= (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c)
634 for expected
in sequence
:
636 pc
= self
.gdb
.p("$pc")
637 assertEqual("%x" % (pc
- main_address
), "%x" % expected
)
639 class TriggerTest(GdbSingleHartTest
):
640 compile_args
= ("programs/trigger.S", )
648 output
= self
.gdb
.c()
649 assertIn("Breakpoint", output
)
650 assertIn("_exit", output
)
652 class TriggerExecuteInstant(TriggerTest
):
653 """Test an execute breakpoint on the first instruction executed out of
656 main_address
= self
.gdb
.p("$pc")
657 self
.gdb
.command("hbreak *0x%x" % (main_address
+ 4))
659 assertEqual(self
.gdb
.p("$pc"), main_address
+4)
661 # FIXME: Triggers aren't quite working yet
662 #class TriggerLoadAddress(TriggerTest):
664 # self.gdb.command("rwatch *((&data)+1)")
665 # output = self.gdb.c()
666 # assertIn("read_loop", output)
667 # assertEqual(self.gdb.p("$a0"),
668 # self.gdb.p("(&data)+1"))
671 class TriggerLoadAddressInstant(TriggerTest
):
672 """Test a load address breakpoint on the first instruction executed out of
675 self
.gdb
.command("b just_before_read_loop")
677 read_loop
= self
.gdb
.p("&read_loop")
678 read_again
= self
.gdb
.p("&read_again")
679 self
.gdb
.command("rwatch data")
681 # Accept hitting the breakpoint before or after the load instruction.
682 assertIn(self
.gdb
.p("$pc"), [read_loop
, read_loop
+ 4])
683 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
686 assertIn(self
.gdb
.p("$pc"), [read_again
, read_again
+ 4])
687 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
689 # FIXME: Triggers aren't quite working yet
690 #class TriggerStoreAddress(TriggerTest):
692 # self.gdb.command("watch *((&data)+3)")
693 # output = self.gdb.c()
694 # assertIn("write_loop", output)
695 # assertEqual(self.gdb.p("$a0"),
696 # self.gdb.p("(&data)+3"))
699 class TriggerStoreAddressInstant(TriggerTest
):
701 """Test a store address breakpoint on the first instruction executed out
703 self
.gdb
.command("b just_before_write_loop")
705 write_loop
= self
.gdb
.p("&write_loop")
706 self
.gdb
.command("watch data")
708 # Accept hitting the breakpoint before or after the store instruction.
709 assertIn(self
.gdb
.p("$pc"), [write_loop
, write_loop
+ 4])
710 assertEqual(self
.gdb
.p("$a0"), self
.gdb
.p("&data"))
712 class TriggerDmode(TriggerTest
):
713 def early_applicable(self
):
714 return self
.hart
.honors_tdata1_hmode
716 def check_triggers(self
, tdata1_lsbs
, tdata2
):
717 dmode
= 1 << (self
.hart
.xlen
-5)
721 if self
.hart
.xlen
== 32:
723 elif self
.hart
.xlen
== 64:
724 xlen_type
= 'long long'
726 raise NotImplementedError
731 tdata1
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
))
734 tdata2
= self
.gdb
.p("((%s *)&data)[%d]" % (xlen_type
, 2*i
+1))
739 assertEqual(tdata1
& 0xffff, tdata1_lsbs
)
740 assertEqual(tdata2
, tdata2
)
743 assertEqual(dmode_count
, 1)
748 self
.gdb
.command("hbreak write_load_trigger")
749 self
.gdb
.b("clear_triggers")
750 self
.gdb
.p("$pc=write_store_trigger")
751 output
= self
.gdb
.c()
752 assertIn("write_load_trigger", output
)
753 self
.check_triggers((1<<6) |
(1<<1), 0xdeadbee0)
754 output
= self
.gdb
.c()
755 assertIn("clear_triggers", output
)
756 self
.check_triggers((1<<6) |
(1<<0), 0xfeedac00)
758 class RegsTest(GdbSingleHartTest
):
759 compile_args
= ("programs/regs.S", )
763 self
.gdb
.b("handle_trap")
766 class WriteGprs(RegsTest
):
768 regs
= [("x%d" % n
) for n
in range(2, 32)]
770 self
.gdb
.p("$pc=write_regs")
771 for i
, r
in enumerate(regs
):
772 self
.gdb
.p("$%s=%d" % (r
, (0xdeadbeef<<i
)+17))
773 self
.gdb
.p("$x1=data")
774 self
.gdb
.command("b all_done")
775 output
= self
.gdb
.c()
776 assertIn("Breakpoint ", output
)
778 # Just to get this data in the log.
779 self
.gdb
.command("x/30gx data")
780 self
.gdb
.command("info registers")
781 for n
in range(len(regs
)):
782 assertEqual(self
.gdb
.x("data+%d" % (8*n
), 'g'),
783 ((0xdeadbeef<<n
)+17) & ((1<<self
.hart
.xlen
)-1))
785 class WriteCsrs(RegsTest
):
787 # As much a test of gdb as of the simulator.
788 self
.gdb
.p("$mscratch=0")
790 assertEqual(self
.gdb
.p("$mscratch"), 0)
791 self
.gdb
.p("$mscratch=123")
793 assertEqual(self
.gdb
.p("$mscratch"), 123)
795 self
.gdb
.p("$pc=write_regs")
796 self
.gdb
.p("$x1=data")
797 self
.gdb
.command("b all_done")
798 self
.gdb
.command("c")
800 assertEqual(123, self
.gdb
.p("$mscratch"))
801 assertEqual(123, self
.gdb
.p("$x1"))
802 assertEqual(123, self
.gdb
.p("$csr832"))
804 class DownloadTest(GdbTest
):
806 # pylint: disable=attribute-defined-outside-init
807 length
= min(2**10, self
.hart
.ram_size
- 2048)
808 self
.download_c
= tempfile
.NamedTemporaryFile(prefix
="download_",
809 suffix
=".c", delete
=False)
810 self
.download_c
.write("#include <stdint.h>\n")
811 self
.download_c
.write(
812 "unsigned int crc32a(uint8_t *message, unsigned int size);\n")
813 self
.download_c
.write("uint32_t length = %d;\n" % length
)
814 self
.download_c
.write("uint8_t d[%d] = {\n" % length
)
816 assert length
% 16 == 0
817 for i
in range(length
/ 16):
818 self
.download_c
.write(" /* 0x%04x */ " % (i
* 16))
820 value
= random
.randrange(1<<8)
821 self
.download_c
.write("0x%02x, " % value
)
822 self
.crc
= binascii
.crc32("%c" % value
, self
.crc
)
823 self
.download_c
.write("\n")
824 self
.download_c
.write("};\n")
825 self
.download_c
.write("uint8_t *data = &d[0];\n")
826 self
.download_c
.write(
827 "uint32_t main() { return crc32a(data, length); }\n")
828 self
.download_c
.flush()
833 self
.binary
= self
.target
.compile(self
.hart
, self
.download_c
.name
,
834 "programs/checksum.c")
835 self
.gdb
.command("file %s" % self
.binary
)
839 # Some hart will get there first! Let them race in RTOS mode.
840 for hart
in self
.target
.harts
:
841 self
.gdb
.select_hart(hart
)
842 self
.gdb
.p("$pc=_start")
843 self
.gdb
.command("b _exit")
846 assertEqual(self
.gdb
.p("status"), self
.crc
)
847 os
.unlink(self
.download_c
.name
)
849 #class MprvTest(GdbSingleHartTest):
850 # compile_args = ("programs/mprv.S", )
855 # """Test that the debugger can access memory when MPRV is set."""
856 # self.gdb.c(wait=False)
858 # self.gdb.interrupt()
859 # output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)")
860 # assertIn("0xbead", output)
862 class PrivTest(GdbSingleHartTest
):
863 compile_args
= ("programs/priv.S", )
865 # pylint: disable=attribute-defined-outside-init
868 misa
= self
.hart
.misa
869 self
.supported
= set()
871 self
.supported
.add(0)
873 self
.supported
.add(1)
875 self
.supported
.add(2)
876 self
.supported
.add(3)
878 class PrivRw(PrivTest
):
880 """Test reading/writing priv."""
881 # Disable physical memory protection by allowing U mode access to all
884 self
.gdb
.p("$pmpcfg0=0xf") # TOR, R, W, X
885 self
.gdb
.p("$pmpaddr0=0x%x" %
886 ((self
.hart
.ram
+ self
.hart
.ram_size
) >> 2))
887 except testlib
.CouldNotFetch
:
888 # PMP registers are optional
891 # Ensure Virtual Memory is disabled if applicable (SATP register is not
894 self
.gdb
.p("$satp=0")
895 except testlib
.CouldNotFetch
:
896 # SATP only exists if you have S mode.
899 # Leave the PC at _start, where the first 4 instructions should be
901 for privilege
in range(4):
902 self
.gdb
.p("$priv=%d" % privilege
)
904 actual
= self
.gdb
.p("$priv")
905 assertIn(actual
, self
.supported
)
906 if privilege
in self
.supported
:
907 assertEqual(actual
, privilege
)
909 class PrivChange(PrivTest
):
911 """Test that the core's privilege level actually changes."""
913 if 0 not in self
.supported
:
914 return 'not_applicable'
920 self
.gdb
.p("$priv=3")
921 main_address
= self
.gdb
.p("$pc")
923 assertEqual("%x" % self
.gdb
.p("$pc"), "%x" % (main_address
+4))
926 self
.gdb
.p("$priv=0")
928 # Should have taken an exception, so be nowhere near main.
929 pc
= self
.gdb
.p("$pc")
930 assertTrue(pc
< main_address
or pc
> main_address
+ 0x100)
934 parser
= argparse
.ArgumentParser(
935 description
="Test that gdb can talk to a RISC-V target.",
937 Example command line from the real world:
938 Run all RegsTest cases against a physical FPGA, with custom openocd command:
939 ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple
941 targets
.add_target_options(parser
)
943 testlib
.add_test_run_options(parser
)
945 # TODO: remove global
946 global parsed
# pylint: disable=global-statement
947 parsed
= parser
.parse_args()
948 target
= targets
.target(parsed
)
949 testlib
.print_log_names
= parsed
.print_log_names
951 module
= sys
.modules
[__name__
]
953 return testlib
.run_all_tests(module
, target
, parsed
)
955 # TROUBLESHOOTING TIPS
956 # If a particular test fails, run just that one test, eg.:
957 # ./gdbserver.py MprvTest.test_mprv
958 # Then inspect gdb.log and spike.log to see what happened in more detail.
960 if __name__
== '__main__':