3 """Test that OpenOCD can talk to a RISC-V target."""
10 from testlib
import assertIn
, assertEqual
12 class OpenOcdTest(testlib
.BaseTest
):
13 def __init__(self
, target
):
14 testlib
.BaseTest
.__init
__(self
, target
)
17 def early_applicable(self
):
18 return self
.target
.openocd_config
21 # pylint: disable=attribute-defined-outside-init
22 self
.cli
= testlib
.OpenocdCli()
23 self
.cli
.command("halt")
25 def write_nops(self
, count
):
26 for address
in range(self
.target
.ram
, self
.target
.ram
+ 4 * count
, 4):
28 self
.cli
.command("mww 0x%x 0x13" % address
)
30 class RegTest(OpenOcdTest
):
37 self
.cli
.command("reg x18 0x11782")
38 self
.cli
.command("step 0x%x" % self
.target
.ram
)
40 assertEqual(self
.cli
.reg("x18"), 0x11782)
42 class StepTest(OpenOcdTest
):
46 self
.cli
.command("step 0x%x" % self
.target
.ram
)
48 pc
= self
.cli
.reg("pc")
49 assertEqual(pc
, self
.target
.ram
+ 4 * (i
+1))
50 self
.cli
.command("step")
52 class ResumeTest(OpenOcdTest
):
56 self
.cli
.command("bp 0x%x 4" % (self
.target
.ram
+ 12))
57 self
.cli
.command("bp 0x%x 4" % (self
.target
.ram
+ 24))
59 self
.cli
.command("resume 0x%x" % self
.target
.ram
)
60 assertEqual(self
.cli
.reg("pc"), self
.target
.ram
+ 12)
62 self
.cli
.command("resume")
63 assertEqual(self
.cli
.reg("pc"), self
.target
.ram
+ 24)
65 self
.cli
.command("resume 0x%x" % self
.target
.ram
)
66 assertEqual(self
.cli
.reg("pc"), self
.target
.ram
+ 12)
69 parser
= argparse
.ArgumentParser(
70 description
="Test that OpenOCD can talk to a RISC-V target.")
71 targets
.add_target_options(parser
)
72 testlib
.add_test_run_options(parser
)
74 parsed
= parser
.parse_args()
76 target
= parsed
.target(parsed
.cmd
, parsed
.run
, parsed
.isolate
)
78 target
.xlen
= parsed
.xlen
80 module
= sys
.modules
[__name__
]
82 return testlib
.run_all_tests(module
, target
, parsed
)
84 if __name__
== '__main__':