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Test step over invalid instruction.
[riscv-tests.git]
/
debug
/
programs
/
step.S
1
// Test stepping over a variety of instructions.
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.global main
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main:
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la t0, trap_entry // 0, 4
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csrw mtvec, t0 // 0x8
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li t0, 5 // 0xc
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beq zero, zero, one // 0x10
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nop // 0x14
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one:
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beq zero, t0, one // 0x18
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jal two // 0x1c
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three:
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.word 0 // 0x20
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nop // 0x24
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two:
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ret // 0x28
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trap_entry:
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j trap_entry // 0x2c