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bump env
[riscv-tests.git]
/
debug
/
targets
/
SiFive
/
HiFive1.py
1
import
targets
2
3
class
HiFive1Hart
(
targets
.
Hart
):
4
xlen
=
32
5
ram
=
0x80000000
6
ram_size
=
16
*
1024
7
instruction_hardware_breakpoint_count
=
2
8
misa
=
0x40001105
9
10
class
HiFive1
(
targets
.
Target
):
11
harts
= [
HiFive1Hart
()]