12 temporary_binary
= None
17 def __init__(self
, server_cmd
, sim_cmd
, isolate
):
18 self
.server_cmd
= server_cmd
19 self
.sim_cmd
= sim_cmd
20 self
.isolate
= isolate
23 """Start the target, eg. a simulator."""
27 """Start the debug server that gdb connects to, eg. OpenOCD."""
28 if self
.openocd_config
:
29 return testlib
.Openocd(server_cmd
=self
.server_cmd
,
30 config
=self
.openocd_config
)
32 raise NotImplementedError
34 def compile(self
, *sources
):
35 binary_name
= "%s_%s-%d" % (
37 os
.path
.basename(os
.path
.splitext(sources
[0])[0]),
40 self
.temporary_binary
= tempfile
.NamedTemporaryFile(
41 prefix
=binary_name
+ "_")
42 binary_name
= self
.temporary_binary
.name
43 Target
.temporary_files
.append(self
.temporary_binary
)
44 march
= "rv%dima" % self
.xlen
47 if self
.extensionSupported("c"):
49 testlib
.compile(sources
+
50 ("programs/entry.S", "programs/init.c",
53 "-T", "targets/%s/link.lds" % (self
.directory
or self
.name
),
56 "-DXLEN=%d" % self
.xlen
,
61 def extensionSupported(self
, letter
):
62 # target.misa is set by testlib.ExamineTarget
63 return self
.misa
& (1 << (ord(letter
.upper()) - ord('A')))
65 class SpikeTarget(Target
):
66 # pylint: disable=abstract-method
70 instruction_hardware_breakpoint_count
= 4
72 openocd_config
= "targets/%s/openocd.cfg" % directory
74 class Spike64Target(SpikeTarget
):
80 return testlib
.Spike(self
.sim_cmd
)
82 class Spike32Target(SpikeTarget
):
87 return testlib
.Spike(self
.sim_cmd
, xlen
=32)
89 class FreedomE300Target(Target
):
94 instruction_hardware_breakpoint_count
= 2
95 openocd_config
= "targets/%s/openocd.cfg" % name
97 class HiFive1Target(FreedomE300Target
):
99 openocd_config
= "targets/%s/openocd.cfg" % name
101 class FreedomE300SimTarget(Target
):
102 name
= "freedom-e300-sim"
106 ram_size
= 256 * 1024 * 1024
107 instruction_hardware_breakpoint_count
= 2
108 openocd_config
= "targets/%s/openocd.cfg" % name
111 return testlib
.VcsSim(sim_cmd
=self
.sim_cmd
, debug
=False)
113 class FreedomU500Target(Target
):
114 name
= "freedom-u500"
118 instruction_hardware_breakpoint_count
= 2
119 openocd_config
= "targets/%s/openocd.cfg" % name
121 class FreedomU500SimTarget(Target
):
122 name
= "freedom-u500-sim"
126 ram_size
= 256 * 1024 * 1024
127 instruction_hardware_breakpoint_count
= 2
128 openocd_config
= "targets/%s/openocd.cfg" % name
131 return testlib
.VcsSim(sim_cmd
=self
.sim_cmd
, debug
=False)
138 FreedomE300SimTarget
,
139 FreedomU500SimTarget
,
142 def add_target_options(parser
):
143 group
= parser
.add_mutually_exclusive_group(required
=True)
145 group
.add_argument("--%s" % t
.name
, action
="store_const", const
=t
,
147 parser
.add_argument("--sim_cmd",
148 help="The command to use to start the actual target (e.g. "
150 parser
.add_argument("--server_cmd",
151 help="The command to use to start the debug server (e.g. OpenOCD)")
153 xlen_group
= parser
.add_mutually_exclusive_group()
154 xlen_group
.add_argument("--32", action
="store_const", const
=32, dest
="xlen",
155 help="Force the target to be 32-bit.")
156 xlen_group
.add_argument("--64", action
="store_const", const
=64, dest
="xlen",
157 help="Force the target to be 64-bit.")
159 parser
.add_argument("--isolate", action
="store_true",
160 help="Try to run in such a way that multiple instances can run at "
161 "the same time. This may make it harder to debug a failure if it "