1 // See LICENSE.SiFive for license details.
3 #include "spike/encoding.h"
4 #include "debug_rom_defines.h"
10 // Entry location on ebreak, Halt, or Breakpoint
11 // It is the same for all harts. They branch when
12 // their GO or RESUME bit is set.
22 // This fence is required because the execution may have written something
23 // into the Abstract Data or Program Buffer registers.
25 csrw CSR_DSCRATCH, s0 // Save s0 to allow signaling MHARTID
27 // We continue to let the hart know that we are halted in order that
28 // a DM which was reset is still made aware that a hart is halted.
29 // We keep checking both whether there is something the debugger wants
30 // us to do, or whether we should resume.
33 sw s0, DEBUG_ROM_HALTED(zero)
34 lbu s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here.
35 andi s0, s0, (1 << DEBUG_ROM_FLAG_GO)
38 lbu s0, DEBUG_ROM_FLAGS(s0) // multiple harts can resume here
39 andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME)
44 sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception.
48 csrr s0, CSR_DSCRATCH // Restore s0 here
49 sw zero, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset.
52 jalr zero, zero, %lo(whereto) // Debug module will put different instructions and data in the RAM,
53 // so we use fence and fence.i for safety. (rocket-chip doesn't have this
54 // because jalr is special there)
58 sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset.
59 csrr s0, CSR_DSCRATCH // Restore s0
62 // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT.
67 // Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer,
68 // or jal x0 resume, as desired.
69 // Debug Module state machine tracks what is 'desired'.
70 // We don't need/want to use jalr here because all of the
71 // Variable ROM contents are set by
72 // Debug Module before setting the OK_GO byte.