1 # This code should be functional. Doesn't have to be optimal.
2 # I'm writing it to prove that it can be done.
4 #include "riscv/encoding.h"
6 # TODO: Update these constants once they're finalized in the doc.
8 #define DEBUG_RAM 0x400
10 # define DEBUG_RAM_SIZE 64
13 #define CLEARDEBINT 0x100
14 #define SETHALTNOT 0x10c
16 #if (defined(RV32) + defined(RV64) + defined(RV128)) > 1
18 #elif (defined(RV32) + defined(RV64) + defined(RV128)) == 0
19 # error define one or more of RV32, RV64, RV128
26 # Automatically called when Debug Mode is first entered.
28 # Should be called by Debug RAM code that has finished execution and
29 # wants to return to Debug Mode.
33 # Set the last word of Debug RAM to all ones, to indicate that we hit
50 bltz s1, restore_not_32
54 lw s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
55 # if defined(RV64) || defined(RV128)
61 #if defined(RV64) && defined(RV128)
68 ld s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
70 #if defined(RV64) && defined(RV128)
75 lq s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
79 # s0 contains ~0 if we got here through an exception, and 0 otherwise.
80 # Store this to the last word in Debug RAM so the debugger can tell if
81 # an exception occurred.
82 sw s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
84 # Clear debug interrupt.
86 sw s0, CLEARDEBINT(zero)
90 andi s0, s0, DCSR_HALT
91 bnez s0, wait_for_interrupt
100 csrw CSR_DSCRATCH, s0
102 # Check why we're here
104 # cause is in bits 8:6 of dcsr
105 andi s0, s0, DCSR_CAUSE
106 addi s0, s0, -(DCSR_CAUSE_DEBUGINT<<6)
107 bnez s0, spontaneous_halt
110 # Save s1 so that the debug program can use two registers.
120 sw s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
125 #if defined(RV64) && defined(RV128)
132 sd s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
138 sq s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
144 sw s0, SETHALTNOT(zero)
145 csrsi CSR_DCSR, DCSR_HALT
149 andi s0, s0, DCSR_DEBUGINT
150 beqz s0, wait_for_interrupt