debug_rom/debug_rom.S

   1 // See LICENSE.SiFive for license details.
   2
   3 #include "spike/encoding.h"
   4
   5 // These are implementation-specific addresses in the Debug Module
   6 #define DEBUG_ROM_HALTED    0x100
   7 #define DEBUG_ROM_GOING     0x104
   8 #define DEBUG_ROM_RESUMING  0x108
   9 #define DEBUG_ROM_EXCEPTION 0x10C
  10
  11 // Region of memory where each hart has 1
  12 // byte to read.
  13 #define DEBUG_ROM_FLAGS 0x400
  14 #define DEBUG_ROM_FLAG_GO     0
  15 #define DEBUG_ROM_FLAG_RESUME 1
  16
  17 // These needs to match the link.ld
  18 #define DEBUG_ROM_WHERETO 0x300
  19 #define DEBUG_ROM_ENTRY   0x800
  20
  21         .option norvc
  22         .global entry
  23         .global exception
  24
  25         // Entry location on ebreak, Halt, or Breakpoint
  26         // It is the same for all harts. They branch when
  27         // their GO or RESUME bit is set.
  28
  29 entry:
  30        jal zero, _entry
  31 resume:
  32        jal zero, _resume
  33 exception:
  34        jal zero, _exception
  35
  36 _entry:
  37         // This fence is required because the execution may have written something
  38         // into the Abstract Data or Program Buffer registers.
  39         fence
  40         csrw CSR_DSCRATCH, s0  // Save s0 to allow signaling MHARTID
  41
  42         // We continue to let the hart know that we are halted in order that
  43         // a DM which was reset is still made aware that a hart is halted.
  44         // We keep checking both whether there is something the debugger wants
  45         // us to do, or whether we should resume.
  46 entry_loop:
  47         csrr s0, CSR_MHARTID
  48         sw   s0, DEBUG_ROM_HALTED(zero)
  49         lbu  s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here.
  50         andi s0, s0, (1 << DEBUG_ROM_FLAG_GO)
  51         bnez s0, going
  52         csrr s0, CSR_MHARTID
  53         lbu  s0, DEBUG_ROM_FLAGS(s0) // multiple harts can resume  here
  54         andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME)
  55         bnez s0, resume
  56         jal  zero, entry_loop
  57
  58 _exception:
  59         sw      zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception.
  60         ebreak
  61
  62 going:
  63         csrr s0, CSR_DSCRATCH          // Restore s0 here
  64         sw zero, DEBUG_ROM_GOING(zero)           // When debug module sees this write, the GO flag is reset.
  65         jalr zero, zero, %lo(whereto)          // Rocket-Chip has a specific hack which is that jalr in
  66                                        // Debug Mode will flush the I-Cache. We need that so that the
  67                                        // remainder of the variable instructions will be what Debug Module
  68                                        // intends.
  69 _resume:
  70         csrr s0, CSR_MHARTID
  71         sw   s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset.
  72         csrr s0, CSR_DSCRATCH   // Restore s0
  73         dret
  74
  75         // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT.
  76
  77 .section .whereto
  78 whereto:
  79         nop
  80         // Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer,
  81         //                or jal x0 resume, as desired.
  82         //                Debug Module state machine tracks what is 'desired'.
  83         //                We don't need/want to use jalr here because all of the
  84         //                Variable ROM contents are set by
  85         //                Debug Module before setting the OK_GO byte.