1 # This code should be functional. Doesn't have to be optimal.
2 # I'm writing it to prove that it can be done.
4 #include "riscv/encoding.h"
6 # TODO: Update these constants once they're finalized in the doc.
8 #define DEBUG_RAM 0x400
9 #define DEBUG_RAM_SIZE 64
11 #define CLEARDEBINT 0x100
12 #define SETHALTNOT 0x10c
18 # Automatically called when Debug Mode is first entered.
20 # Should be called by Debug RAM code that has finished execution and
21 # wants to return to Debug Mode.
25 # Set the last word of Debug RAM to all ones, to indicate that we hit
33 # Clear debug interrupt.
35 sw s1, CLEARDEBINT(zero)
40 bltz s1, restore_not_32
42 lw s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
48 ld s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
51 nop #lq s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
53 # s0 contains ~0 if we got here through an exception, and 0 otherwise.
54 # Store this to the last word in Debug RAM so the debugger can tell if
55 # an exception occurred.
56 sw s0, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
60 andi s0, s0, DCSR_HALT
73 # Check why we're here
75 # cause is in bits 2:0 of dcsr
76 andi s0, s0, DCSR_CAUSE
77 addi s0, s0, -DCSR_CAUSE_DEBUGINT
78 bnez s0, spontaneous_halt
81 # Save s1 so that the debug program can use two registers.
86 sw s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 4)(zero)
92 sd s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 8)(zero)
95 nop #sq s1, (DEBUG_RAM + DEBUG_RAM_SIZE - 16)(zero)
100 sw s0, SETHALTNOT(zero)
101 csrsi CSR_DCSR, DCSR_HALT
105 andi s0, s0, DCSR_DEBUGINT
106 beqz s0, wait_for_interrupt