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HEAD
Add support for virtual priv register. (#59)
[riscv-isa-sim.git]
/
debug_rom
/
link.ld
1
OUTPUT_ARCH( "riscv" )
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ENTRY( entry )
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SECTIONS
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{
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. = 0x800;
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.text :
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{
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*(.text)
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}
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_end = .;
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}