b42fb1d32bb58c89eaaac4d31c6bc6f9faa2f46e
2 from nmigen
.cli
import rtlil
5 class Adder(Elaboratable
):
6 def __init__(self
, width
):
11 def elaborate(self
, platform
):
13 m
.d
.comb
+= self
.o
.eq(self
.a
+ self
.b
)
17 class Subtractor(Elaboratable
):
18 def __init__(self
, width
):
19 self
.a
= Signal(width
)
20 self
.b
= Signal(width
)
21 self
.o
= Signal(width
)
23 def elaborate(self
, platform
):
25 m
.d
.comb
+= self
.o
.eq(self
.a
- self
.b
)
29 class ALU(Elaboratable
):
30 def __init__(self
, width
):
32 self
.a
= Signal(width
)
33 self
.b
= Signal(width
)
34 self
.o
= Signal(width
)
36 self
.add
= Adder(width
)
37 self
.sub
= Subtractor(width
)
39 def elaborate(self
, platform
):
42 #m.domains.sync = ClockDomain()
43 #m.d.comb += ClockSignal().eq(self.m_clock)
45 m
.submodules
.add
= self
.add
46 m
.submodules
.sub
= self
.sub
48 self
.add
.a
.eq(self
.a
),
49 self
.sub
.a
.eq(self
.a
),
50 self
.add
.b
.eq(self
.b
),
51 self
.sub
.b
.eq(self
.b
),
54 m
.d
.sync
+= self
.o
.eq(self
.sub
.o
)
56 m
.d
.sync
+= self
.o
.eq(self
.add
.o
)
60 def create_ilang(dut
, ports
, test_name
):
61 vl
= rtlil
.convert(dut
, name
=test_name
, ports
=ports
)
62 with
open("%s.il" % test_name
, "w") as f
:
65 if __name__
== "__main__":
67 create_ilang(alu
, [#alu.m_clock, alu.p_reset,
68 alu
.op
, alu
.a
, alu
.b
, alu
.o
], "alu_hier")