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last changeThu, 1 Jul 2021 12:03:34 +0000 (14:03 +0200)
shortlog
2021-07-01 Jean-Paul ChaputEnable the heavy leaf load on the main clock. master LS180_RC7_FINAL
2021-06-29 Jean-Paul ChaputAdd the filler setting in doDesign.py. LS180_RC6
2021-06-26 Jean-Paul ChaputReadjust the position of the SRAM after their blockage...
2021-06-18 Jean-Paul ChaputKeep track of the latest debugged nets (antenna & DRC). LS180_RC3
2021-06-18 Jean-Paul ChaputAdd logos in the bottom left corner and supress iovss...
2021-06-15 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-06-15 Luke Kenneth... add wget of libresoc gds logo
2021-06-15 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-06-15 Jean-Paul ChaputAdjust router track reservations for convergence.
2021-06-14 Luke Kenneth... add sorbonne logo to wget
2021-06-14 Luke Kenneth... hmm set spacemargin back to 0.05
2021-06-13 Luke Kenneth... experiment with same settings as benchs/6502
2021-06-12 Luke Kenneth... attempt to put together a GDSII loader file. errr...
2021-06-12 Luke Kenneth... add fetch of GDS-II files
2021-06-12 Luke Kenneth... add fetch of GDS-II files
2021-06-10 Luke Kenneth... reverse pingroup SDRAM address to get it closer to...
...
tags
10 days ago LS180_RC7_FINAL LS180 RC7 & FINAL version (CTS OK)
3 weeks ago LS180_RC6 LS180 RC6 version (TSMC valid)
5 weeks ago LS180_RC3 Version used to generate LibreSOC...
6 months ago ls180-24jan2020
7 months ago partial-core-ls180-gdsii
heads
3 weeks ago master