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wire assignments
[sv2nmigen.git]
/
examples
/
counter.sv
1
module up_counter(input logic clk,
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input logic reset,
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output[3:0] counter
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);
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reg [3:0] counter_up;
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// up counter
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always @(posedge clk or posedge reset)
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begin
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if(reset)
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counter_up <= 4'd0;
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else
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counter_up <= counter_up + 4'd1;
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end
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assign counter = counter_up;
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endmodule