experiments12/memory.py

   1 from nmigen import Elaboratable, Cat, Module, Signal, Instance
   2 from nmigen.cli import rtlil
   3
   4
   5 class ADD(Elaboratable):
   6     def __init__(self, width):
   7         self.a   = Signal(width)
   8         self.b   = Signal(width)
   9         self.f   = Signal(width)
  10
  11     def elaborate(self, platform):
  12         m = Module()
  13         result = Signal.like(self.f)
  14         m.d.sync += result.eq(self.a + self.b)
  15
  16         # 64k SRAM instance
  17         a = Signal(9)
  18         q = Signal(64) # output
  19         d = Signal(64) # input
  20         we = Signal(8)
  21         sram = Instance("SPBlock_512W64B8W", i_a=a, o_q=q, i_d=d, i_we=we)
  22         m.submodules += sram
  23
  24         # connect up some arbitrary signals
  25         m.d.comb += a.eq(Cat(self.a, self.b, self.a[0]))
  26         m.d.comb += d.eq(result)
  27         m.d.comb += self.f.eq(q)
  28
  29         return m
  30
  31
  32 def create_ilang(dut, ports, test_name):
  33     vl = rtlil.convert(dut, name=test_name, ports=ports)
  34     with open("%s.il" % test_name, "w") as f:
  35         f.write(vl)
  36
  37 if __name__ == "__main__":
  38     alu = ADD(width=4)
  39     create_ilang(alu, [alu.a, alu.b, alu.f], "memory")